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[/] [open8_urisc/] [trunk/] [VHDL/] [hd44780_4b.vhd] - Blame information for rev 301

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Line No. Rev Author Line
1 287 jshamlet
-- Copyright (c)2021 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Entity: o8_hd44780_4b
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-- Description: Provides low-level timing of the control signals in 4-bit mode
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--              (required by o8_hd44780_if)
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/12/21 Design Start
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33 286 jshamlet
library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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entity hd44780_4b is
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generic(
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  Tsu                        : integer :=  40; -- ns
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  Tpw                        : integer := 250; -- nS
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  Tcyc                       : integer := 500; -- nS
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  Clock_Frequency            : real    := 50000000.0; -- Hz
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  Reset_Level                : std_logic := '1'
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);
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port(
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  Clock                      : in  std_logic;
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  Reset                      : in  std_logic;
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  --
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  Wr_Fnset                   : in  std_logic;
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  Wr_Data                    : in  std_logic_vector(7 downto 0);
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  Wr_Reg                     : in  std_logic;
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  Wr_En                      : in  std_logic;
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  --
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  IO_Done                    : out std_logic;
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  --
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  LCD_RS                     : out std_logic;
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  LCD_E                      : out std_logic;
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  LCD_DQ                     : out std_logic_vector(7 downto 0)
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);
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end entity;
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architecture behave of hd44780_4b is
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  -- The ceil_log2 function returns the minimum register width required to
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  --  hold the supplied integer.
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  function ceil_log2 (x : in natural) return natural is
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    variable retval          : natural;
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  begin
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    retval                   := 1;
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    while ((2**retval) - 1) < x loop
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      retval                 := retval + 1;
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    end loop;
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    return retval;
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  end function;
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  constant CONV_NANOSECS     : real := 0.000000001;
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  constant Tsu_r             : real := CONV_NANOSECS * real(Tsu);
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  constant Tpw_r             : real := CONV_NANOSECS * real(Tpw);
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  constant Tcyc_r            : real := CONV_NANOSECS * real(Tcyc);
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  constant TCYC_i            : integer := integer(Clock_Frequency * Tcyc_r);
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  constant TCYC_BITS         : integer := ceil_log2(TCYC_i);
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  constant TCYC_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=
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                               conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
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  signal tcyc_timer          : std_logic_vector(TCYC_BITS - 1 downto 0) :=
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                               (others => '0');
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  constant TPW_i             : integer := integer(Clock_Frequency * Tpw_r);
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  constant TPW_DELAY         : std_logic_vector(TCYC_BITS-1 downto 0) :=
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                               conv_std_logic_vector(TPW_i-1, TCYC_BITS);
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  constant TSU_i             : integer := integer(Clock_Frequency * Tsu_r);
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  constant TSU_BITS          : integer := ceil_log2(TSU_i);
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  constant TSU_DELAY         : std_logic_vector(TSU_BITS - 1 downto 0) :=
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                               conv_std_logic_vector(TSU_i-1,TSU_BITS);
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  signal tsnh_timer          : std_logic_vector(TSU_BITS-1 downto 0) :=
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                                (others => '0');
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  type IO_STATES   is (IDLE,
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                       INIT_UB, TAS_UB, TPW_UB, TCYC_UB,
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                       INIT_LB, TPW_LB, TCYC_LB,
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                       DONE );
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  signal io_state            : IO_STATES;
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  signal fn_set              : std_logic;
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  signal Wr_Buffer           : std_logic_vector(8 downto 0);
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  alias Wr_Buffer_A          is Wr_Buffer(8);
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  alias Wr_Buffer_U          is Wr_Buffer(7 downto 4);
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  alias Wr_Buffer_L          is Wr_Buffer(3 downto 0);
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  alias LCD_DQ_U             is LCD_DQ(7 downto 4);
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  alias LCD_DQ_L             is LCD_DQ(3 downto 0);
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begin
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  LCD_IO_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      io_state               <= IDLE;
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      fn_set                 <= '0';
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      tcyc_timer             <= (others => '0');
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      tsnh_timer             <= (others => '0');
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      Wr_Buffer              <= (others => '0');
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      IO_Done                <= '0';
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      LCD_RS                 <= '0';
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      LCD_E                  <= '0';
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      LCD_DQ                 <= (others => '0');
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    elsif( rising_edge(Clock) )then
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      IO_Done                <= '0';
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      LCD_E                  <= '0';
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      LCD_DQ_L               <= (others => '0');
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      case( io_state )is
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        when IDLE =>
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          if( Wr_En = '1' )then
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            Wr_Buffer        <= Wr_Reg & Wr_Data;
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            fn_set           <= Wr_Fnset;
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            io_state         <= INIT_UB;
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          end if;
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        when INIT_UB =>
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          tsnh_timer         <= TSU_DELAY;
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          tcyc_timer         <= (others => '0');
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          LCD_RS             <= Wr_Buffer_A;
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          io_state           <= TAS_UB;
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        when TAS_UB =>
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          tsnh_timer         <= tsnh_timer - 1;
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          if( or_reduce(tsnh_timer) = '0' )then
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            io_state         <= TPW_UB;
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          end if;
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156
        when TPW_UB =>
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          tcyc_timer         <= tcyc_timer + 1;
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          LCD_E              <= '1';
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          LCD_DQ_U           <= Wr_Buffer_U;
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          if( tcyc_timer = TPW_DELAY )then
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            io_state         <= TCYC_UB;
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          end if;
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        when TCYC_UB =>
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          tcyc_timer         <= tcyc_timer + 1;
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          if( tcyc_timer >= TCYC_DELAY )then
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            io_state         <= INIT_LB;
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          end if;
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        when INIT_LB =>
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          tcyc_timer         <= (others => '0');
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          io_state           <= TPW_LB;
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          if( fn_set = '1' )then
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            fn_set           <= '0';
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            io_state         <= TPW_UB;
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          end if;
177
 
178
        when TPW_LB =>
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          tcyc_timer         <= tcyc_timer + 1;
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          LCD_E              <= '1';
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          LCD_DQ_U           <= Wr_Buffer_L;
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          if( tcyc_timer = TPW_DELAY )then
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            io_state         <= TCYC_LB;
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          end if;
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        when TCYC_LB =>
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          tcyc_timer         <= tcyc_timer + 1;
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          if( tcyc_timer >= TCYC_DELAY )then
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            io_state         <= DONE;
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          end if;
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        when DONE =>
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          IO_Done            <= '1';
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          LCD_RS             <= '0';
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          LCD_DQ_U           <= (others => '0');
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          io_state           <= IDLE;
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        when others =>
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          null;
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      end case;
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    end if;
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  end process;
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end architecture;

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