OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [hd44780_8b.vhd] - Blame information for rev 301

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 287 jshamlet
-- Copyright (c)2021 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Entity: o8_hd44780_if
25
-- Description: Provides low-level timing of the control signals in 8-bit mode
26
--              (required by o8_hd44780_if)
27
--
28
-- Revision History
29
-- Author          Date     Change
30
------------------ -------- ---------------------------------------------------
31
-- Seth Henry      04/12/21 Design Start
32
 
33 286 jshamlet
library ieee;
34
  use ieee.std_logic_1164.all;
35
  use ieee.std_logic_unsigned.all;
36
  use ieee.std_logic_arith.all;
37
  use ieee.std_logic_misc.all;
38
 
39
entity hd44780_8b is
40
generic(
41
  Tsu                        : integer :=  40; -- ns
42
  Tpw                        : integer := 250; -- nS
43
  Tcyc                       : integer := 500; -- nS
44
  Clock_Frequency            : real    := 50000000.0; -- Hz
45
  Reset_Level                : std_logic := '1'
46
);
47
port(
48
  Clock                      : in  std_logic;
49
  Reset                      : in  std_logic;
50
  --
51
  Wr_Data                    : in  std_logic_vector(7 downto 0);
52
  Wr_Reg                     : in  std_logic;
53
  Wr_En                      : in  std_logic;
54
  --
55
  IO_Done                    : out std_logic;
56
  --
57
  LCD_RS                     : out std_logic;
58
  LCD_E                      : out std_logic;
59
  LCD_DQ                     : out std_logic_vector(7 downto 0)
60
);
61
end entity;
62
 
63
architecture behave of hd44780_8b is
64
 
65
  -- The ceil_log2 function returns the minimum register width required to
66
  --  hold the supplied integer.
67
  function ceil_log2 (x : in natural) return natural is
68
    variable retval          : natural;
69
  begin
70
    retval                   := 1;
71
    while ((2**retval) - 1) < x loop
72
      retval                 := retval + 1;
73
    end loop;
74
    return retval;
75
  end function;
76
 
77
  constant CONV_NANOSECS     : real := 0.000000001;
78
 
79
  constant Tsu_r             : real := CONV_NANOSECS * real(Tsu);
80
  constant Tpw_r             : real := CONV_NANOSECS * real(Tpw);
81
  constant Tcyc_r            : real := CONV_NANOSECS * real(Tcyc);
82
 
83
  constant TCYC_i            : integer := integer(Clock_Frequency * Tcyc_r);
84
  constant TCYC_BITS         : integer := ceil_log2(TCYC_i);
85
 
86
  constant TCYC_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=
87
                               conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
88
  signal tcyc_timer          : std_logic_vector(TCYC_BITS - 1 downto 0) :=
89
                               (others => '0');
90
 
91
  constant TPW_i             : integer := integer(Clock_Frequency * Tpw_r);
92
  constant TPW_DELAY         : std_logic_vector(TCYC_BITS-1 downto 0) :=
93
                               conv_std_logic_vector(TPW_i-1, TCYC_BITS);
94
 
95
  constant TSU_i             : integer := integer(Clock_Frequency * Tsu_r);
96
  constant TSU_BITS          : integer := ceil_log2(TSU_i);
97
  constant TSU_DELAY         : std_logic_vector(TSU_BITS - 1 downto 0) :=
98
                               conv_std_logic_vector(TSU_i-1,TSU_BITS);
99
  signal tsnh_timer          : std_logic_vector(TSU_BITS-1 downto 0) :=
100
                                (others => '0');
101
 
102
  type IO_STATES   is (IDLE, INIT, IO_TAS, IO_TPW, IO_TCYC, DONE );
103
  signal io_state            : IO_STATES;
104
 
105
  signal Wr_Buffer           : std_logic_vector(8 downto 0);
106
  alias Wr_Buffer_A          is Wr_Buffer(8);
107
  alias Wr_Buffer_D          is Wr_Buffer(7 downto 0);
108
 
109
begin
110
 
111
  LCD_IO_proc: process( Clock, Reset )
112
  begin
113
    if( Reset = Reset_Level )then
114
      io_state               <= IDLE;
115
      tcyc_timer             <= (others => '0');
116
      tsnh_timer             <= (others => '0');
117
      Wr_Buffer              <= (others => '0');
118
      IO_Done                <= '0';
119
      LCD_RS                 <= '0';
120
      LCD_E                  <= '0';
121
      LCD_DQ                 <= (others => '0');
122
    elsif( rising_edge(Clock) )then
123
      IO_Done                <= '0';
124
      LCD_E                  <= '0';
125
      case( io_state )is
126
        when IDLE =>
127
          if( Wr_En = '1' )then
128
            Wr_Buffer        <= Wr_Reg & Wr_Data;
129
            io_state         <= INIT;
130
          end if;
131
 
132
        when INIT =>
133
          tsnh_timer         <= TSU_DELAY;
134
          tcyc_timer         <= (others => '0');
135
          LCD_RS             <= Wr_Buffer_A;
136
          io_state           <= IO_TAS;
137
 
138
        when IO_TAS =>
139
          tsnh_timer         <= tsnh_timer - 1;
140
          if( or_reduce(tsnh_timer) = '0' )then
141
            io_state         <= IO_TPW;
142
          end if;
143
 
144
        when IO_TPW =>
145
          tcyc_timer         <= tcyc_timer + 1;
146
          LCD_E              <= '1';
147
          LCD_DQ             <= Wr_Buffer_D;
148
          if( tcyc_timer = TPW_DELAY )then
149
            io_state         <= IO_TCYC;
150
          end if;
151
 
152
        when IO_TCYC =>
153
          tcyc_timer         <= tcyc_timer + 1;
154
          if( tcyc_timer >= TCYC_DELAY )then
155
            io_state         <= DONE;
156
          end if;
157
 
158
        when DONE =>
159
          IO_Done            <= '1';
160
          LCD_RS             <= '0';
161
          LCD_DQ             <= (others => '0');
162
          io_state           <= IDLE;
163
 
164
        when others =>
165
          null;
166
      end case;
167
    end if;
168
  end process;
169
 
170
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.