Subversion Repositories open8_urisc

-- Copyright (c)2021 Jeremy Seth Henry

-- All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution,

--       where applicable (as part of a user interface, debugging port, etc.)

--

-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--

-- VHDL Entity: o8_hd44780_if

-- Description: Provides low-level timing of the control signals in 8-bit mode

--              (required by o8_hd44780_if)

--

-- Note: This code attempts to implement the timing diagram in the HD44780U

--        LCD II datasheet with a few simplifications. Chiefly, DQ is updated

--        at the start of E, rather than attempting to assert within Tds of

--        the falling edge of E. Further, both RS and DQ are asserted until

--        the end of Tcycle, where Tcycle is defined as TcycleE + Tas

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      04/12/21 Design Start

-- Seth Henry      09/19/23 Rewrote IF to use a single cycle timer

library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

  use ieee.std_logic_misc.all;

entity hd44780_8b is

generic(

  Tas                        : integer :=   50; -- ns

  Tpwe                       : integer :=  450; -- ns

  Tcyce                      : integer := 1000; -- ns

  Clock_Frequency            : real    := 100000000.0; -- Hz

  Reset_Level                : std_logic := '1'

);

port(

  Clock                      : in  std_logic;

  Reset                      : in  std_logic;

  --

  Wr_Data                    : in  std_logic_vector(7 downto 0);

  Wr_Reg                     : in  std_logic;

  Wr_En                      : in  std_logic;

  --

  IO_Done                    : out std_logic;

  --

  LCD_RS                     : out std_logic;

  LCD_E                      : out std_logic;

  LCD_DQ                     : out std_logic_vector(7 downto 0)

);

end entity;

architecture behave of hd44780_8b is

  -- The ceil_log2 function returns the minimum register width required to

  --  hold the supplied integer.

  function ceil_log2 (x : in natural) return natural is

    variable retval          : natural;

  begin

    retval                   := 1;

    while ((2**retval) - 1) < x loop

      retval                 := retval + 1;

    end loop;

    return retval;

  end function;

  constant CONV_NANOSECS     : real := 0.000000001;

  constant Tas_r             : real := CONV_NANOSECS * real(Tas);

  constant Tpwe_r            : real := CONV_NANOSECS * real(Tpwe + Tas);

  constant Tcyc_r            : real := CONV_NANOSECS * real(Tcyce + Tas);

  constant TCYC_i            : integer := integer(Clock_Frequency * Tcyc_r);

  constant TCYC_BITS         : integer := ceil_log2(TCYC_i);

  constant TCYC_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=

                               conv_std_logic_vector(TCYC_i-1, TCYC_BITS);

  signal tcyc_timer          : std_logic_vector(TCYC_BITS - 1 downto 0) :=

                               (others => '0');

  constant TAS_i             : integer := integer(Clock_Frequency * Tas_r);

  constant TAS_DELAY         : std_logic_vector(TCYC_BITS - 1 downto 0) :=

                               conv_std_logic_vector(TAS_i-1,TCYC_BITS);

  constant TPWE_i            : integer := integer(Clock_Frequency * Tpwe_r);

  constant TPWE_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=

                               conv_std_logic_vector(TPWE_i-1, TCYC_BITS);

  type IO_STATES   is (IDLE, IO_TAS, IO_TPWE, IO_TCYC );

  signal io_state            : IO_STATES;

  signal Wr_Buffer           : std_logic_vector(8 downto 0);

  alias Wr_Buffer_A          is Wr_Buffer(8);

  alias Wr_Buffer_D          is Wr_Buffer(7 downto 0);

begin

  LCD_IO_proc: process( Clock, Reset )

  begin

    if( Reset = Reset_Level )then

      io_state               <= IDLE;

      tcyc_timer             <= (others => '0');

      Wr_Buffer              <= (others => '0');

      IO_Done                <= '0';

      LCD_RS                 <= '0';

      LCD_E                  <= '0';

      LCD_DQ                 <= (others => '0');

    elsif( rising_edge(Clock) )then

      IO_Done                <= '0';

      LCD_RS                 <= '0';

      LCD_E                  <= '0';

      LCD_DQ                 <= x"00";

      tcyc_timer             <= tcyc_timer + 1;

      case( io_state )is

        when IDLE =>

          tcyc_timer         <= (others => '0');

          if( Wr_En = '1' )then

            Wr_Buffer        <= Wr_Reg & Wr_Data;

            io_state         <= IO_TAS;

          end if;

        when IO_TAS =>

          LCD_RS             <= Wr_Buffer_A;

          if( tcyc_timer >= TAS_DELAY )then

            io_state         <= IO_TPWE;

          end if;

        when IO_TPWE =>

          LCD_RS             <= Wr_Buffer_A;

          LCD_E              <= '1';

          LCD_DQ             <= Wr_Buffer_D;

          if( tcyc_timer >= TPWE_DELAY )then

            io_state         <= IO_TCYC;

          end if;

        when IO_TCYC =>

          LCD_RS             <= Wr_Buffer_A;

          LCD_DQ             <= Wr_Buffer_D;

          if( tcyc_timer >= TCYC_DELAY )then

            IO_Done          <= '1';

            io_state         <= IDLE;

          end if;

        when others =>

          null;

      end case;

    end if;

  end process;

end architecture;