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-- Copyright (c)2023 Jeremy Seth Henry

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--

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--       where applicable (as part of a user interface, debugging port, etc.)

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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

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--

-- VHDL units : intdiv

-- Description: Performs an integer division operation using a restoring

--               algorithm that produces both a quotient and a remainder.

--              Note that the Dividend and Divisor have the same bit width.

--

-- Algorithm:

--  1: Initialize registers (Q = Dividend, M = Divisor, R = 0, N = number of bits in dividend)

--  2: Shift R & Q (RQ) left by 1

--  3: Calculate difference R = R - M

--  4: Check the sign of the result.

--     If the MSB of RQ (R) is '0' (R >= M), then set the LSB of RQ (Q) to a '1'

--     If the MSB of RQ (R) is '1' (M > R) then restore R and set the LSB of Q to '0'

--  5: Loop to step 2 while N < Div_Width (Dividend Width)

--  6: Assign Q to Quotient and R to Remainder

--

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      04/10/23 Initial Design

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity intdiv is

generic(

  Div_Width             : integer   := 16;

  Reset_Level           : std_logic := '0'

);

port(

  Clock                 : in  std_logic;

  Reset                 : in  std_logic;

  --

  Enable                : in  std_logic;

  Busy                  : out std_logic;

  --

  Dividend              : in  std_logic_vector(Div_Width - 1 downto 0);

  Divisor               : in  std_logic_vector(Div_Width - 1 downto 0);

  Quotient              : out std_logic_vector(Div_Width - 1 downto 0);

  Remainder             : out std_logic_vector(Div_Width - 1 downto 0)

);

end entity;

architecture behave of intdiv is

  -- RQ combines R & Q into a single register

  signal RQ             : std_logic_vector(Div_Width*2-1 downto 0) :=

                           (others => '0');

  alias  R              is RQ(Div_Width*2-1 downto Div_Width);

  alias  Q              is RQ(Div_Width-1 downto 0);

  -- Dividend is assumed to be the same width as the Divisor

  signal M              : std_logic_vector(Div_Width - 1 downto 0) :=

                           (others => '0');

  -- Difference result should be 1 bit larger than the Dividend to allow for

  --  a sign bit

  signal D              : std_logic_vector(Div_Width downto 0) :=

                           (others => '0');

  alias  S              is D(Div_Width);

  constant LZ           : std_logic_vector(Div_Width - 1 downto 0) :=

                            (others => '0');

  signal N              : integer range 0 to Div_Width := 0;

begin

  Quotient              <= Q;

  Remainder             <= R;

  -- This statement combines the left shift logic with the subtraction.

  -- Leading '0's are used to force both arguments to be positive.

  D                     <= ('0' & RQ(Div_Width*2-2 downto Div_Width-1)) -

                           ('0' & M);

  Divide_proc: process( Clock, Reset )

  begin

    if( Reset = Reset_Level )then

      RQ                <= (others => '0');

      M                 <= (others => '0');

      N                 <= 0;

      Busy              <= '0';

    elsif( rising_edge(Clock) )then

      Busy              <= '0';

      if( Enable = '1' )then

        Busy            <= '1';

        N               <= Div_Width;

        RQ              <= LZ & Dividend;

        M               <= Divisor;

      end if;

      if( N > 0 )then

        Busy            <= '1';

        N               <= N - 1;

        -- Leave R set to R-M and set Q[0] to '1'

        RQ              <= D(Div_Width-1 downto 0) &  -- New R

                           RQ(Div_Width-2 downto 0) & -- Q<<1

                           '1';                       -- Q(0) = '1'

        if( S = '1' )then

          -- Restore R and set Q[0] to '0'

          RQ            <= RQ(Div_Width*2-2 downto 0) & '0';

        end if;

      end if;

    end if;

  end process;

end architecture;