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[/] [open8_urisc/] [trunk/] [VHDL/] [intdiv.vhd] - Blame information for rev 333

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Line No. Rev Author Line
1 318 jshamlet
-- Copyright (c)2023 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL units : intdiv
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-- Description: Performs an integer division operation using a restoring
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--               algorithm that produces both a quotient and a remainder.
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--              Note that the Dividend and Divisor have the same bit width.
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--
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-- Algorithm:
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--  1: Initialize registers (Q = Dividend, M = Divisor, R = 0, N = number of bits in dividend)
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--  2: Shift R & Q (RQ) left by 1
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--  3: Calculate difference R = R - M
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--  4: Check the sign of the result.
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--     If the MSB of RQ (R) is '0' (R >= M), then set the LSB of RQ (Q) to a '1'
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--     If the MSB of RQ (R) is '1' (M > R) then restore R and set the LSB of Q to '0'
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--  5: Loop to step 2 while N < Div_Width (Dividend Width)
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--  6: Assign Q to Quotient and R to Remainder
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/10/23 Initial Design
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity intdiv is
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generic(
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  Div_Width             : integer   := 16;
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  Reset_Level           : std_logic := '0'
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);
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port(
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  Clock                 : in  std_logic;
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  Reset                 : in  std_logic;
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  --
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  Enable                : in  std_logic;
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  Busy                  : out std_logic;
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  --
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  Dividend              : in  std_logic_vector(Div_Width - 1 downto 0);
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  Divisor               : in  std_logic_vector(Div_Width - 1 downto 0);
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  Quotient              : out std_logic_vector(Div_Width - 1 downto 0);
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  Remainder             : out std_logic_vector(Div_Width - 1 downto 0)
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);
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end entity;
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architecture behave of intdiv is
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  -- RQ combines R & Q into a single register
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  signal RQ             : std_logic_vector(Div_Width*2-1 downto 0) :=
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                           (others => '0');
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  alias  R              is RQ(Div_Width*2-1 downto Div_Width);
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  alias  Q              is RQ(Div_Width-1 downto 0);
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  -- Dividend is assumed to be the same width as the Divisor
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  signal M              : std_logic_vector(Div_Width - 1 downto 0) :=
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                           (others => '0');
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  -- Difference result should be 1 bit larger than the Dividend to allow for
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  --  a sign bit
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  signal D              : std_logic_vector(Div_Width downto 0) :=
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                           (others => '0');
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  alias  S              is D(Div_Width);
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  constant LZ           : std_logic_vector(Div_Width - 1 downto 0) :=
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                            (others => '0');
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  signal N              : integer range 0 to Div_Width := 0;
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begin
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  Quotient              <= Q;
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  Remainder             <= R;
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  -- This statement combines the left shift logic with the subtraction.
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  -- Leading '0's are used to force both arguments to be positive.
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  D                     <= ('0' & RQ(Div_Width*2-2 downto Div_Width-1)) -
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                           ('0' & M);
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  Divide_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      RQ                <= (others => '0');
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      M                 <= (others => '0');
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      N                 <= 0;
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      Busy              <= '0';
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    elsif( rising_edge(Clock) )then
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      Busy              <= '0';
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      if( Enable = '1' )then
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        Busy            <= '1';
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        N               <= Div_Width;
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        RQ              <= LZ & Dividend;
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        M               <= Divisor;
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      end if;
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      if( N > 0 )then
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        Busy            <= '1';
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        N               <= N - 1;
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        -- Leave R set to R-M and set Q[0] to '1'
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        RQ              <= D(Div_Width-1 downto 0) &  -- New R
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                           RQ(Div_Width-2 downto 0) & -- Q<<1
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                           '1';                       -- Q(0) = '1'
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        if( S = '1' )then
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          -- Restore R and set Q[0] to '0'
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          RQ            <= RQ(Div_Width*2-2 downto 0) & '0';
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        end if;
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      end if;
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    end if;
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  end process;
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end architecture;

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