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jshamlet |
-- Copyright (c)2023 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL units : mavg_8ch_16b_64d
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-- Description: 8-channel moving average calculation for 16-bit unsigned data
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-- Accumulator depth is 64 elements, using 1 block RAM.
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 05/18/23 Initial Upload
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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entity mavg_8ch_16b_64d is
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generic(
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Reset_Level : std_logic := '1'
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);
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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RAW_Channel : in std_logic_vector(2 downto 0);
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RAW_Data : in std_logic_vector(15 downto 0);
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RAW_Valid : in std_logic;
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--
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Busy_Out : out std_logic;
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--
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AVG_Channel : out std_logic_vector(2 downto 0);
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AVG_Out : out std_logic_vector(15 downto 0);
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AVG_Valid : out std_logic;
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--
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Busy_In : in std_logic
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);
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end entity;
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architecture behave of mavg_8ch_16b_64d is
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type AVG_CTL_STATES is (INIT, CLR_BUFF, IDLE, BUSY_WAIT, RD_LAST,
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ADV_PTR, CALC_NEXT, WR_NEW);
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signal AVG_Ctl : AVG_CTL_STATES := INIT;
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signal CH_Select : std_logic_vector(2 downto 0);
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signal Data_New : std_logic_vector(15 downto 0) := (others => '0');
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signal RAM_Wr_Addr : std_logic_vector(8 downto 0) := (others => '0');
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alias RAM_Wr_Chan is RAM_Wr_Addr(8 downto 6);
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alias RAM_Wr_Ptr is RAM_Wr_Addr(5 downto 0);
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signal RAM_Wr_Data : std_logic_vector(15 downto 0) := (others => '0');
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signal RAM_Wr_En : std_logic := '0';
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signal RAM_Rd_Addr : std_logic_vector(8 downto 0) := (others => '0');
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alias RAM_Rd_Chan is RAM_Rd_Addr(8 downto 6);
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alias RAM_Rd_Ptr is RAM_Rd_Addr(5 downto 0);
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signal RAM_Rd_Data : std_logic_vector(15 downto 0) := (others => '0');
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alias Data_Old is RAM_Rd_Data;
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type PTR_ARRAY is array (0 to 7) of std_logic_vector(5 downto 0);
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signal SP0_Pointers : PTR_ARRAY;
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signal SPN_Pointers : PTR_ARRAY;
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-- Accumulator width is bus_size (16) + log depth (6)
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type ACCUM_ARRAY is array (0 to 7) of unsigned(21 downto 0);
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signal Accumulators : ACCUM_ARRAY;
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begin
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MAVG_Control_proc: process( Clock, Reset )
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variable i : integer := 0;
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begin
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if( Reset = Reset_Level )then
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AVG_Ctl <= INIT;
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CH_Select <= (others => '0');
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Data_New <= (others => '0');
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Busy_Out <= '0';
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for i in 0 to 7 loop
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SP0_Pointers(i) <= (others => '1');
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SPN_Pointers(i) <= (others => '0');
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Accumulators(i) <= (others => '0');
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end loop;
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RAM_Wr_Addr <= (others => '0');
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RAM_Wr_Data <= (others => '0');
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RAM_Wr_En <= '0';
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RAM_Rd_Addr <= (others => '0');
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AVG_Channel <= (others => '0');
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AVG_Out <= (others => '0');
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AVG_Valid <= '0';
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elsif( rising_edge(Clock) )then
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RAM_Wr_En <= '0';
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Busy_Out <= '1';
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AVG_Valid <= '0';
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i := conv_integer(unsigned(CH_Select));
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case( AVG_Ctl )is
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when INIT =>
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RAM_Wr_Addr <= (others => '0');
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RAM_Wr_Data <= (others => '0');
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AVG_Ctl <= CLR_BUFF;
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when CLR_BUFF =>
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RAM_Wr_Addr <= RAM_Wr_Addr + 1;
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RAM_Wr_En <= '1';
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if( and_reduce(RAM_Wr_Addr) = '1' )then
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AVG_Ctl <= IDLE;
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end if;
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when IDLE =>
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Busy_Out <= '0';
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if( RAW_Valid = '1' )then
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Data_New <= RAW_Data;
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CH_Select <= RAW_Channel;
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AVG_Ctl <= BUSY_WAIT;
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end if;
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when BUSY_WAIT =>
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if( Busy_In = '0' )then
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AVG_Ctl <= RD_LAST;
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end if;
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when RD_LAST =>
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RAM_Rd_Chan <= CH_Select;
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RAM_Rd_Ptr <= SPN_Pointers(i);
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AVG_Ctl <= ADV_PTR;
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when ADV_PTR =>
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SP0_Pointers(i) <= SP0_Pointers(i) + 1;
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AVG_Ctl <= CALC_NEXT;
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when CALC_NEXT =>
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Accumulators(i) <= Accumulators(i) +
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unsigned( Data_New ) -
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unsigned( Data_Old );
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AVG_Ctl <= WR_NEW;
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when WR_NEW =>
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RAM_Wr_Chan <= CH_Select;
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RAM_Wr_Ptr <= SP0_Pointers(i);
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RAM_Wr_Data <= Data_New;
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RAM_Wr_En <= '1';
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SPN_Pointers(i) <= SP0_Pointers(i) + 1;
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AVG_Channel <= CH_Select;
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AVG_Out <= std_logic_vector(Accumulators(i)(21 downto 6));
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AVG_Valid <= '1';
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AVG_Ctl <= IDLE;
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when others =>
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null;
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end case;
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end if;
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end process;
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U_BUFF : entity work.mavg_buffer_16b
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port map(
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clock => Clock,
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data => RAM_Wr_Data,
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rdaddress => RAM_Rd_Addr,
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wraddress => RAM_Wr_Addr,
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wren => RAM_Wr_En,
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q => RAM_Rd_Data
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);
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end architecture;
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