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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_alu16.vhd] - Blame information for rev 167

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1 167 jshamlet
-- Copyright (c)2013 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
22
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_alu16
25
-- Description:  Provides a mix of common 16-bit math functions to accelerate
26
--            :   math operations on the Open8 microprocessor core.
27
--
28
-- Notes      :  All output registers are updated by writing an instruction to
29
--            :   offset 0x1F.
30
--            :  The math unit is busy when the MSB of the status
31
--            :   register is high, and done/ready when it reads low.
32
--            :  Almost Equal checks to see if Addend 1 is no more, or less
33
--            :   addend 2 within the specified tolerance. For example,
34
--            :   addend_1 = 2 is almost equal to addend_2 = -1 with a
35
--            :   tolerance of 3, but not a tolerance of 1. Actual function is
36
--            :   AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
37
--            :   This is an inherently signed function.
38
--            : Signed Overflow/Underflow is logically equivalent to
39
--            :  S_Sum/Dif(16) xor S_Sum/Dif(15), since the apparent result
40
--            :  changes sign while the internal sign bit does not. For example
41
--            :  |8000| will result in (-)8000 due to the way the internal
42
--            :  logic handles sign extension. Thus, the O bit should be
43
--            :  checked when performing signed math
44
--            : Decimal Adjust converts the contents of a register into its BCD
45
--            :  equivalent. This can be used to get the base 10 representation
46
--            :  of a value for conversion to ASCII. There are two variants,
47
--            :  Byte and Word. Note that conversion times are fairly long,
48
--            :  since we are repeatedly issuing division commands, but it is
49
--            :  still faster than software emulation.
50
--            : The Byte conversion only operates on the lower 8 bits, and sets
51
--            :  the Z and N flags. The N flag is only set when SDAB is used
52
--            :  and the signed value of the register is negative. The O bit is
53
--            :  set if the upper byte of the register is non-zero, but does
54
--            :  not actually result in an calculation error.
55
--            :  Examples:
56
--            :  UDAB 0x00FE -> 0x0254, Flags -> 0x0
57
--            :  SDAB 0x00FE -> 0x0002, Flags -> 0x4
58
--            : The Word conversion uses the entire 16-bit word, and uses the
59
--            :  Flags register to hold the Tens of Thousands place. Note that
60
--            :  the N flag is still used for signed conversions, while it may
61
--            :  be used as a data bit for unsigned conversions.
62
--            :  Examples:
63
--            :  UDAW 0xD431 -> 0x4321, Flags -> 0x5 ('0', MSB, MSB-1, MSB-2)
64
--            :  SDAW 0xD431 -> 0x1216, Flags -> 0x5 ('0', N  , MSB  , MSB-1)
65
 
66
-- Register Map:
67
-- Offset  Bitfield Description                        Read/Write
68
--   0x00   AAAAAAAA Register 0 ( 7:0)                  (RW)
69
--   0x01   AAAAAAAA Register 0 (15:8)                  (RW)
70
--   0x02   AAAAAAAA Register 1 ( 7:0)                  (RW)
71
--   0x03   AAAAAAAA Register 1 (15:8)                  (RW)
72
--   0x04   AAAAAAAA Register 2 ( 7:0)                  (RW)
73
--   0x05   AAAAAAAA Register 2 (15:8)                  (RW)
74
--   0x06   AAAAAAAA Register 3 ( 7:0)                  (RW)
75
--   0x07   AAAAAAAA Register 3 (15:8)                  (RW)
76
--   0x08   AAAAAAAA Register 4 ( 7:0)                  (RW)
77
--   0x09   AAAAAAAA Register 4 (15:8)                  (RW)
78
--   0x0A   AAAAAAAA Register 5 ( 7:0)                  (RW)
79
--   0x0B   AAAAAAAA Register 5 (15:8)                  (RW)
80
--   0x0C   AAAAAAAA Register 6 ( 7:0)                  (RW)
81
--   0x0D   AAAAAAAA Register 6 (15:8)                  (RW)
82
--   0x0E   AAAAAAAA Register 7 ( 7:0)                  (RW)
83
--   0x0F   AAAAAAAA Register 7 (15:8)                  (RW)
84
--   0x10   -------- Reserved                           (--)
85
--   0x11   -------- Reserved                           (--)
86
--   0x12   -------- Reserved                           (--)
87
--   0x13   -------- Reserved                           (--)
88
--   0x14   -------- Reserved                           (--)
89
--   0x15   -------- Reserved                           (--)
90
--   0x16   -------- Reserved                           (--)
91
--   0x17   -------- Reserved                           (--)
92
--   0x18   -------- Reserved                           (--)
93
--   0x19   -------- Reserved                           (--)
94
--   0x1A   -------- Reserved                           (--)
95
--   0x1B   -------- Reserved                           (--)
96
--   0x1C   AAAAAAAA Tolerance  ( 7:0)                  (RW)
97
--   0x1D   AAAAAAAA Tolerance  (15:8)                  (RW)
98
--   0x1E   E---DCBA Status & Flags                     (RW)
99
--                   A = Zero Flag
100
--                   B = Carry Flag 
101
--                   C = Negative Flag
102
--                   D = Overflow / Error Flag
103
--                   E = Busy Flag (1 = busy, 0 = idle)
104
--   0x1F   BBBBBAAA Instruction Register               (RW)
105
--                   A = Operand (register select)
106
--                   B = Opcode  (instruction select)
107
--
108
-- Instruction Map:
109
-- OP_T0X  "0000 0xxx" : Transfer R0 to Rx    R0      -> Rx (Sets Z,N)
110
-- OP_TX0  "0000 1xxx" : Transfer Rx to R0    Rx      -> R0 (Sets Z,N)
111
-- OP_CLR  "0001 0xxx" : Set Rx to 0          0x00    -> Rx (Sets Z,N)
112
--
113
-- OP_IDIV "0001 1xxx" : Integer Division     R0/Rx   -> Q:R0, R:Rx
114
--
115
-- OP_UMUL "0010 0xxx" : Unsigned Multiply    R0*Rx   -> R1:R0 (Sets Z)
116
-- OP_UADD "0010 1xxx" : Unsigned Addition    R0+Rx   -> R0 (Sets N,Z,C)
117
-- OP_UADC "0011 0xxx" : Unsigned Add w/Carry R0+Rx+C -> R0 (Sets N,Z,C)
118
-- OP_USUB "0011 1xxx" : Unsigned Subtraction R0-Rx   -> R0 (Sets N,Z,C)
119
-- OP_USBC "0100 0xxx" : Unsigned Sub w/Carry R0-Rx-C -> R0 (Sets N,Z,C)
120
-- OP_UCMP "0100 1xxx" : Unsigned Compare     R0-Rx - Sets N,Z,C only
121
--
122
-- OP_SMUL "0101 0xxx" : Signed Multiply      R0*Rx   -> R1:R0 (Sets N,Z)
123
-- OP_SADD "0101 1xxx" : Signed Addition      R0+Rx   -> R0 (Sets N,Z,O)
124
-- OP_SSUB "0110 0xxx" : Signed Subtraction   R0-Rx   -> R0 (Sets N,Z,O)
125
-- OP_SCMP "0110 1xxx" : Signed Compare       R0-Rx - Sets N,Z,O only
126
-- OP_SMAG "0111 0xxx" : Signed Magnitude     |Rx|    -> R0 (Sets Z,O)
127
-- OP_SNEG "0111 1xxx" : Signed Negation      -Rx     -> R0 (Sets N,Z,O)
128
--
129
-- OP_ACMP "1000 0xxx" : Signed Almost Equal (see description)
130
-- OP_SCRY "1000 1---" : Set the carry bit   (ignores operand)
131
--
132
-- OP_UDAB "1001 0xxx" : Decimal Adjust Byte (see description)
133
-- OP_SDAB "1001 1xxx" : Decimal Adjust Byte (see description)
134
-- OP_UDAW "1010 0xxx" : Decimal Adjust Word (see description)
135
-- OP_SDAW "1010 1xxx" : Decimal Adjust Word (see description)
136
 
137
-- OP_RSVD "1011 0---" : Reserved
138
 
139
-- OP_BSWP "1011 1xxx" : Byte Swap (Swaps upper and lower bytes)
140
 
141
-- OP_BOR  "1100 0xxx" : Bitwise Logical OR   Rx or  R0 -> R0
142
-- OP_BAND "1100 1xxx" : Bitwise Logical AND  Rx and R0 -> R0
143
-- OP_BXOR "1101 0xxx" : Bitwise Logical XOR  Rx xor R0 -> R0
144
--
145
-- OP_BINV "1101 1xxx" : Bitwise logical NOT #Rx      -> Rx
146
-- OP_BSFL "1110 0xxx" : Logical Shift Left   Rx<<1,0 -> Rx
147
-- OP_BROL "1110 1xxx" : Logical Rotate Left  Rx<<1,C -> Rx,C
148
-- OP_BSFR "1111 0xxx" : Logical Shift Right  0,Rx>>1 -> Rx
149
-- OP_BROR "1111 1xxx" : Logical Rotate Right C,Rx>>1 -> Rx,C
150
 
151
library ieee;
152
use ieee.std_logic_1164.all;
153
use ieee.std_logic_arith.all;
154
use ieee.std_logic_unsigned.all;
155
use ieee.std_logic_misc.all;
156
 
157
library work;
158
  use work.open8_pkg.all;
159
 
160
entity o8_alu16 is
161
generic(
162
  Reset_Level           : std_logic;
163
  Address               : ADDRESS_TYPE
164
);
165
port(
166
  Clock                 : in  std_logic;
167
  Reset                 : in  std_logic;
168
  --
169
  Bus_Address           : in  ADDRESS_TYPE;
170
  Wr_Enable             : in  std_logic;
171
  Wr_Data               : in  DATA_TYPE;
172
  Rd_Enable             : in  std_logic;
173
  Rd_Data               : out DATA_TYPE;
174
  Interrupt             : out std_logic
175
);
176
end entity;
177
 
178
architecture behave of o8_alu16 is
179
 
180
  -------------------------------------------------------------------
181
  -- Opcode Definitions (should match the table above)
182
  -- Register Manipulation
183
  constant OP_T0X       : std_logic_vector(4 downto 0) := "00000";
184
  constant OP_TX0       : std_logic_vector(4 downto 0) := "00001";
185
  constant OP_CLR       : std_logic_vector(4 downto 0) := "00010";
186
 
187
  -- Integer Division
188
  constant OP_IDIV      : std_logic_vector(4 downto 0) := "00011";
189
 
190
  -- Unsigned Math Operations
191
  constant OP_UMUL      : std_logic_vector(4 downto 0) := "00100";
192
  constant OP_UADD      : std_logic_vector(4 downto 0) := "00101";
193
  constant OP_UADC      : std_logic_vector(4 downto 0) := "00110";
194
  constant OP_USUB      : std_logic_vector(4 downto 0) := "00111";
195
  constant OP_USBC      : std_logic_vector(4 downto 0) := "01000";
196
  constant OP_UCMP      : std_logic_vector(4 downto 0) := "01001";
197
 
198
  -- Signed Math Operations
199
  constant OP_SMUL      : std_logic_vector(4 downto 0) := "01010";
200
  constant OP_SADD      : std_logic_vector(4 downto 0) := "01011";
201
  constant OP_SSUB      : std_logic_vector(4 downto 0) := "01100";
202
  constant OP_SCMP      : std_logic_vector(4 downto 0) := "01101";
203
  constant OP_SMAG      : std_logic_vector(4 downto 0) := "01110";
204
  constant OP_SNEG      : std_logic_vector(4 downto 0) := "01111";
205
 
206
  -- Signed Almost Equal
207
  constant OP_ACMP      : std_logic_vector(4 downto 0) := "10000";
208
 
209
  -- Carry Flag set/clear
210
  constant OP_SCRY      : std_logic_vector(4 downto 0) := "10001";
211
 
212
  -- (Un)Signed Decimal Adjust Byte
213
  constant OP_UDAB      : std_logic_vector(4 downto 0) := "10010";
214
  constant OP_SDAB      : std_logic_vector(4 downto 0) := "10011";
215
 
216
  -- (Un)Signed Decimal Adjust Word
217
  constant OP_UDAW      : std_logic_vector(4 downto 0) := "10100";
218
  constant OP_SDAW      : std_logic_vector(4 downto 0) := "10101";
219
 
220
  -- Reserved for future use
221
  constant OP_RSVD      : std_logic_vector(4 downto 0) := "10110";
222
 
223
  -- Byte Swap ( U <> L )
224
  constant OP_BSWP      : std_logic_vector(4 downto 0) := "10111";
225
 
226
  -- Bitwise Boolean Operations (two operand)
227
  constant OP_BOR       : std_logic_vector(4 downto 0) := "11000";
228
  constant OP_BAND      : std_logic_vector(4 downto 0) := "11001";
229
  constant OP_BXOR      : std_logic_vector(4 downto 0) := "11010";
230
 
231
  -- In-place Bitwise Boolean Operations (single operand)
232
  constant OP_BINV      : std_logic_vector(4 downto 0) := "11011";
233
  constant OP_BSFL      : std_logic_vector(4 downto 0) := "11100";
234
  constant OP_BROL      : std_logic_vector(4 downto 0) := "11101";
235
  constant OP_BSFR      : std_logic_vector(4 downto 0) := "11110";
236
  constant OP_BROR      : std_logic_vector(4 downto 0) := "11111";
237
  -------------------------------------------------------------------
238
 
239
  constant User_Addr    : std_logic_vector(15 downto 5):= Address(15 downto 5);
240
  alias Comp_Addr       is Bus_Address(15 downto 5);
241
  signal Reg_Addr       : std_logic_vector(4 downto 0);
242
 
243
  signal Addr_Match     : std_logic;
244
  signal Wr_En          : std_logic;
245
  signal Wr_Data_q      : DATA_TYPE;
246
  signal Rd_En          : std_logic;
247
 
248
  type REG_ARRAY is array( 0 to 7 ) of std_logic_vector(15 downto 0);
249
  signal regfile        : REG_ARRAY;
250
 
251
  signal Start          : std_logic;
252
  signal Opcode         : std_logic_vector(4 downto 0);
253
  signal Operand_Sel    : std_logic_vector(2 downto 0);
254
 
255
  signal Tolerance      : std_logic_vector(15 downto 0);
256
  signal High_Tol       : signed(16 downto 0);
257
  signal Low_Tol        : signed(16 downto 0);
258
  signal Almost_Equal   : std_logic;
259
 
260
  constant FLAG_Z       : integer := 0;
261
  constant FLAG_C       : integer := 1;
262
  constant FLAG_N       : integer := 2;
263
  constant FLAG_O       : integer := 3;
264
 
265
  signal Flags          : std_logic_vector(3 downto 0);
266
 
267
  type ALU_STATES is ( IDLE, LOAD, EXECUTE,   IDIV_INIT, IDIV_WAIT,
268
                       DAW_INIT,   DAB_INIT,  DAA_WAIT1, DAA_STEP2,
269
                       DAA_WAIT2,  DAA_STEP3, DAA_WAIT3, DAA_STEP4,
270
                       STORE );
271
  signal alu_ctrl       : ALU_STATES;
272
 
273
  signal Busy           : std_logic;
274
  signal Busy_q         : std_logic;
275
 
276
  signal Operand_1      : std_logic_vector(15 downto 0);
277
  signal Operand_2      : std_logic_vector(15 downto 0);
278
 
279
  alias  Dividend       is Operand_1;
280
  alias  Divisor        is Operand_2;
281
 
282
  alias  u_Operand_1    is Operand_1;
283
  alias  u_Operand_2    is Operand_2;
284
 
285
  alias  u_Addend_1     is Operand_1;
286
  alias  u_Addend_2     is Operand_2;
287
 
288
  signal s_Operand_1    : signed(16 downto 0);
289
  signal s_Operand_2    : signed(16 downto 0);
290
 
291
  alias  s_Addend_1     is S_Operand_1;
292
  alias  s_Addend_2     is S_Operand_2;
293
 
294
  signal u_accum        : std_logic_vector(16 downto 0);
295
  alias  u_data         is u_accum(15 downto 0);
296
  alias  u_sign         is u_accum(15);
297
  alias  u_carry        is u_accum(16);
298
 
299
  signal u_prod         : std_logic_vector(31 downto 0);
300
 
301
  signal s_accum        : signed(16 downto 0);
302
  alias  s_data         is s_accum(15 downto 0);
303
  alias  s_sign         is s_accum(15);
304
  alias  s_ovf          is s_accum(16);
305
 
306
  signal s_prod         : signed(33 downto 0);
307
 
308
  signal IDIV_Start     : std_logic;
309
  signal IDIV_Busy      : std_logic;
310
 
311
  constant N            : integer := 16; -- Width of Operands
312
 
313
  signal q              : std_logic_vector(N*2-1 downto 0);
314
  signal diff           : std_logic_vector(N downto 0);
315
  signal count          : integer range 0 to N + 1;
316
 
317
  signal Quotient_i     : std_logic_vector(15 downto 0);
318
  signal Quotient       : std_logic_vector(15 downto 0);
319
 
320
  signal Remainder_i    : std_logic_vector(15 downto 0);
321
  signal Remainder      : std_logic_vector(15 downto 0);
322
 
323
  signal DAA_intreg     : std_logic_vector(15 downto 0);
324
  signal DAA_mode       : std_logic;
325
  signal DAA_sign       : std_logic;
326
  signal DAA_p4         : std_logic_vector(3 downto 0);
327
  signal DAA_p3         : std_logic_vector(3 downto 0);
328
  signal DAA_p2         : std_logic_vector(3 downto 0);
329
  alias  DAA_p1         is Quotient(3 downto 0);
330
  alias  DAA_p0         is Remainder(3 downto 0);
331
  signal DAA_result     : std_logic_vector(19 downto 0);
332
 
333
begin
334
 
335
  Addr_Match            <= '1' when Comp_Addr = User_Addr else '0';
336
 
337
  -- Sign-extend the base operands to created operands for signed math
338
  S_Operand_1           <= signed(Operand_1(15) & Operand_1);
339
  S_Operand_2           <= signed(Operand_2(15) & Operand_2);
340
 
341
  -- Compute the tolerance bounds for the Almost Equal function
342
  High_Tol              <= S_Operand_2 + signed('0' & Tolerance);
343
  Low_Tol               <= S_Operand_2 - signed('0' & Tolerance);
344
 
345
  -- Combinational logic for the Decimal Adjust logic
346
  DAA_result            <= DAA_p4 & DAA_p3 & DAA_p2 & DAA_p1 & DAA_p0;
347
 
348
  -- Combinational logic for the division logic
349
  diff                  <= ('0' & Q(N*2-2 downto N-1)) - ('0' & Divisor);
350
  Quotient_i            <= q(N-1 downto 0);
351
  Remainder_i           <= q(N*2-1 downto N);
352
 
353
  ALU_proc: process( Clock, Reset )
354
    variable Reg_Sel    : integer;
355
    variable Oper_Sel   : integer;
356
  begin
357
    if( Reset = Reset_Level )then
358
      Wr_En             <= '0';
359
      Wr_Data_q         <= (others => '0');
360
      Rd_En             <= '0';
361
      Rd_Data           <= (others => '0');
362
      Reg_Addr          <= (others => '0');
363
      Opcode            <= (others => '0');
364
      Operand_Sel       <= (others => '0');
365
      Tolerance         <= (others => '0');
366
      Start             <= '0';
367
      Busy_q            <= '0';
368
      Interrupt         <= '0';
369
      for i in 0 to 7 loop
370
        regfile(i)      <= (others => '0');
371
      end loop;
372
      alu_ctrl          <= IDLE;
373
      Operand_1         <= (others => '0');
374
      Operand_2         <= (others => '0');
375
      u_accum           <= (others => '0');
376
      u_prod            <= (others => '0');
377
      s_accum           <= (others => '0');
378
      s_prod            <= (others => '0');
379
      Quotient          <= (others => '0');
380
      Remainder         <= (others => '0');
381
      Flags             <= (others => '0');
382
      Almost_Equal      <= '0';
383
      Busy              <= '0';
384
      DAA_mode          <= '0';
385
      DAA_sign          <= '0';
386
      DAA_intreg        <= (others => '0');
387
      DAA_p4            <= (others => '0');
388
      DAA_p3            <= (others => '0');
389
      DAA_p2            <= (others => '0');
390
      IDIV_Start        <= '0';
391
      q                 <= (others => '0');
392
      count             <= N;
393
      IDIV_Busy         <= '0';
394
    elsif( rising_edge(Clock) )then
395
      -- For convenience, convert these to integers and assign them to
396
      --  variables
397
      Reg_Sel           := conv_integer(Reg_Addr(3 downto 1));
398
      Oper_Sel          := conv_integer(Operand_Sel);
399
 
400
      Wr_En             <= Addr_Match and Wr_Enable;
401
      Wr_Data_q         <= Wr_Data;
402
      Reg_Addr          <= Bus_Address(4 downto 0);
403
 
404
      Start             <= '0';
405
      if( Wr_En = '1' )then
406
        case( Reg_Addr )is
407
          -- Even addresses go to the lower byte of the register
408
          when "00000" | "00010" | "00100" | "00110" |
409
               "01000" | "01010" | "01100" | "01110" =>
410
            regfile(Reg_Sel)(7 downto 0) <= Wr_Data_q;
411
 
412
          -- Odd addresses go to the upper byte of the register
413
          when "00001" | "00011" | "00101" | "00111" |
414
               "01001" | "01011" | "01101" | "01111" =>
415
            regfile(Reg_Sel)(15 downto 8)<= Wr_Data_q;
416
 
417
          when "11100" => -- 0x1C -> Tolerance.l
418
            Tolerance(7 downto 0) <= Wr_Data_q;
419
 
420
          when "11101" => -- 0x1D -> Tolerance.u
421
            Tolerance(15 downto 8) <= Wr_Data_q;
422
 
423
          when "11110" => -- 0x1E -> Status register
424
            null;
425
 
426
          when "11111" => -- 0x1F -> Control register
427
            Start       <= '1';
428
            Opcode      <= Wr_Data_q(7 downto 3);
429
            Operand_Sel <= Wr_Data_q(2 downto 0);
430
 
431
          when others => null;
432
        end case;
433
      end if;
434
 
435
      Rd_Data           <= (others => '0');
436
      Rd_En             <= Addr_Match and Rd_Enable;
437
 
438
      if( Rd_En = '1' )then
439
        case( Reg_Addr )is
440
          when "00000" | "00010" | "00100" | "00110" |
441
               "01000" | "01010" | "01100" | "01110" =>
442
            Rd_Data  <= regfile(Reg_Sel)(7 downto 0);
443
          when "00001" | "00011" | "00101" | "00111" |
444
               "01001" | "01011" | "01101" | "01111" =>
445
            Rd_Data  <= regfile(Reg_Sel)(15 downto 8);
446
          when "11100" => -- 0x1C -> Tolerance.l
447
            Rd_Data  <= Tolerance(7 downto 0);
448
          when "11101" => -- 0x1D -> Tolerance.u
449
            Rd_Data  <= Tolerance(15 downto 8);
450
          when "11110" => -- 0x1E -> Flags & Status register
451
            Rd_Data  <= Busy & "000" & Flags;
452
          when "11111" => -- 0x1F -> Control register
453
            Rd_Data  <= Opcode & Operand_Sel;
454
          when others => null;
455
        end case;
456
      end if;
457
 
458
      Busy              <= '1';
459
      IDIV_Start        <= '0';
460
      case( alu_ctrl )is
461
        when IDLE =>
462
          Busy          <= '0';
463
          if( Start = '1' )then
464
            alu_ctrl    <= LOAD;
465
          end if;
466
 
467
        -- Load the operands from the register file. We also check for specific
468
        --  opcodes to set the DAA mode (signed vs unsigned). This is the only
469
        --  place where we READ the register file outside of the bus interface
470
        when LOAD =>
471
          Operand_1     <= regfile(0);
472
          Operand_2     <= regfile(Oper_Sel);
473
          DAA_mode      <= '0';
474
          if( Opcode = OP_SDAW or Opcode = OP_SDAB )then
475
            DAA_mode    <= '1';
476
          end if;
477
          alu_ctrl      <= EXECUTE;
478
 
479
        -- Now that the operands are loaded, we can execute the actual math
480
        --  operations. We do it with separate operand registers to pipeline
481
        --  the logic.
482
        when EXECUTE =>
483
          alu_ctrl      <= STORE;
484
          case( Opcode)is
485
            when OP_T0X =>
486
              u_accum   <= '0' & Operand_1;
487
 
488
            when OP_TX0 =>
489
              u_accum   <= '0' & Operand_2;
490
 
491
            when OP_CLR | OP_SCRY =>
492
              u_accum   <= (others => '0');
493
 
494
            when OP_BSWP =>
495
              u_accum   <= '0' &
496
                           Operand_2(7 downto 0) &
497
                           Operand_2(15 downto 8);
498
 
499
            when OP_SMAG =>
500
              s_accum   <= S_Operand_2;
501
              if( S_Operand_2 < 0)then
502
                s_accum <= -S_Operand_2;
503
              end if;
504
 
505
            when OP_SNEG =>
506
              s_accum   <= -S_Operand_2;
507
 
508
            when OP_SMUL =>
509
              s_prod    <= S_Operand_1 * S_Operand_2;
510
 
511
            when OP_UMUL =>
512
              u_prod    <= U_Operand_1 * U_Operand_2;
513
 
514
            when OP_SADD =>
515
              s_accum   <= S_Addend_1  + S_Addend_2;
516
 
517
            when OP_UADD =>
518
              u_accum   <= ('0' & Operand_1) + ('0' & Operand_2);
519
 
520
            when OP_UADC =>
521
              u_accum   <= ('0' & Operand_1) + ('0' & Operand_2) + Flags(FLAG_C);
522
 
523
            when OP_SSUB | OP_SCMP =>
524
              s_accum   <= S_Addend_1  - S_Addend_2;
525
 
526
            when OP_USUB | OP_UCMP =>
527
              u_accum   <= ('0' & U_Addend_1)  - ('0' & U_Addend_2);
528
 
529
            when OP_USBC =>
530
              u_accum   <= ('0' & U_Addend_1)  - ('0' & U_Addend_2) - Flags(FLAG_C);
531
 
532
            when OP_ACMP =>
533
              -- Perform the function
534
              -- AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
535
              Almost_Equal    <= '0';
536
              if( (S_Addend_1 <= High_Tol) and
537
                  (S_Addend_1 >= Low_Tol) )then
538
                Almost_Equal  <= '1';
539
              end if;
540
 
541
            when OP_BINV =>
542
              u_accum    <= '0' & (not U_Operand_1);
543
 
544
            when OP_BSFL =>
545
              u_accum    <= U_Operand_1 & '0';
546
 
547
            when OP_BROL =>
548
              u_accum    <= U_Operand_1 & Flags(FLAG_C);
549
 
550
            when OP_BSFR =>
551
              u_accum    <= "00" & U_Operand_1(15 downto 1);
552
 
553
            when OP_BROR =>
554
              u_accum    <= U_Operand_1(0) & Flags(FLAG_C) &
555
                            U_Operand_1(15 downto 1);
556
 
557
            when OP_BOR  =>
558
              u_accum    <= '0' & (U_Operand_1 or U_Operand_2);
559
 
560
            when OP_BAND =>
561
              u_accum    <= '0' & (U_Operand_1 and U_Operand_2);
562
 
563
            when OP_BXOR =>
564
              u_accum    <= '0' & (U_Operand_1 xor U_Operand_2);
565
 
566
         -- Division unit has a longer latency, so we need to wait for its busy
567
         --  signal to return low before storing results. Trigger the engine,
568
         --  and then jump to the wait state for it to finish
569
            when OP_IDIV =>
570
              IDIV_Start<= '1';
571
              alu_ctrl  <= IDIV_INIT;
572
 
573
        -- Decimal Adjust Word initialization
574
        --  Stores the sign bit for later use setting the N flag
575
        --  Assigns Operand_1 to register as-is
576
        --  If the sign bit is set, do a 2's complement of the register
577
            when OP_UDAW | OP_SDAW =>
578
              IDIV_Start<= '1';
579
              DAA_sign  <= Operand_2(15);
580
              Operand_1 <= Operand_2;
581
              if( (Operand_2(15) and DAA_mode) = '1' )then
582
                Operand_1 <= (not Operand_2) + 1;
583
              end if;
584
              Operand_2 <= x"2710";
585
              alu_ctrl  <= DAW_INIT;
586
 
587
        -- Decimal Adjust Byte initialization
588
        --  Stores the sign bit for later use setting the N flag
589
        --  Assigns Operand_1 to the lower byte of the register
590
        --  If the sign bit is set, do a 2's complement of the register
591
            when OP_UDAB | OP_SDAB =>
592
              IDIV_Start<= '1';
593
              DAA_p4    <= (others => '0');
594
              DAA_p3    <= (others => '0');
595
              DAA_sign  <= Operand_2(7);
596
              Operand_1 <= x"00" & Operand_2(7 downto 0);
597
              if( (Operand_2(7) and DAA_mode) = '1' )then
598
                Operand_1 <= ((not Operand_2) + 1) and x"00FF";
599
              end if;
600
              Operand_2 <= x"0064";
601
              alu_ctrl  <= DAB_INIT;
602
 
603
            when others => null;
604
          end case;
605
 
606
        -- These three states look superfluous, but simplify the state machine
607
        --  logic enough to improve performance. Leave them.
608
        when IDIV_INIT =>
609
          if( IDIV_Busy = '1' )then
610
            alu_ctrl    <= IDIV_WAIT;
611
          end if;
612
 
613
        when DAW_INIT =>
614
          if( IDIV_Busy = '1' )then
615
            alu_ctrl    <= DAA_WAIT1;
616
          end if;
617
 
618
        when DAB_INIT =>
619
          if( IDIV_Busy = '1' )then
620
            alu_ctrl    <= DAA_WAIT3;
621
          end if;
622
 
623
        when DAA_WAIT1 =>
624
          if( IDIV_Busy = '0' )then
625
            DAA_p4      <= Quotient_i(3 downto 0);
626
            DAA_intreg  <= Remainder_i;
627
            alu_ctrl    <= DAA_STEP2;
628
          end if;
629
 
630
        when DAA_STEP2 =>
631
          Operand_1     <= DAA_intreg;
632
          Operand_2     <= x"03E8";
633
          IDIV_Start    <= '1';
634
          if( IDIV_Busy = '1' )then
635
            alu_ctrl    <= DAA_WAIT2;
636
          end if;
637
 
638
        when DAA_WAIT2 =>
639
          if( IDIV_Busy = '0' )then
640
            DAA_p3      <= Quotient_i(3 downto 0);
641
            DAA_intreg  <= Remainder_i;
642
            alu_ctrl    <= DAA_STEP3;
643
          end if;
644
 
645
        when DAA_STEP3 =>
646
          Operand_1     <= DAA_intreg;
647
          Operand_2     <= x"0064";
648
          IDIV_Start    <= '1';
649
          if( IDIV_Busy = '1' )then
650
            alu_ctrl    <= DAA_WAIT3;
651
          end if;
652
 
653
        when DAA_WAIT3 =>
654
          if( IDIV_Busy = '0' )then
655
            DAA_p2      <= Quotient_i(3 downto 0);
656
            DAA_intreg  <= Remainder_i;
657
            alu_ctrl    <= DAA_STEP4;
658
          end if;
659
 
660
        when DAA_STEP4 =>
661
          Operand_1     <= DAA_intreg;
662
          Operand_2     <= x"000A";
663
          IDIV_Start    <= '1';
664
          if( IDIV_Busy = '1' )then
665
            alu_ctrl    <= IDIV_WAIT;
666
          end if;
667
 
668
        when IDIV_WAIT =>
669
          if( IDIV_Busy = '0' )then
670
            Quotient    <= Quotient_i;
671
            Remainder   <= Remainder_i;
672
            alu_ctrl    <= STORE;
673
          end if;
674
 
675
        -- All ALU writes to the register file go through here. This is also
676
        --  where the flag register gets updated. This should be the only
677
        --  place where the register file gets WRITTEN outside of the bus
678
        --  interface.
679
        when STORE =>
680
          Flags          <= (others => '0');
681
          case( Opcode)is
682
            when OP_T0X | OP_CLR | OP_BSWP =>
683
              regfile(Oper_Sel) <= u_data;
684
              Flags(FLAG_Z) <= nor_reduce(u_data);
685
              Flags(FLAG_N) <= u_sign;
686
 
687
            when OP_TX0  =>
688
              regfile(0) <= u_data;
689
              Flags(FLAG_Z) <= nor_reduce(u_data);
690
              Flags(FLAG_N) <= u_sign;
691
 
692
            when OP_SCRY =>
693
              Flags(FLAG_C) <= '0';
694
              if( Oper_Sel > 0 )then
695
                Flags(FLAG_C)<= '1';
696
              end if;
697
 
698
            when OP_IDIV =>
699
              regfile(0) <= Quotient;
700
              regfile(Oper_Sel) <= Remainder;
701
              Flags(FLAG_Z) <= nor_reduce(Quotient);
702
 
703
            when OP_SMAG | OP_SNEG | OP_SADD | OP_SSUB =>
704
              regfile(0) <= std_logic_vector(s_data);
705
              Flags(FLAG_N) <= s_sign;
706
              Flags(FLAG_Z) <= nor_reduce(std_logic_vector(s_data));
707
              Flags(FLAG_O) <= s_ovf xor s_sign;
708
 
709
            when OP_SMUL =>
710
              regfile(0) <= std_logic_vector(s_prod(15 downto 0));
711
              regfile(1) <= std_logic_vector(s_prod(31 downto 16));
712
              Flags(FLAG_N) <= s_prod(33) or s_prod(32);
713
              Flags(FLAG_Z) <= nor_reduce(std_logic_vector(s_prod));
714
 
715
            when OP_UMUL =>
716
              regfile(0) <= u_prod(15 downto 0);
717
              regfile(1) <= u_prod(31 downto 16);
718
              Flags(FLAG_N) <= u_prod(31);
719
              Flags(FLAG_Z) <= nor_reduce(u_prod);
720
 
721
            when OP_UADD | OP_USUB =>
722
              regfile(0) <= u_data;
723
              Flags(FLAG_Z) <= nor_reduce(u_data);
724
              Flags(FLAG_N) <= u_sign;
725
              Flags(FLAG_C) <= u_carry;
726
 
727
            when OP_SCMP =>
728
              Flags(FLAG_N) <= s_ovf;
729
              Flags(FLAG_Z) <= nor_reduce(std_logic_vector(s_data));
730
              Flags(FLAG_O) <= s_accum(16) xor s_accum(15);
731
 
732
            when OP_UCMP =>
733
              Flags(FLAG_Z) <= nor_reduce(u_data);
734
              Flags(FLAG_C) <= u_carry;
735
 
736
            when OP_ACMP =>
737
              Flags(FLAG_Z) <= Almost_Equal;
738
 
739
            when OP_UDAB | OP_SDAB =>
740
              regfile(Oper_Sel) <= DAA_result(15 downto 0);
741
              Flags(FLAG_Z) <= nor_reduce(DAA_result);
742
              Flags(FLAG_N) <= DAA_sign;
743
 
744
            when OP_UDAW | OP_SDAW =>
745
              regfile(Oper_Sel) <= DAA_result(15 downto 0);
746
              Flags(3 downto 0) <= DAA_result(19 downto 16);
747
              if( DAA_mode = '1' )then
748
                Flags(FLAG_N) <= DAA_sign;
749
              end if;
750
 
751
            when OP_BOR  | OP_BAND | OP_BXOR =>
752
              regfile(0) <= u_data;
753
              Flags(FLAG_Z) <= nor_reduce(u_data);
754
              Flags(FLAG_N) <= u_sign;
755
 
756
            when OP_BINV =>
757
              regfile(Oper_Sel) <= u_data;
758
              Flags(FLAG_Z) <= nor_reduce(u_data);
759
              Flags(FLAG_N) <= u_sign;
760
 
761
            when OP_BSFL | OP_BROL | OP_BSFR | OP_BROR =>
762
              regfile(Oper_Sel) <= u_data;
763
              Flags(FLAG_Z) <= nor_reduce(u_data);
764
              Flags(FLAG_N) <= u_sign;
765
              Flags(FLAG_C) <= u_carry;
766
 
767
            when others => null;
768
          end case;
769
          alu_ctrl      <= IDLE;
770
 
771
        when others =>
772
          null;
773
 
774
      end case;
775
 
776
      IDIV_Busy         <= '0';
777
      if( IDIV_Start = '1' )then
778
        IDIV_Busy       <= '1';
779
        count           <= 0;
780
        q               <= conv_std_logic_vector(0,N) & Dividend;
781
      elsif( count < N )then
782
        IDIV_Busy       <= '1';
783
        count           <= count + 1;
784
        q               <= diff(N-1 downto 0) & q(N-2 downto 0) & '1';
785
        if( diff(N) = '1' )then
786
          q             <= q(N*2-2 downto 0) & '0';
787
        end if;
788
      end if;
789
 
790
      -- Fire on the falling edge of Busy
791
      Busy_q            <= Busy;
792
      Interrupt         <= not Busy and Busy_q;
793
 
794
    end if;
795
  end process;
796
 
797
end architecture;

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