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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_alu16.vhd] - Blame information for rev 217

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1 213 jshamlet
-- Copyright (c)2006, 2015, 2019, 2020 Jeremy Seth Henry
2 193 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 193 jshamlet
--
24
-- VHDL Units :  o8_alu16
25
-- Description:  Provides a mix of common 16-bit math functions to accelerate
26
--            :   math operations on the Open8 microprocessor core.
27
--
28
-- Notes      :  All output registers are updated by writing to offset 0x1F.
29
--
30
--            :  The math unit is busy when the MSB of the status
31
--            :   register is high, and done/ready when it reads low.
32
--            :  Almost Equal checks to see if Addend 1 is no more, or less,
33
--            :   addend 2 within the specified tolerance. For example,
34
--            :   addend_1 = 2 is almost equal to addend_2 = -1 with a
35
--            :   tolerance of 3, but not a tolerance of 1. Actual function is
36
--            :   AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
37
--            :   This is an inherently signed function.
38
--            : Signed Overflow/Underflow is logically equivalent to
39
--            :  S_Sum/Dif(16) xor S_Sum/Dif(15), since the apparent result
40
--            :  changes sign while the internal sign bit doesn't. For example
41
--            :  |8000| will result in (-)8000 due to the way the internal
42
--            :  logic handles sign extension. Thus, the O bit should be
43
--            :  checked when performing signed math
44
--            : Decimal Adjust converts the contents of a register into its BCD
45
--            :  equivalent. This can be used to get the base 10 representation
46
--            :  of a value for conversion to ASCII. There are two variants,
47
--            :  Byte and Word. Note that conversion times are fairly long,
48
--            :  since we are repeatedly issuing division commands, but it is
49
--            :  still faster than software emulation.
50
--            : The Byte conversion only operates on the lower 8 bits, and
51
--            :  sets the Z and N flags. The N flag is only set when SDAB is
52
--            :  used and the signed value of the register is negative. The O
53
--            :  bit is set if the upper byte of the register is non-zero, but
54
--            :  does not actually result in an calculation error.
55
--            :  Examples:
56
--            :  UDAB 0x00FE -> 0x0254, Flags -> 0x0
57
--            :  SDAB 0x00FE -> 0x0002, Flags -> 0x4
58
--            : The Word conversion uses the entire 16-bit word, and uses the
59
--            :  Flags register to hold the Tens of Thousands place. Note that
60
--            :  the N flag is still used for signed conversions, while it may
61
--            :  be used as a data bit for unsigned conversions.
62
--            :  Examples:
63
--            :  UDAW 0xD431 -> 0x4321, Flags -> 0x5 ('0', MSB, MSB-1, MSB-2)
64
--            :  SDAW 0xD431 -> 0x1216, Flags -> 0x5 ('0', N  , MSB  , MSB-1)
65
--
66
-- Register Map:
67
-- Offset  Bitfield Description                        Read/Write
68
--   0x00   AAAAAAAA Register 0 ( 7:0)                  (RW)
69
--   0x01   AAAAAAAA Register 0 (15:8)                  (RW)
70
--   0x02   AAAAAAAA Register 1 ( 7:0)                  (RW)
71
--   0x03   AAAAAAAA Register 1 (15:8)                  (RW)
72
--   0x04   AAAAAAAA Register 2 ( 7:0)                  (RW)
73
--   0x05   AAAAAAAA Register 2 (15:8)                  (RW)
74
--   0x06   AAAAAAAA Register 3 ( 7:0)                  (RW)
75
--   0x07   AAAAAAAA Register 3 (15:8)                  (RW)
76
--   0x08   AAAAAAAA Register 4 ( 7:0)                  (RW)
77
--   0x09   AAAAAAAA Register 4 (15:8)                  (RW)
78
--   0x0A   AAAAAAAA Register 5 ( 7:0)                  (RW)
79
--   0x0B   AAAAAAAA Register 5 (15:8)                  (RW)
80
--   0x0C   AAAAAAAA Register 6 ( 7:0)                  (RW)
81
--   0x0D   AAAAAAAA Register 6 (15:8)                  (RW)
82
--   0x0E   AAAAAAAA Register 7 ( 7:0)                  (RW)
83
--   0x0F   AAAAAAAA Register 7 (15:8)                  (RW)
84
--   0x10   -------- Reserved                           (--)
85
--   0x11   -------- Reserved                           (--)
86
--   0x12   -------- Reserved                           (--)
87
--   0x13   -------- Reserved                           (--)
88
--   0x14   -------- Reserved                           (--)
89
--   0x15   -------- Reserved                           (--)
90
--   0x16   -------- Reserved                           (--)
91
--   0x17   -------- Reserved                           (--)
92
--   0x18   -------- Reserved                           (--)
93
--   0x19   -------- Reserved                           (--)
94
--   0x1A   -------- Reserved                           (--)
95
--   0x1B   -------- Reserved                           (--)
96
--   0x1C   AAAAAAAA Tolerance  ( 7:0)                  (RW)
97
--   0x1D   AAAAAAAA Tolerance  (15:8)                  (RW)
98
--   0x1E   BBBBBAAA Instruction Register               (RW)
99
--                   A = Operand (register select)
100
--                   B = Opcode  (instruction select)
101
--   0x1F   E---DCBA Status & Flags                     (RW)
102
--                   A = Zero Flag
103
--                   B = Carry Flag
104
--                   C = Negative Flag
105
--                   D = Overflow / Error Flag
106
--                   E = Busy Flag (1 = busy, 0 = idle)
107
--
108
-- Instruction Map:
109
-- OP_T0X  "0000 0xxx" : Transfer R0 to Rx    R0      -> Rx (Sets Z,N)
110
-- OP_TX0  "0000 1xxx" : Transfer Rx to R0    Rx      -> R0 (Sets Z,N)
111
-- OP_CLR  "0001 0xxx" : Set Rx to 0          0x00    -> Rx (Sets Z,N)
112
--
113
-- OP_IDIV "0001 1xxx" : Integer Division     R0/Rx   -> Q:R0, R:Rx
114
--
115
-- OP_UMUL "0010 0xxx" : Unsigned Multiply    R0*Rx   -> R1:R0 (Sets Z)
116
-- OP_UADD "0010 1xxx" : Unsigned Addition    R0+Rx   -> R0 (Sets N,Z,C)
117
-- OP_UADC "0011 0xxx" : Unsigned Add w/Carry R0+Rx+C -> R0 (Sets N,Z,C)
118
-- OP_USUB "0011 1xxx" : Unsigned Subtraction R0-Rx   -> R0 (Sets N,Z,C)
119
-- OP_USBC "0100 0xxx" : Unsigned Sub w/Carry R0-Rx-C -> R0 (Sets N,Z,C)
120
-- OP_UCMP "0100 1xxx" : Unsigned Compare     R0-Rx - Sets N,Z,C only
121
--
122
-- OP_SMUL "0101 0xxx" : Signed Multiply      R0*Rx   -> R1:R0 (Sets N,Z)
123
-- OP_SADD "0101 1xxx" : Signed Addition      R0+Rx   -> R0 (Sets N,Z,O)
124
-- OP_SSUB "0110 0xxx" : Signed Subtraction   R0-Rx   -> R0 (Sets N,Z,O)
125
-- OP_SCMP "0110 1xxx" : Signed Compare       R0-Rx - Sets N,Z,O only
126
-- OP_SMAG "0111 0xxx" : Signed Magnitude     |Rx|    -> R0 (Sets Z,O)
127
-- OP_SNEG "0111 1xxx" : Signed Negation      -Rx     -> R0 (Sets N,Z,O)
128
--
129
-- OP_ACMP "1000 0xxx" : Signed Almost Equal (see description)
130
-- OP_SCRY "1000 1---" : Set the carry bit   (ignores operand)
131
--
132
-- OP_UDAB "1001 0xxx" : Decimal Adjust Byte (see description)
133
-- OP_SDAB "1001 1xxx" : Decimal Adjust Byte (see description)
134
-- OP_UDAW "1010 0xxx" : Decimal Adjust Word (see description)
135
-- OP_SDAW "1010 1xxx" : Decimal Adjust Word (see description)
136
 
137
-- OP_RSVD "1011 0---" : Reserved
138
 
139
-- OP_BSWP "1011 1xxx" : Byte Swap (Swaps upper and lower bytes)
140
 
141
-- OP_BOR  "1100 0xxx" : Bitwise Logical OR   Rx or  R0 -> R0
142
-- OP_BAND "1100 1xxx" : Bitwise Logical AND  Rx and R0 -> R0
143
-- OP_BXOR "1101 0xxx" : Bitwise Logical XOR  Rx xor R0 -> R0
144
--
145
-- OP_BINV "1101 1xxx" : Bitwise logical NOT #Rx      -> Rx
146
-- OP_BSFL "1110 0xxx" : Logical Shift Left   Rx<<1,0 -> Rx
147
-- OP_BROL "1110 1xxx" : Logical Rotate Left  Rx<<1,C -> Rx,C
148
-- OP_BSFR "1111 0xxx" : Logical Shift Right  0,Rx>>1 -> Rx
149
-- OP_BROR "1111 1xxx" : Logical Rotate Right C,Rx>>1 -> Rx,C
150
--
151
-- Revision History
152
-- Author          Date     Change
153
------------------ -------- --------------------------------------------------
154
-- Seth Henry      07/19/06 Design Start
155
-- Seth Henry      03/13/15 Added "Almost Equal" instruction
156
-- Seth Henry      12/19/19 Renamed to o8_alu16 to fit "theme"
157 213 jshamlet
-- Seth Henry      04/10/20 Comment and code cleanup
158 193 jshamlet
 
159
library ieee;
160
use ieee.std_logic_1164.all;
161
use ieee.std_logic_arith.all;
162
use ieee.std_logic_unsigned.all;
163
use ieee.std_logic_misc.all;
164
 
165
library work;
166
  use work.open8_pkg.all;
167
 
168
entity o8_alu16 is
169
generic(
170 217 jshamlet
  Reset_Level                : std_logic;
171
  Address                    : ADDRESS_TYPE
172 193 jshamlet
);
173
port(
174 217 jshamlet
  Clock                      : in  std_logic;
175
  Reset                      : in  std_logic;
176 193 jshamlet
  --
177 217 jshamlet
  Bus_Address                : in  ADDRESS_TYPE;
178
  Wr_Enable                  : in  std_logic;
179
  Wr_Data                    : in  DATA_TYPE;
180
  Rd_Enable                  : in  std_logic;
181
  Rd_Data                    : out DATA_TYPE;
182
  Interrupt                  : out std_logic
183 193 jshamlet
);
184
end entity;
185
 
186
architecture behave of o8_alu16 is
187
 
188
  -------------------------------------------------------------------
189
  -- Opcode Definitions (should match the table above)
190
  -- Register Manipulation
191 217 jshamlet
  constant OP_T0X            : std_logic_vector(4 downto 0) := "00000";
192
  constant OP_TX0            : std_logic_vector(4 downto 0) := "00001";
193
  constant OP_CLR            : std_logic_vector(4 downto 0) := "00010";
194 193 jshamlet
 
195
  -- Integer Division
196 217 jshamlet
  constant OP_IDIV           : std_logic_vector(4 downto 0) := "00011";
197 193 jshamlet
 
198
  -- Unsigned Math Operations
199 217 jshamlet
  constant OP_UMUL           : std_logic_vector(4 downto 0) := "00100";
200
  constant OP_UADD           : std_logic_vector(4 downto 0) := "00101";
201
  constant OP_UADC           : std_logic_vector(4 downto 0) := "00110";
202
  constant OP_USUB           : std_logic_vector(4 downto 0) := "00111";
203
  constant OP_USBC           : std_logic_vector(4 downto 0) := "01000";
204
  constant OP_UCMP           : std_logic_vector(4 downto 0) := "01001";
205 193 jshamlet
 
206
  -- Signed Math Operations
207 217 jshamlet
  constant OP_SMUL           : std_logic_vector(4 downto 0) := "01010";
208
  constant OP_SADD           : std_logic_vector(4 downto 0) := "01011";
209
  constant OP_SSUB           : std_logic_vector(4 downto 0) := "01100";
210
  constant OP_SCMP           : std_logic_vector(4 downto 0) := "01101";
211
  constant OP_SMAG           : std_logic_vector(4 downto 0) := "01110";
212
  constant OP_SNEG           : std_logic_vector(4 downto 0) := "01111";
213 193 jshamlet
 
214
  -- Signed Almost Equal
215 217 jshamlet
  constant OP_ACMP           : std_logic_vector(4 downto 0) := "10000";
216 193 jshamlet
 
217
  -- Carry Flag set/clear
218 217 jshamlet
  constant OP_SCRY           : std_logic_vector(4 downto 0) := "10001";
219 193 jshamlet
 
220
  -- (Un)Signed Decimal Adjust Byte
221 217 jshamlet
  constant OP_UDAB           : std_logic_vector(4 downto 0) := "10010";
222
  constant OP_SDAB           : std_logic_vector(4 downto 0) := "10011";
223 193 jshamlet
 
224
  -- (Un)Signed Decimal Adjust Word
225 217 jshamlet
  constant OP_UDAW           : std_logic_vector(4 downto 0) := "10100";
226
  constant OP_SDAW           : std_logic_vector(4 downto 0) := "10101";
227 193 jshamlet
 
228
  -- Reserved for future use
229 217 jshamlet
  constant OP_RSVD           : std_logic_vector(4 downto 0) := "10110";
230 193 jshamlet
 
231
  -- Byte Swap ( U <> L )
232 217 jshamlet
  constant OP_BSWP           : std_logic_vector(4 downto 0) := "10111";
233 193 jshamlet
 
234
  -- Bitwise Boolean Operations (two operand)
235 217 jshamlet
  constant OP_BOR            : std_logic_vector(4 downto 0) := "11000";
236
  constant OP_BAND           : std_logic_vector(4 downto 0) := "11001";
237
  constant OP_BXOR           : std_logic_vector(4 downto 0) := "11010";
238 193 jshamlet
 
239
  -- In-place Bitwise Boolean Operations (single operand)
240 217 jshamlet
  constant OP_BINV           : std_logic_vector(4 downto 0) := "11011";
241
  constant OP_BSFL           : std_logic_vector(4 downto 0) := "11100";
242
  constant OP_BROL           : std_logic_vector(4 downto 0) := "11101";
243
  constant OP_BSFR           : std_logic_vector(4 downto 0) := "11110";
244
  constant OP_BROR           : std_logic_vector(4 downto 0) := "11111";
245 193 jshamlet
  -------------------------------------------------------------------
246
 
247 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 5):=
248
                                 Address(15 downto 5);
249
  alias Comp_Addr            is Bus_Address(15 downto 5);
250 193 jshamlet
 
251 217 jshamlet
  signal Reg_Addr            : std_logic_vector(4 downto 0) :=
252
                                (others => '0');
253 193 jshamlet
 
254 217 jshamlet
  signal Addr_Match          : std_logic := '0';
255
  signal Wr_En               : std_logic := '0';
256
  signal Wr_Data_q           : DATA_TYPE := (others => '0');
257
  signal Rd_En               : std_logic := '0';
258
 
259 193 jshamlet
  type REG_ARRAY is array( 0 to 7 ) of std_logic_vector(15 downto 0);
260 217 jshamlet
  signal regfile             : REG_ARRAY := (
261
                                 x"0000",x"0000",x"0000",x"0000",
262
                                 x"0000",x"0000",x"0000",x"0000");
263 193 jshamlet
 
264 217 jshamlet
  signal Start               : std_logic := '0';
265
  signal Opcode              : std_logic_vector(4 downto 0) :=
266
                                (others => '0');
267 193 jshamlet
 
268 217 jshamlet
  signal Operand_Sel         : std_logic_vector(2 downto 0) :=
269
                                (others => '0');
270 193 jshamlet
 
271 217 jshamlet
  signal Tolerance           : std_logic_vector(15 downto 0) :=
272
                                (others => '0');
273 193 jshamlet
 
274 217 jshamlet
  signal High_Tol            : signed(16 downto 0) := (others => '0');
275
  signal Low_Tol             : signed(16 downto 0) := (others => '0');
276
  signal Almost_Equal        : std_logic := '0';
277 193 jshamlet
 
278 217 jshamlet
  constant FLAG_Z            : integer := 0;
279
  constant FLAG_C            : integer := 1;
280
  constant FLAG_N            : integer := 2;
281
  constant FLAG_O            : integer := 3;
282
 
283
  signal Flags               : std_logic_vector(3 downto 0) :=
284
                                (others => '0');
285
 
286 193 jshamlet
  type ALU_STATES is ( IDLE, LOAD, EXECUTE,   IDIV_INIT, IDIV_WAIT,
287
                       DAW_INIT,   DAB_INIT,  DAA_WAIT1, DAA_STEP2,
288
                       DAA_WAIT2,  DAA_STEP3, DAA_WAIT3, DAA_STEP4,
289
                       STORE );
290 217 jshamlet
  signal alu_ctrl            : ALU_STATES := IDLE;
291 193 jshamlet
 
292 217 jshamlet
  signal Busy                : std_logic := '0';
293
  signal Busy_q              : std_logic := '0';
294 193 jshamlet
 
295 217 jshamlet
  signal Operand_1           : std_logic_vector(15 downto 0) :=
296
                                (others => '0');
297 193 jshamlet
 
298 217 jshamlet
  signal Operand_2           : std_logic_vector(15 downto 0) :=
299
                                (others => '0');
300 193 jshamlet
 
301 217 jshamlet
  alias  Dividend            is Operand_1;
302
  alias  Divisor             is Operand_2;
303 193 jshamlet
 
304 217 jshamlet
  alias  u_Operand_1         is Operand_1;
305
  alias  u_Operand_2         is Operand_2;
306 193 jshamlet
 
307 217 jshamlet
  alias  u_Addend_1          is Operand_1;
308
  alias  u_Addend_2          is Operand_2;
309 193 jshamlet
 
310 217 jshamlet
  signal s_Operand_1         : signed(16 downto 0) := (others => '0');
311
  signal s_Operand_2         : signed(16 downto 0) := (others => '0');
312 193 jshamlet
 
313 217 jshamlet
  alias  s_Addend_1          is S_Operand_1;
314
  alias  s_Addend_2          is S_Operand_2;
315 193 jshamlet
 
316 217 jshamlet
  signal u_accum             : std_logic_vector(16 downto 0) :=
317
                               (others => '0');
318
  alias  u_data              is u_accum(15 downto 0);
319
  alias  u_sign              is u_accum(15);
320
  alias  u_carry             is u_accum(16);
321 193 jshamlet
 
322 217 jshamlet
  signal u_prod              : std_logic_vector(31 downto 0) :=
323
                                (others => '0');
324 193 jshamlet
 
325 217 jshamlet
  signal s_accum             : signed(16 downto 0) := (others => '0');
326
  alias  s_data              is s_accum(15 downto 0);
327
  alias  s_sign              is s_accum(15);
328
  alias  s_ovf               is s_accum(16);
329 193 jshamlet
 
330 217 jshamlet
  signal s_prod              : signed(33 downto 0) := (others => '0');
331 193 jshamlet
 
332 217 jshamlet
  signal IDIV_Start          : std_logic := '0';
333
  signal IDIV_Busy           : std_logic := '0';
334 193 jshamlet
 
335 217 jshamlet
  constant DIV_WIDTH         : integer := 16; -- Width of Operands
336 193 jshamlet
 
337 217 jshamlet
  signal q                   : std_logic_vector(DIV_WIDTH*2-1 downto 0) :=
338
                                (others => '0');
339 193 jshamlet
 
340 217 jshamlet
  signal diff                : std_logic_vector(DIV_WIDTH downto 0) :=
341
                                (others => '0');
342 193 jshamlet
 
343 217 jshamlet
  signal count               : integer range 0 to DIV_WIDTH + 1 := 0;
344 213 jshamlet
 
345 217 jshamlet
  signal Quotient_i          : std_logic_vector(15 downto 0) :=
346
                                (others => '0');
347 213 jshamlet
 
348 217 jshamlet
  signal Quotient            : std_logic_vector(15 downto 0) :=
349
                                (others => '0');
350 193 jshamlet
 
351 217 jshamlet
  signal Remainder_i         : std_logic_vector(15 downto 0) :=
352
                                (others => '0');
353
 
354
  signal Remainder           : std_logic_vector(15 downto 0) :=
355
                                (others => '0');
356
 
357
  signal DAA_intreg          : std_logic_vector(15 downto 0) :=
358
                                (others => '0');
359
 
360
  signal DAA_mode            : std_logic := '0';
361
  signal DAA_sign            : std_logic := '0';
362
  signal DAA_p4              : std_logic_vector(3 downto 0) :=
363
                                (others => '0');
364
 
365
  signal DAA_p3              : std_logic_vector(3 downto 0) :=
366
                                (others => '0');
367
 
368
  signal DAA_p2              : std_logic_vector(3 downto 0) :=
369
                                (others => '0');
370
 
371
  alias  DAA_p1              is Quotient(3 downto 0);
372
  alias  DAA_p0              is Remainder(3 downto 0);
373
  signal DAA_result          : std_logic_vector(19 downto 0) :=
374
                                (others => '0');
375
 
376 193 jshamlet
begin
377
 
378 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
379 193 jshamlet
 
380
  -- Sign-extend the base operands to created operands for signed math
381 217 jshamlet
  S_Operand_1                <= signed(Operand_1(15) & Operand_1);
382
  S_Operand_2                <= signed(Operand_2(15) & Operand_2);
383 193 jshamlet
 
384
  -- Compute the tolerance bounds for the Almost Equal function
385 217 jshamlet
  High_Tol                   <= S_Operand_2 + signed('0' & Tolerance);
386
  Low_Tol                    <= S_Operand_2 - signed('0' & Tolerance);
387 193 jshamlet
 
388
  -- Combinational logic for the Decimal Adjust logic
389 217 jshamlet
  DAA_result                 <= DAA_p4 & DAA_p3 & DAA_p2 & DAA_p1 & DAA_p0;
390 193 jshamlet
 
391
  -- Combinational logic for the division logic
392 217 jshamlet
  diff                       <= ('0' & Q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
393
                                ('0' & Divisor);
394
  Quotient_i                 <= q(DIV_WIDTH-1 downto 0);
395
  Remainder_i                <= q(DIV_WIDTH*2-1 downto DIV_WIDTH);
396 193 jshamlet
 
397
  ALU_proc: process( Clock, Reset )
398 217 jshamlet
    variable Reg_Sel         : integer;
399
    variable Oper_Sel        : integer;
400 193 jshamlet
  begin
401
    if( Reset = Reset_Level )then
402 217 jshamlet
      Wr_En                  <= '0';
403
      Wr_Data_q              <= (others => '0');
404
      Rd_En                  <= '0';
405
      Rd_Data                <= OPEN8_NULLBUS;
406
      Reg_Addr               <= (others => '0');
407
      Opcode                 <= (others => '0');
408
      Operand_Sel            <= (others => '0');
409
      Tolerance              <= (others => '0');
410
      Start                  <= '0';
411
      Busy_q                 <= '0';
412
      Interrupt              <= '0';
413 193 jshamlet
      for i in 0 to 7 loop
414 217 jshamlet
        regfile(i)           <= (others => '0');
415 193 jshamlet
      end loop;
416 217 jshamlet
      alu_ctrl               <= IDLE;
417
      Operand_1              <= (others => '0');
418
      Operand_2              <= (others => '0');
419
      u_accum                <= (others => '0');
420
      u_prod                 <= (others => '0');
421
      s_accum                <= (others => '0');
422
      s_prod                 <= (others => '0');
423
      Quotient               <= (others => '0');
424
      Remainder              <= (others => '0');
425
      Flags                  <= (others => '0');
426
      Almost_Equal           <= '0';
427
      Busy                   <= '0';
428
      DAA_mode               <= '0';
429
      DAA_sign               <= '0';
430
      DAA_intreg             <= (others => '0');
431
      DAA_p4                 <= (others => '0');
432
      DAA_p3                 <= (others => '0');
433
      DAA_p2                 <= (others => '0');
434
      IDIV_Start             <= '0';
435
      q                      <= (others => '0');
436
      count                  <= DIV_WIDTH;
437
      IDIV_Busy              <= '0';
438 193 jshamlet
    elsif( rising_edge(Clock) )then
439
      -- For convenience, convert these to integers and assign them to
440
      --  variables
441 217 jshamlet
      Reg_Sel                := conv_integer(Reg_Addr(3 downto 1));
442
      Oper_Sel               := conv_integer(Operand_Sel);
443 193 jshamlet
 
444 217 jshamlet
      Wr_En                  <= Addr_Match and Wr_Enable;
445
      Wr_Data_q              <= Wr_Data;
446
      Reg_Addr               <= Bus_Address(4 downto 0);
447 193 jshamlet
 
448 217 jshamlet
      Start                  <= '0';
449 193 jshamlet
      if( Wr_En = '1' )then
450
        case( Reg_Addr )is
451
          -- Even addresses go to the lower byte of the register
452
          when "00000" | "00010" | "00100" | "00110" |
453
               "01000" | "01010" | "01100" | "01110" =>
454
            regfile(Reg_Sel)(7 downto 0) <= Wr_Data_q;
455
 
456
          -- Odd addresses go to the upper byte of the register
457
          when "00001" | "00011" | "00101" | "00111" |
458
               "01001" | "01011" | "01101" | "01111" =>
459
            regfile(Reg_Sel)(15 downto 8)<= Wr_Data_q;
460
 
461
          when "11100" => -- 0x1C -> Tolerance.l
462
            Tolerance(7 downto 0) <= Wr_Data_q;
463
 
464
          when "11101" => -- 0x1D -> Tolerance.u
465
            Tolerance(15 downto 8) <= Wr_Data_q;
466
 
467
          when "11110" => -- 0x1E -> Opcode register
468 217 jshamlet
            Opcode           <= Wr_Data_q(7 downto 3);
469
            Operand_Sel      <= Wr_Data_q(2 downto 0);
470 193 jshamlet
 
471
          when "11111" => -- 0x1F -> Status/Start register
472 217 jshamlet
            Start            <= '1';
473 193 jshamlet
 
474
          when others => null;
475
        end case;
476
      end if;
477
 
478 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
479
      Rd_En                  <= Addr_Match and Rd_Enable;
480 193 jshamlet
 
481
      if( Rd_En = '1' )then
482
        case( Reg_Addr )is
483
          when "00000" | "00010" | "00100" | "00110" |
484
               "01000" | "01010" | "01100" | "01110" =>
485 217 jshamlet
            Rd_Data          <= regfile(Reg_Sel)(7 downto 0);
486 193 jshamlet
          when "00001" | "00011" | "00101" | "00111" |
487
               "01001" | "01011" | "01101" | "01111" =>
488 217 jshamlet
            Rd_Data          <= regfile(Reg_Sel)(15 downto 8);
489 193 jshamlet
          when "11100" => -- 0x1C -> Tolerance.l
490 217 jshamlet
            Rd_Data          <= Tolerance(7 downto 0);
491 193 jshamlet
          when "11101" => -- 0x1D -> Tolerance.u
492 217 jshamlet
            Rd_Data          <= Tolerance(15 downto 8);
493 193 jshamlet
          when "11110" => -- 0x1E -> Opcode register
494 217 jshamlet
            Rd_Data          <= Opcode & Operand_Sel;
495 193 jshamlet
          when "11111" => -- 0x1F -> Flags & Status register
496 217 jshamlet
            Rd_Data          <= Busy & "000" & Flags;
497 193 jshamlet
 
498
          when others => null;
499
        end case;
500
      end if;
501
 
502 217 jshamlet
      Busy                   <= '1';
503
      IDIV_Start             <= '0';
504 193 jshamlet
      case( alu_ctrl )is
505
        when IDLE =>
506 217 jshamlet
          Busy               <= '0';
507 193 jshamlet
          if( Start = '1' )then
508 217 jshamlet
            alu_ctrl         <= LOAD;
509 193 jshamlet
          end if;
510
 
511
        -- Load the operands from the reg file. We also check for specific
512
        --  opcodes to set the DAA mode (signed vs unsigned). This is the only
513
        --  place where we READ the register file outside of the bus interface
514
        when LOAD =>
515 217 jshamlet
          Operand_1          <= regfile(0);
516
          Operand_2          <= regfile(Oper_Sel);
517
          DAA_mode           <= '0';
518 193 jshamlet
          if( Opcode = OP_SDAW or Opcode = OP_SDAB )then
519 217 jshamlet
            DAA_mode         <= '1';
520 193 jshamlet
          end if;
521 217 jshamlet
          alu_ctrl           <= EXECUTE;
522 193 jshamlet
 
523
        -- Now that the operands are loaded, we can execute the actual math
524
        --  operations. We do it with separate operand registers to pipeline
525
        --  the logic.
526
        when EXECUTE =>
527 217 jshamlet
          alu_ctrl           <= STORE;
528 193 jshamlet
          case( Opcode)is
529
            when OP_T0X =>
530 217 jshamlet
              u_accum        <= '0' & Operand_1;
531 193 jshamlet
 
532
            when OP_TX0 =>
533 217 jshamlet
              u_accum        <= '0' & Operand_2;
534 193 jshamlet
 
535
            when OP_CLR | OP_SCRY =>
536 217 jshamlet
              u_accum        <= (others => '0');
537 193 jshamlet
 
538
            when OP_BSWP =>
539 217 jshamlet
              u_accum        <= '0' &
540
                                Operand_2(7 downto 0) &
541
                                Operand_2(15 downto 8);
542 193 jshamlet
 
543
            when OP_SMAG =>
544 217 jshamlet
              s_accum        <= S_Operand_2;
545 193 jshamlet
              if( S_Operand_2 < 0)then
546 217 jshamlet
                s_accum      <= -S_Operand_2;
547 193 jshamlet
              end if;
548
 
549
            when OP_SNEG =>
550 217 jshamlet
              s_accum        <= -S_Operand_2;
551 193 jshamlet
 
552
            when OP_SMUL =>
553 217 jshamlet
              s_prod         <= S_Operand_1 * S_Operand_2;
554 193 jshamlet
 
555
            when OP_UMUL =>
556 217 jshamlet
              u_prod         <= U_Operand_1 * U_Operand_2;
557 193 jshamlet
 
558
            when OP_SADD =>
559 217 jshamlet
              s_accum        <= S_Addend_1  + S_Addend_2;
560 193 jshamlet
 
561
            when OP_UADD =>
562 217 jshamlet
              u_accum        <= ('0' & Operand_1) +
563
                                ('0' & Operand_2);
564 193 jshamlet
 
565
            when OP_UADC =>
566 217 jshamlet
              u_accum        <= ('0' & Operand_1) +
567
                                ('0' & Operand_2) +
568
                                Flags(FLAG_C);
569 193 jshamlet
 
570
            when OP_SSUB | OP_SCMP =>
571 217 jshamlet
              s_accum        <= S_Addend_1 - S_Addend_2;
572 193 jshamlet
 
573
            when OP_USUB | OP_UCMP =>
574 217 jshamlet
              u_accum        <= ('0' & U_Addend_1) -
575
                                ('0' & U_Addend_2);
576 193 jshamlet
 
577
            when OP_USBC =>
578 217 jshamlet
              u_accum        <= ('0' & U_Addend_1) -
579
                                ('0' & U_Addend_2) -
580
                                Flags(FLAG_C);
581 193 jshamlet
 
582
            when OP_ACMP =>
583
              -- Perform the function
584
              -- AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
585 217 jshamlet
              Almost_Equal   <= '0';
586 193 jshamlet
              if( (S_Addend_1 <= High_Tol) and
587
                  (S_Addend_1 >= Low_Tol) )then
588 217 jshamlet
                Almost_Equal <= '1';
589 193 jshamlet
              end if;
590
 
591
            when OP_BINV =>
592 217 jshamlet
              u_accum        <= '0' & (not U_Operand_1);
593 193 jshamlet
 
594
            when OP_BSFL =>
595 217 jshamlet
              u_accum        <= U_Operand_1 & '0';
596 193 jshamlet
 
597
            when OP_BROL =>
598 217 jshamlet
              u_accum        <= U_Operand_1 & Flags(FLAG_C);
599 193 jshamlet
 
600
            when OP_BSFR =>
601 217 jshamlet
              u_accum        <= "00" & U_Operand_1(15 downto 1);
602 193 jshamlet
 
603
            when OP_BROR =>
604 217 jshamlet
              u_accum        <= U_Operand_1(0) & Flags(FLAG_C) &
605
                                U_Operand_1(15 downto 1);
606 193 jshamlet
 
607
            when OP_BOR  =>
608 217 jshamlet
              u_accum        <= '0' & (U_Operand_1 or U_Operand_2);
609 193 jshamlet
 
610
            when OP_BAND =>
611 217 jshamlet
              u_accum        <= '0' & (U_Operand_1 and U_Operand_2);
612 193 jshamlet
 
613
            when OP_BXOR =>
614 217 jshamlet
              u_accum        <= '0' & (U_Operand_1 xor U_Operand_2);
615 193 jshamlet
 
616
        -- Division unit has a longer latency, so we need to wait for its busy
617
        --  signal to return low before storing results. Trigger the engine,
618
        --  and then jump to the wait state for it to finish
619
            when OP_IDIV =>
620 217 jshamlet
              IDIV_Start     <= '1';
621
              alu_ctrl       <= IDIV_INIT;
622 193 jshamlet
 
623
        -- Decimal Adjust Word initialization
624
        --  Stores the sign bit for later use setting the N flag
625
        --  Assigns Operand_1 to register as-is
626
        --  If the sign bit is set, do a 2's complement of the register
627
            when OP_UDAW | OP_SDAW =>
628 217 jshamlet
              IDIV_Start     <= '1';
629
              DAA_sign       <= Operand_2(15);
630
              Operand_1      <= Operand_2;
631 193 jshamlet
              if( (Operand_2(15) and DAA_mode) = '1' )then
632 217 jshamlet
                Operand_1    <= (not Operand_2) + 1;
633 193 jshamlet
              end if;
634 217 jshamlet
              Operand_2      <= x"2710";
635
              alu_ctrl       <= DAW_INIT;
636 193 jshamlet
 
637
        -- Decimal Adjust Byte initialization
638
        --  Stores the sign bit for later use setting the N flag
639
        --  Assigns Operand_1 to the lower byte of the register
640
        --  If the sign bit is set, do a 2's complement of the register
641
            when OP_UDAB | OP_SDAB =>
642 217 jshamlet
              IDIV_Start     <= '1';
643
              DAA_p4         <= (others => '0');
644
              DAA_p3         <= (others => '0');
645
              DAA_sign       <= Operand_2(7);
646
              Operand_1      <= x"00" & Operand_2(7 downto 0);
647 193 jshamlet
              if( (Operand_2(7) and DAA_mode) = '1' )then
648 217 jshamlet
                Operand_1    <= ((not Operand_2) + 1) and x"00FF";
649 193 jshamlet
              end if;
650 217 jshamlet
              Operand_2      <= x"0064";
651
              alu_ctrl       <= DAB_INIT;
652 193 jshamlet
 
653
            when others => null;
654
          end case;
655
 
656
        -- These three states look superfluous, but simplify the state machine
657
        --  logic enough to improve performance. Leave them.
658
        when IDIV_INIT =>
659
          if( IDIV_Busy = '1' )then
660 217 jshamlet
            alu_ctrl         <= IDIV_WAIT;
661 193 jshamlet
          end if;
662
 
663
        when DAW_INIT =>
664
          if( IDIV_Busy = '1' )then
665 217 jshamlet
            alu_ctrl         <= DAA_WAIT1;
666 193 jshamlet
          end if;
667
 
668
        when DAB_INIT =>
669
          if( IDIV_Busy = '1' )then
670 217 jshamlet
            alu_ctrl         <= DAA_WAIT3;
671 193 jshamlet
          end if;
672
 
673
        when DAA_WAIT1 =>
674
          if( IDIV_Busy = '0' )then
675 217 jshamlet
            DAA_p4           <= Quotient_i(3 downto 0);
676
            DAA_intreg       <= Remainder_i;
677
            alu_ctrl         <= DAA_STEP2;
678 193 jshamlet
          end if;
679
 
680
        when DAA_STEP2 =>
681 217 jshamlet
          Operand_1          <= DAA_intreg;
682
          Operand_2          <= x"03E8";
683
          IDIV_Start         <= '1';
684 193 jshamlet
          if( IDIV_Busy = '1' )then
685 217 jshamlet
            alu_ctrl         <= DAA_WAIT2;
686 193 jshamlet
          end if;
687
 
688
        when DAA_WAIT2 =>
689
          if( IDIV_Busy = '0' )then
690 217 jshamlet
            DAA_p3           <= Quotient_i(3 downto 0);
691
            DAA_intreg       <= Remainder_i;
692
            alu_ctrl         <= DAA_STEP3;
693 193 jshamlet
          end if;
694
 
695
        when DAA_STEP3 =>
696 217 jshamlet
          Operand_1          <= DAA_intreg;
697
          Operand_2          <= x"0064";
698
          IDIV_Start         <= '1';
699 193 jshamlet
          if( IDIV_Busy = '1' )then
700 217 jshamlet
            alu_ctrl         <= DAA_WAIT3;
701 193 jshamlet
          end if;
702
 
703
        when DAA_WAIT3 =>
704
          if( IDIV_Busy = '0' )then
705 217 jshamlet
            DAA_p2           <= Quotient_i(3 downto 0);
706
            DAA_intreg       <= Remainder_i;
707
            alu_ctrl         <= DAA_STEP4;
708 193 jshamlet
          end if;
709
 
710
        when DAA_STEP4 =>
711 217 jshamlet
          Operand_1          <= DAA_intreg;
712
          Operand_2          <= x"000A";
713
          IDIV_Start         <= '1';
714 193 jshamlet
          if( IDIV_Busy = '1' )then
715 217 jshamlet
            alu_ctrl         <= IDIV_WAIT;
716 193 jshamlet
          end if;
717
 
718
        when IDIV_WAIT =>
719
          if( IDIV_Busy = '0' )then
720 217 jshamlet
            Quotient         <= Quotient_i;
721
            Remainder        <= Remainder_i;
722
            alu_ctrl         <= STORE;
723 193 jshamlet
          end if;
724
 
725
        -- All ALU writes to the register file go through here. This is also
726
        --  where the flag register gets updated. This should be the only
727
        --  place where the register file gets WRITTEN outside of the bus
728
        --  interface.
729
        when STORE =>
730 217 jshamlet
          Flags              <= (others => '0');
731 193 jshamlet
          case( Opcode)is
732
            when OP_T0X | OP_CLR | OP_BSWP =>
733
              regfile(Oper_Sel) <= u_data;
734 217 jshamlet
              Flags(FLAG_Z)  <= nor_reduce(u_data);
735
              Flags(FLAG_N)  <= u_sign;
736 193 jshamlet
 
737
            when OP_TX0  =>
738 217 jshamlet
              regfile(0)     <= u_data;
739
              Flags(FLAG_Z)  <= nor_reduce(u_data);
740
              Flags(FLAG_N)  <= u_sign;
741 193 jshamlet
 
742
            when OP_SCRY =>
743 217 jshamlet
              Flags(FLAG_C)  <= '0';
744 193 jshamlet
              if( Oper_Sel > 0 )then
745
                Flags(FLAG_C)<= '1';
746
              end if;
747
 
748
            when OP_IDIV =>
749 217 jshamlet
              regfile(0)     <= Quotient;
750 193 jshamlet
              regfile(Oper_Sel) <= Remainder;
751 217 jshamlet
              Flags(FLAG_Z)  <= nor_reduce(Quotient);
752 193 jshamlet
 
753
            when OP_SMAG | OP_SNEG | OP_SADD | OP_SSUB =>
754 217 jshamlet
              regfile(0)     <= std_logic_vector(s_data);
755
              Flags(FLAG_N)  <= s_sign;
756
              Flags(FLAG_Z)  <= nor_reduce(std_logic_vector(s_data));
757
              Flags(FLAG_O)  <= s_ovf xor s_sign;
758 193 jshamlet
 
759
            when OP_SMUL =>
760 217 jshamlet
              regfile(0)     <= std_logic_vector(s_prod(15 downto 0));
761
              regfile(1)     <= std_logic_vector(s_prod(31 downto 16));
762
              Flags(FLAG_N)  <= s_prod(33) or s_prod(32);
763
              Flags(FLAG_Z)  <= nor_reduce(std_logic_vector(s_prod));
764 193 jshamlet
 
765
            when OP_UMUL =>
766 217 jshamlet
              regfile(0)     <= u_prod(15 downto 0);
767
              regfile(1)     <= u_prod(31 downto 16);
768
              Flags(FLAG_N)  <= u_prod(31);
769
              Flags(FLAG_Z)  <= nor_reduce(u_prod);
770 193 jshamlet
 
771
            when OP_UADD | OP_USUB =>
772 217 jshamlet
              regfile(0)     <= u_data;
773
              Flags(FLAG_Z)  <= nor_reduce(u_data);
774
              Flags(FLAG_N)  <= u_sign;
775
              Flags(FLAG_C)  <= u_carry;
776 193 jshamlet
 
777
            when OP_SCMP =>
778 217 jshamlet
              Flags(FLAG_N)  <= s_ovf;
779
              Flags(FLAG_Z)  <= nor_reduce(std_logic_vector(s_data));
780
              Flags(FLAG_O)  <= s_accum(16) xor s_accum(15);
781 193 jshamlet
 
782
            when OP_UCMP =>
783 217 jshamlet
              Flags(FLAG_Z)  <= nor_reduce(u_data);
784
              Flags(FLAG_C)  <= u_carry;
785 193 jshamlet
 
786
            when OP_ACMP =>
787 217 jshamlet
              Flags(FLAG_Z)  <= Almost_Equal;
788 193 jshamlet
 
789
            when OP_UDAB | OP_SDAB =>
790
              regfile(Oper_Sel) <= DAA_result(15 downto 0);
791 217 jshamlet
              Flags(FLAG_Z)  <= nor_reduce(DAA_result);
792
              Flags(FLAG_N)  <= DAA_sign;
793 193 jshamlet
 
794
            when OP_UDAW | OP_SDAW =>
795
              regfile(Oper_Sel) <= DAA_result(15 downto 0);
796
              Flags(3 downto 0) <= DAA_result(19 downto 16);
797
              if( DAA_mode = '1' )then
798
                Flags(FLAG_N) <= DAA_sign;
799
              end if;
800
 
801
            when OP_BOR  | OP_BAND | OP_BXOR =>
802 217 jshamlet
              regfile(0)     <= u_data;
803
              Flags(FLAG_Z)  <= nor_reduce(u_data);
804
              Flags(FLAG_N)  <= u_sign;
805 193 jshamlet
 
806
            when OP_BINV =>
807
              regfile(Oper_Sel) <= u_data;
808 217 jshamlet
              Flags(FLAG_Z)  <= nor_reduce(u_data);
809
              Flags(FLAG_N)  <= u_sign;
810 193 jshamlet
 
811
            when OP_BSFL | OP_BROL | OP_BSFR | OP_BROR =>
812
              regfile(Oper_Sel) <= u_data;
813 217 jshamlet
              Flags(FLAG_Z)  <= nor_reduce(u_data);
814
              Flags(FLAG_N)  <= u_sign;
815
              Flags(FLAG_C)  <= u_carry;
816 193 jshamlet
 
817
            when others => null;
818
          end case;
819 217 jshamlet
          alu_ctrl           <= IDLE;
820 193 jshamlet
 
821
        when others =>
822
          null;
823
 
824
      end case;
825
 
826 217 jshamlet
      IDIV_Busy              <= '0';
827 193 jshamlet
      if( IDIV_Start = '1' )then
828 217 jshamlet
        IDIV_Busy            <= '1';
829
        count                <= 0;
830
        q                    <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
831 193 jshamlet
      elsif( count < DIV_WIDTH )then
832 217 jshamlet
        IDIV_Busy            <= '1';
833
        count                <= count + 1;
834
        q                    <= diff(DIV_WIDTH-1 downto 0) &
835
                              q(DIV_WIDTH-2 downto 0) &
836
                              '1';
837 193 jshamlet
        if( diff(DIV_WIDTH) = '1' )then
838 217 jshamlet
          q                  <= q(DIV_WIDTH*2-2 downto 0) & '0';
839 193 jshamlet
        end if;
840
      end if;
841
 
842
      -- Fire on the falling edge of Busy
843 217 jshamlet
      Busy_q                 <= Busy;
844
      Interrupt              <= not Busy and Busy_q;
845 193 jshamlet
 
846
    end if;
847
  end process;
848
 
849
end architecture;

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