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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_async_serial.vhd] - Blame information for rev 329

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1 207 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 213 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 207 jshamlet
--
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-- VHDL Units :  o8_async_serial
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-- Description:  Provides a single 8-bit, asynchronous transceiver. While the
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--               width is fixed at 8-bits, the bit rate and parity controls
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--               are settable via generics.
28 209 jshamlet
--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x00  AAAAAAAA TX Data (WR) RX Data (RD)             (RW)
32 274 jshamlet
--   0x01  EDCBA--- Status                                (RO*)
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--                  A: RX Parity Error (write to clear)
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--                  B: RX FIFO Empty
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--                  C: RX FIFO almost full (922/1024)
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--                  D: TX FIFO Empty
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--                  E: TX FIFO almost full (922/1024)
38 213 jshamlet
--
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-- Note: The baud rate generator will produce an approximate frequency. The
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--        final bit rate should be within +/- 1% of the true bit rate to
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--        ensure the receiver can successfully receive. With a sufficiently
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--        high core clock, this is generally achievable for common PC serial
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--        data rates.
44 213 jshamlet
--
45
-- Revision History
46
-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
48
-- Seth Henry      12/20/19 Design Start
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-- Seth Henry      04/10/20 Code cleanup and register documentation
50 224 jshamlet
-- Seth Henry      04/16/20 Modified to use Open8 bus record
51 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
52 320 jshamlet
-- Seth Henry       6/06/23 Inverted flow control signals for standard EIA-232
53 207 jshamlet
 
54
library ieee;
55
use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
58
use ieee.std_logic_misc.all;
59
 
60
library work;
61
  use work.open8_pkg.all;
62
 
63
entity o8_async_serial is
64
generic(
65 217 jshamlet
  Disable_Transmit           : boolean := FALSE;
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  Disable_Receive            : boolean := FALSE;
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  Bit_Rate                   : real;
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  Enable_Parity              : boolean;
69
  Parity_Odd_Even_n          : std_logic;
70 224 jshamlet
  Clock_Frequency            : real;
71 217 jshamlet
  Address                    : ADDRESS_TYPE
72 207 jshamlet
);
73
port(
74 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
75 244 jshamlet
  Write_Qual                 : in  std_logic := '1';
76 217 jshamlet
  Rd_Data                    : out DATA_TYPE;
77 207 jshamlet
  --
78 217 jshamlet
  TX_Out                     : out std_logic;
79 320 jshamlet
  CTS_In                     : in  std_logic := '0';
80 244 jshamlet
  RX_In                      : in  std_logic := '1';
81 217 jshamlet
  RTS_Out                    : out std_logic
82 207 jshamlet
);
83
end entity;
84
 
85
architecture behave of o8_async_serial is
86
 
87 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
88
  alias Reset                is Open8_Bus.Reset;
89
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
90 244 jshamlet
  alias Wr_En                is Open8_Bus.Wr_En;
91
  alias Wr_Data              is Open8_Bus.Wr_Data;
92
  alias Rd_En                is Open8_Bus.Rd_En;
93 224 jshamlet
 
94 207 jshamlet
  signal FIFO_Reset          : std_logic := '0';
95
 
96
  constant User_Addr         : std_logic_vector(15 downto 1) :=
97
                                Address(15 downto 1);
98 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
99 207 jshamlet
  signal Addr_Match          : std_logic := '0';
100
 
101 244 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(0);
102
  signal Reg_Sel_q           : std_logic := '0';
103
  signal Wr_En_d             : std_logic := '0';
104
  signal Wr_En_q             : std_logic := '0';
105
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
106
  signal Wr_Data_q           : DATA_TYPE := x"00";
107
  signal Rd_En_d             : std_logic := '0';
108
  signal Rd_En_q             : std_logic := '0';
109 207 jshamlet
 
110
  signal TX_FIFO_Wr_En       : std_logic := '0';
111 244 jshamlet
  signal TX_FIFO_Wr_Data     : DATA_TYPE := x"00";
112 207 jshamlet
  signal TX_FIFO_Rd_En       : std_logic := '0';
113
  signal TX_FIFO_Empty       : std_logic := '0';
114
  signal TX_FIFO_AFull       : std_logic := '0';
115
  signal TX_FIFO_Rd_Data     : DATA_TYPE := x"00";
116
 
117
  alias  Tx_Data             is TX_FIFO_Rd_Data;
118
 
119
  type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
120
  signal TX_Ctrl             : TX_CTRL_STATES := IDLE;
121
 
122
  signal TX_Xmit             : std_logic := '0';
123
  signal TX_Done             : std_logic := '0';
124
 
125 224 jshamlet
  constant BAUD_RATE_DIV     : integer := integer(Clock_Frequency / Bit_Rate);
126 207 jshamlet
 
127
  signal CTS_sr              : std_logic_vector(3 downto 0) := "0000";
128
  alias  CTS_Okay            is CTS_sr(3);
129
 
130
  signal RX_FIFO_Wr_En       : std_logic := '0';
131 209 jshamlet
  signal RX_FIFO_Wr_Data     : DATA_TYPE := x"00";
132
  signal RX_FIFO_Rd_En       : std_logic := '0';
133
  signal RX_FIFO_Empty       : std_logic := '0';
134
  signal RX_FIFO_AFull       : std_logic := '0';
135
  signal RX_FIFO_Rd_Data     : DATA_TYPE := x"00";
136 207 jshamlet
 
137 244 jshamlet
  signal Rx_PErr             : std_logic := '0';
138
  signal RX_Parity_Err       : std_logic := '0';
139
 
140 207 jshamlet
begin
141
 
142
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
143 244 jshamlet
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
144
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
145 207 jshamlet
 
146
  io_reg: process( Clock, Reset )
147
  begin
148
    if( Reset = Reset_Level )then
149 244 jshamlet
      Reg_Sel_q              <= '0';
150
      Wr_En_q                <= '0';
151
      Wr_Data_q              <= x"00";
152
      Rd_En_q                <= '0';
153 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
154
      RTS_Out                <= '0';
155 244 jshamlet
      RX_Parity_Err          <= '0';
156 207 jshamlet
    elsif( rising_edge( Clock ) )then
157 244 jshamlet
      Reg_Sel_q              <= Reg_Sel_d;
158
 
159
      Wr_En_q                <= Wr_En_d;
160
      Wr_Data_q              <= Wr_Data_d;
161
 
162
      TX_FIFO_Wr_En          <= Wr_En_q and not Reg_Sel_q;
163
      TX_FIFO_Wr_Data        <= Wr_Data_q;
164
 
165
      if( Rx_PErr = '1' )then
166
        RX_Parity_Err        <= '1';
167
      elsif( Wr_En_q = '1' and Reg_Sel_q = '1' and Write_Qual = '1' )then
168
        RX_Parity_Err        <= '0';
169
      end if;
170
 
171
      Rd_En_q                <= Rd_En_d;
172 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
173 244 jshamlet
      if( Rd_En_q = '1' and Reg_Sel_q = '1' )then
174 293 jshamlet
        Rd_Data(3)           <= RX_Parity_Err;
175 217 jshamlet
        Rd_Data(4)           <= RX_FIFO_Empty;
176
        Rd_Data(5)           <= RX_FIFO_AFull;
177
        Rd_Data(6)           <= TX_FIFO_Empty;
178
        Rd_Data(7)           <= TX_FIFO_AFull;
179 207 jshamlet
      end if;
180 244 jshamlet
      if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
181 217 jshamlet
        Rd_Data              <= RX_FIFO_Rd_Data;
182 207 jshamlet
      end if;
183 320 jshamlet
      RTS_Out                <= RX_FIFO_AFull;
184 244 jshamlet
 
185 207 jshamlet
    end if;
186
  end process;
187
 
188 213 jshamlet
TX_Disabled : if( Disable_Transmit )generate
189
 
190
  TX_FIFO_Empty              <= '1';
191
  TX_FIFO_AFull              <= '0';
192
  TX_Out                     <= '1';
193
 
194
end generate;
195
 
196
TX_Enabled : if( not Disable_Transmit )generate
197
 
198 207 jshamlet
  FIFO_Reset                 <= '1' when Reset = Reset_Level else '0';
199
 
200
  U_TX_FIFO : entity work.fifo_1k_core
201
  port map(
202
    aclr                     => FIFO_Reset,
203
    clock                    => Clock,
204
    data                     => TX_FIFO_Wr_Data,
205
    rdreq                    => TX_FIFO_Rd_En,
206
    wrreq                    => TX_FIFO_Wr_En,
207
    empty                    => TX_FIFO_Empty,
208
    almost_full              => TX_FIFO_AFull,
209
    q                        => TX_FIFO_Rd_Data
210
  );
211
 
212
  tx_FSM: process( Clock, Reset )
213
  begin
214
    if( Reset = Reset_Level )then
215
      TX_Ctrl                <= IDLE;
216
      TX_Xmit                <= '0';
217
      TX_FIFO_Rd_En          <= '0';
218
      CTS_sr                 <= (others => '0');
219
    elsif( rising_edge(Clock) )then
220
      TX_Xmit                <= '0';
221
      TX_FIFO_Rd_En          <= '0';
222 320 jshamlet
      CTS_sr                 <= CTS_sr(2 downto 0) & (not CTS_In);
223 207 jshamlet
 
224
      case( TX_Ctrl )is
225
        when IDLE =>
226
          if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
227
            TX_FIFO_Rd_En    <= '1';
228
            TX_Ctrl          <= TX_BYTE;
229
          end if;
230
 
231
        when TX_BYTE =>
232
          TX_Xmit            <= '1';
233
          TX_Ctrl            <= TX_START;
234
 
235
        when TX_START =>
236
          if( Tx_Done = '0' )then
237
            TX_Ctrl          <= TX_WAIT;
238
          end if;
239
 
240
        when TX_WAIT =>
241
          if( Tx_Done = '1' )then
242
            TX_Ctrl          <= IDLE;
243
          end if;
244
 
245
        when others => null;
246
      end case;
247
 
248
    end if;
249
  end process;
250
 
251
  U_TX : entity work.async_ser_tx
252
  generic map(
253
    Reset_Level              => Reset_Level,
254
    Enable_Parity            => Enable_Parity,
255
    Parity_Odd_Even_n        => Parity_Odd_Even_n,
256
    Clock_Divider            => BAUD_RATE_DIV
257
  )
258
  port map(
259
    Clock                    => Clock,
260
    Reset                    => Reset,
261
    --
262
    Tx_Data                  => Tx_Data,
263
    Tx_Valid                 => TX_Xmit,
264
    --
265
    Tx_Out                   => TX_Out,
266
    Tx_Done                  => Tx_Done
267
  );
268
 
269 213 jshamlet
end generate;
270
 
271 244 jshamlet
RX_Disabled : if( Disable_Receive )generate
272 213 jshamlet
 
273 244 jshamlet
  Rx_PErr                    <= '0';
274 213 jshamlet
  RX_FIFO_Empty              <= '1';
275
  RX_FIFO_AFull              <= '0';
276
  RX_FIFO_Rd_Data            <= x"00";
277
 
278
end generate;
279
 
280
RX_Enabled : if( not Disable_Receive )generate
281
 
282 207 jshamlet
  U_RX : entity work.async_ser_rx
283
  generic map(
284
    Reset_Level              => Reset_Level,
285
    Enable_Parity            => Enable_Parity,
286
    Parity_Odd_Even_n        => Parity_Odd_Even_n,
287
    Clock_Divider            => BAUD_RATE_DIV
288
  )
289
  port map(
290
    Clock                    => Clock,
291
    Reset                    => Reset,
292
    --
293
    Rx_In                    => RX_In,
294
    --
295
    Rx_Data                  => RX_FIFO_Wr_Data,
296
    Rx_Valid                 => RX_FIFO_Wr_En,
297 244 jshamlet
    Rx_PErr                  => Rx_PErr
298 207 jshamlet
  );
299
 
300 223 jshamlet
  RX_FIFO_Rd_En              <= Open8_Bus.Rd_En and
301
                                Addr_Match and
302 244 jshamlet
                                (not Reg_Sel_d);
303 207 jshamlet
 
304
  U_RX_FIFO : entity work.fifo_1k_core
305
  port map(
306
    aclr                     => FIFO_Reset,
307
    clock                    => Clock,
308
    data                     => RX_FIFO_Wr_Data,
309
    rdreq                    => RX_FIFO_Rd_En,
310
    wrreq                    => RX_FIFO_Wr_En,
311
    empty                    => RX_FIFO_Empty,
312
    almost_full              => RX_FIFO_AFull,
313
    q                        => RX_FIFO_Rd_Data
314
  );
315
 
316 213 jshamlet
end generate;
317
 
318 207 jshamlet
end architecture;

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