OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_btn_int.vhd] - Blame information for rev 179

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 173 jshamlet
-- Copyright (c)2013 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
22
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_btn_int
25
-- Description:  Detects and reports when a user pushbutton is pressed with an
26
--                interrupt. Software must clear the flag for additional
27
--                interrupts to avoid inundating the processor.
28
 
29
library ieee;
30
use ieee.std_logic_1164.all;
31
use ieee.std_logic_unsigned.all;
32
use ieee.std_logic_misc.all;
33
 
34
library work;
35
  use work.open8_pkg.all;
36
 
37
entity o8_btn_int is
38
generic(
39
  Button_Level          : std_logic;
40
  Address               : ADDRESS_TYPE;
41
  Reset_Level           : std_logic
42
);
43
port(
44
  Clock                 : in  std_logic;
45
  Reset                 : in  std_logic;
46
  uSec_Tick             : in  std_logic;
47
  --
48
  Bus_Address           : in  ADDRESS_TYPE;
49
  Rd_Enable             : in  std_logic;
50
  Rd_Data               : out DATA_TYPE;
51
  Interrupt             : out std_logic;
52
  --
53
  Button1_In            : in  std_logic;
54
  Button2_In            : in  std_logic
55
);
56
end entity;
57
 
58
architecture behave of o8_btn_int is
59
 
60
  constant User_Addr    : std_logic_vector(15 downto 0) := Address;
61
  alias  Comp_Addr      is Bus_Address(15 downto 0);
62
  signal Addr_Match     : std_logic;
63
  signal Rd_En          : std_logic;
64
 
65
  signal Button1_SR     : std_logic_vector(2 downto 0);
66
  alias  Button1_In_q   is Button1_SR(2);
67
 
68
  signal Button1_Dn_Tmr : std_logic_vector(7 downto 0);
69
  signal Button1_Dn     : std_logic;
70
 
71
  signal Button1_Up_Tmr : std_logic_vector(7 downto 0);
72
  signal Button1_Up     : std_logic;
73
 
74
  signal Button1_State  : std_logic;
75
  signal Button1_State_q: std_logic;
76
 
77
  signal Button1_Int    : std_logic;
78
 
79
  signal Button2_SR     : std_logic_vector(2 downto 0);
80
  alias  Button2_In_q   is Button2_SR(2);
81
 
82
  signal Button2_Dn_Tmr : std_logic_vector(7 downto 0);
83
  signal Button2_Dn     : std_logic;
84
 
85
  signal Button2_Up_Tmr : std_logic_vector(7 downto 0);
86
  signal Button2_Up     : std_logic;
87
 
88
  signal Button2_State  : std_logic;
89
  signal Button2_State_q: std_logic;
90
 
91
  signal Button2_Int    : std_logic;
92
 
93
begin
94
 
95
  Addr_Match            <= Rd_Enable when Comp_Addr = User_Addr else '0';
96
 
97
  io_reg: process( Clock, Reset )
98
  begin
99
    if( Reset = Reset_Level )then
100
      Rd_En             <= '0';
101
      Rd_Data           <= x"00";
102
    elsif( rising_edge( Clock ) )then
103
      Rd_En             <= Addr_Match;
104
      Rd_Data           <= (others => '0');
105
      if( Rd_En = '1' )then
106
        Rd_Data(6)      <= Button1_State;
107
        Rd_Data(7)      <= Button2_State;
108
      end if;
109
 
110
    end if;
111
  end process;
112
 
113
  Interrupt             <= Button1_Int or Button2_Int;
114
 
115
  Button1_trap: process( Clock, Reset )
116
  begin
117
    if( Reset = Reset_Level )then
118
      Button1_SR         <= (others => '0');
119
 
120
      Button1_Dn_Tmr     <= (others => '0');
121
      Button1_Dn         <= '0';
122
 
123
      Button1_Up_Tmr     <= (others => '0');
124
      Button1_Up         <= '0';
125
 
126
      Button1_State      <= '0';
127
      Button1_State_q    <= '0';
128
 
129
      Button1_Int        <= '0';
130
    elsif( rising_edge(Clock) )then
131
      Button1_SR        <= Button1_SR(1 downto 0) & Button1_In;
132
 
133
      Button1_Dn_Tmr    <= (others => '0');
134
      Button1_Dn        <= '0';
135
      if( Button1_In_q = Button_Level )then
136
        Button1_Dn_Tmr  <= Button1_Dn_Tmr + uSec_Tick;
137
        if( and_reduce(Button1_Dn_Tmr) = '1' )then
138
          Button1_Dn_Tmr<= Button1_Dn_Tmr;
139
          Button1_Dn    <= '1';
140
        end if;
141
      end if;
142
 
143
      Button1_Up_Tmr    <= (others => '0');
144
      Button1_Up        <= '0';
145
      if( Button1_In_q = not Button_Level )then
146
        Button1_Up_Tmr  <= Button1_Up_Tmr + uSec_Tick;
147
        if( and_reduce(Button1_Up_Tmr) = '1' )then
148
          Button1_Up_Tmr<= Button1_Up_Tmr;
149
          Button1_Up    <= '1';
150
        end if;
151
      end if;
152
 
153
      if( Button1_Dn = '1' )then
154
        Button1_State   <= '1';
155
      elsif( Button1_Up = '1' )then
156
        Button1_State   <= '0';
157
      end if;
158
 
159
      Button1_State_q   <= Button1_State;
160
      Button1_Int       <= Button1_State xor Button1_State_q;
161
 
162
    end if;
163
  end process;
164
 
165
  Button2_trap: process( Clock, Reset )
166
  begin
167
    if( Reset = Reset_Level )then
168
      Button2_SR         <= (others => '0');
169
 
170
      Button2_Dn_Tmr     <= (others => '0');
171
      Button2_Dn         <= '0';
172
 
173
      Button2_Up_Tmr     <= (others => '0');
174
      Button2_Up         <= '0';
175
 
176
      Button2_State      <= '0';
177
      Button2_State_q    <= '0';
178
 
179
      Button2_Int        <= '0';
180
    elsif( rising_edge(Clock) )then
181
      Button2_SR        <= Button2_SR(1 downto 0) & Button2_In;
182
 
183
      Button2_Dn_Tmr    <= (others => '0');
184
      Button2_Dn        <= '0';
185
      if( Button2_In_q = Button_Level )then
186
        Button2_Dn_Tmr  <= Button2_Dn_Tmr + uSec_Tick;
187
        if( and_reduce(Button2_Dn_Tmr) = '1' )then
188
          Button2_Dn_Tmr<= Button2_Dn_Tmr;
189
          Button2_Dn    <= '1';
190
        end if;
191
      end if;
192
 
193
      Button2_Up_Tmr    <= (others => '0');
194
      Button2_Up        <= '0';
195
      if( Button2_In_q = not Button_Level )then
196
        Button2_Up_Tmr  <= Button2_Up_Tmr + uSec_Tick;
197
        if( and_reduce(Button2_Up_Tmr) = '1' )then
198
          Button2_Up_Tmr<= Button2_Up_Tmr;
199
          Button2_Up    <= '1';
200
        end if;
201
      end if;
202
 
203
      if( Button2_Dn = '1' )then
204
        Button2_State   <= '1';
205
      elsif( Button2_Up = '1' )then
206
        Button2_State   <= '0';
207
      end if;
208
 
209
      Button2_State_q   <= Button2_State;
210
      Button2_Int       <= Button2_State xor Button2_State_q;
211
 
212
    end if;
213
  end process;
214
 
215
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.