OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_clk_detect.vhd] - Blame information for rev 174

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 173 jshamlet
-- Copyright (c)2013 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
22
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_clk_detect
25
-- Description:  Provides up/down status and interrupt for monitoring a clock
26
--
27
-- Register Map:
28
-- Offset  Bitfield Description                          Read/Write
29
--   0x00   BB-----A VSD Engine PLL Reset                (RO/RW)
30
--                    A = Interrupt Enable (1 = enabled, 0 = masked) (RW)
31
--                    B = Clock Line State (follows input, only valid if B = 1) (RO)
32
--                    C = Clock Detect (1 = transition detected) (RO)
33
 
34
library ieee;
35
use ieee.std_logic_1164.all;
36
use ieee.std_logic_unsigned.all;
37
use ieee.std_logic_arith.all;
38
use ieee.std_logic_misc.all;
39
 
40
library work;
41
  use work.open8_pkg.all;
42
 
43
entity o8_clk_detect is
44
generic(
45
  Threshold_Count       : integer;
46
  Address               : ADDRESS_TYPE;
47
  Reset_Level           : std_logic
48
);
49
port(
50
  Clock                 : in  std_logic;
51
  Reset                 : in  std_logic;
52
  --
53
  Ref_Clk_In            : in  std_logic;
54
  --
55
  Bus_Address           : in  ADDRESS_TYPE;
56
  Wr_Enable             : in  std_logic;
57
  Wr_Data               : in  DATA_TYPE;
58
  Rd_Enable             : in  std_logic;
59
  Rd_Data               : out DATA_TYPE;
60
  Interrupt             : out std_logic
61
);
62
end entity;
63
 
64
architecture behave of o8_clk_detect is
65
 
66
  constant User_Addr    : std_logic_vector(15 downto 0) := Address;
67
  alias  Comp_Addr      is Bus_Address(15 downto 0);
68
  signal Addr_Match     : std_logic;
69
 
70
  signal Wr_Data_Q      : DATA_TYPE;
71
  signal Wr_En          : std_logic;
72
  signal Rd_En          : std_logic;
73
 
74
  signal Int_En         : std_logic;
75
 
76
  function ceil_log2 (x : in natural) return natural is
77
    variable retval          : natural;
78
  begin
79
    retval                   := 1;
80
    while ((2**retval) - 1) < x loop
81
      retval                 := retval + 1;
82
    end loop;
83
    return retval;
84
  end function;
85
 
86
  constant Threshold_bits    : integer := ceil_log2(Threshold_Count);
87
  constant THRESHOLD         : std_logic_vector(Threshold_bits - 1 downto 0) :=
88
                        conv_std_logic_vector(Threshold_Count,Threshold_bits);
89
 
90
  signal RE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0);
91
  signal FE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0);
92
 
93
  signal Ref_In_SR           : std_logic_vector(3 downto 0);
94
  alias  Ref_In_q1           is Ref_In_SR(2);
95
  alias  Ref_In_q2           is Ref_In_SR(3);
96
  signal Ref_In_RE           : std_logic;
97
  signal Ref_In_FE           : std_logic;
98
 
99
  signal Ref_Detect          : std_logic;
100
  signal Ref_Detect_q1       : std_logic;
101
  signal Ref_Detect_CoS      : std_logic;
102
 
103
begin
104
 
105
  Addr_Match            <= '1' when Comp_Addr = User_Addr else '0';
106
 
107
  io_reg: process( Clock, Reset )
108
  begin
109
    if( Reset = Reset_Level )then
110
      Wr_Data_Q         <= x"00";
111
      Wr_En             <= '0';
112
      Rd_En             <= '0';
113
      Rd_Data           <= x"00";
114
      Int_En            <= '0';
115
    elsif( rising_edge( Clock ) )then
116
      Wr_Data_Q         <= Wr_Data;
117
      Wr_En             <= Wr_Enable and Addr_Match;
118
      Rd_En             <= Rd_Enable and Addr_Match;
119
 
120
    if( Wr_En = '1' )then
121
      Int_En          <= Wr_Data_Q(0);
122
    end if;
123
 
124
      Rd_Data           <= (others => '0');
125
      if( Rd_En = '1' )then
126
        Rd_Data(0)      <= Int_En;
127
        Rd_Data(6)      <= Ref_In_q2;
128
        Rd_Data(7)      <= Ref_Detect;
129
      end if;
130
 
131
    end if;
132
  end process;
133
 
134
  Detect_proc: process( Clock, Reset )
135
  begin
136
    if( Reset = Reset_Level )then
137
      Ref_In_SR              <= (others => '0');
138
      Ref_In_RE              <= '0';
139
      Ref_In_FE              <= '0';
140
      RE_Threshold_Ctr       <= (others => '0');
141
      FE_Threshold_Ctr       <= (others => '0');
142
      Ref_Detect             <= '0';
143
      Interrupt              <= '0';
144
    elsif( rising_edge(Clock) )then
145
      Ref_In_SR              <= Ref_In_SR(2 downto 0) & Ref_Clk_In;
146
      Ref_In_RE              <= Ref_In_q1 and (not Ref_In_q2);
147
      Ref_In_FE              <= (not Ref_In_q1) and Ref_In_q2;
148
 
149
      RE_Threshold_Ctr       <= RE_Threshold_Ctr - 1;
150
      if( Ref_In_RE = '1' )then
151
        RE_Threshold_Ctr     <= THRESHOLD;
152
      elsif( or_reduce(RE_Threshold_Ctr) = '0' )then
153
        RE_Threshold_Ctr     <= (others => '0');
154
      end if;
155
 
156
      FE_Threshold_Ctr       <= FE_Threshold_Ctr - 1;
157
      if( Ref_In_FE = '1' )then
158
        FE_Threshold_Ctr     <= THRESHOLD;
159
      elsif( or_reduce(FE_Threshold_Ctr) = '0' )then
160
        FE_Threshold_Ctr     <= (others => '0');
161
      end if;
162
 
163
 
164
      Ref_Detect             <= or_reduce(RE_Threshold_Ctr) and
165
                                or_reduce(FE_Threshold_Ctr);
166
      Ref_Detect_q1          <= Ref_Detect;
167
      Ref_Detect_CoS         <= Ref_Detect xor Ref_Detect_q1;
168
 
169
      Interrupt              <= Ref_Detect_CoS and Int_En;
170
    end if;
171
  end process;
172
 
173
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.