OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_clk_detect.vhd] - Blame information for rev 253

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 194 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
2 173 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 173 jshamlet
--
24
-- VHDL Units :  o8_clk_detect
25
-- Description:  Provides up/down status and interrupt for monitoring a clock
26
--
27
-- Register Map:
28
-- Offset  Bitfield Description                          Read/Write
29 197 jshamlet
--  0x00   BA------ Recieve Clock Status                   (RO)
30
--                    A = Clock Line State (follows input)
31
--                    B = Clock Detect (1 = transition detected)
32 224 jshamlet
--
33
-- Revision History
34
-- Author          Date     Change
35
------------------ -------- ---------------------------------------------------
36
-- Seth Henry      04/16/20 Revision block added
37 173 jshamlet
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.std_logic_unsigned.all;
41
use ieee.std_logic_arith.all;
42
use ieee.std_logic_misc.all;
43
 
44
library work;
45
  use work.open8_pkg.all;
46
 
47
entity o8_clk_detect is
48
generic(
49 191 jshamlet
  Threshold_Count            : integer;
50 224 jshamlet
  Address                    : ADDRESS_TYPE
51 173 jshamlet
);
52
port(
53 191 jshamlet
  Ref_Clk_In                 : in  std_logic;
54 173 jshamlet
  --
55 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
56 191 jshamlet
  Rd_Data                    : out DATA_TYPE;
57
  Interrupt                  : out std_logic
58 173 jshamlet
);
59
end entity;
60
 
61
architecture behave of o8_clk_detect is
62
 
63 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
64
  alias Reset                is Open8_Bus.Reset;
65
 
66 191 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
67 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
68 191 jshamlet
  signal Addr_Match          : std_logic := '0';
69 173 jshamlet
 
70 244 jshamlet
  signal Rd_En_d             : std_logic := '0';
71
  signal Rd_En_q             : std_logic := '0';
72 173 jshamlet
 
73
  constant Threshold_bits    : integer := ceil_log2(Threshold_Count);
74
  constant THRESHOLD         : std_logic_vector(Threshold_bits - 1 downto 0) :=
75
                        conv_std_logic_vector(Threshold_Count,Threshold_bits);
76
 
77 191 jshamlet
  signal RE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0) :=
78
                                (others => '0');
79
  signal FE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0) :=
80
                                (others => '0');
81 173 jshamlet
 
82 191 jshamlet
  signal Ref_In_SR           : std_logic_vector(3 downto 0) := (others => '0');
83 173 jshamlet
  alias  Ref_In_q1           is Ref_In_SR(2);
84
  alias  Ref_In_q2           is Ref_In_SR(3);
85 191 jshamlet
  signal Ref_In_RE           : std_logic := '0';
86
  signal Ref_In_FE           : std_logic := '0';
87 173 jshamlet
 
88 191 jshamlet
  signal Ref_Detect          : std_logic := '0';
89
  signal Ref_Detect_q1       : std_logic := '0';
90
  signal Ref_Detect_CoS      : std_logic := '0';
91 173 jshamlet
 
92
begin
93
 
94 244 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
95
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
96 173 jshamlet
 
97
  io_reg: process( Clock, Reset )
98
  begin
99
    if( Reset = Reset_Level )then
100 244 jshamlet
      Rd_En_q                <= '0';
101 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
102 173 jshamlet
    elsif( rising_edge( Clock ) )then
103 244 jshamlet
      Rd_En_q                <= Rd_En_d;
104 173 jshamlet
 
105 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
106 244 jshamlet
      if( Rd_En_q = '1' )then
107 217 jshamlet
        Rd_Data(6)           <= Ref_In_q2;
108
        Rd_Data(7)           <= Ref_Detect;
109 173 jshamlet
      end if;
110
 
111
    end if;
112
  end process;
113
 
114
  Detect_proc: process( Clock, Reset )
115
  begin
116
    if( Reset = Reset_Level )then
117
      Ref_In_SR              <= (others => '0');
118
      Ref_In_RE              <= '0';
119
      Ref_In_FE              <= '0';
120
      RE_Threshold_Ctr       <= (others => '0');
121
      FE_Threshold_Ctr       <= (others => '0');
122
      Ref_Detect             <= '0';
123
      Interrupt              <= '0';
124
    elsif( rising_edge(Clock) )then
125
      Ref_In_SR              <= Ref_In_SR(2 downto 0) & Ref_Clk_In;
126
      Ref_In_RE              <= Ref_In_q1 and (not Ref_In_q2);
127
      Ref_In_FE              <= (not Ref_In_q1) and Ref_In_q2;
128
 
129
      RE_Threshold_Ctr       <= RE_Threshold_Ctr - 1;
130
      if( Ref_In_RE = '1' )then
131
        RE_Threshold_Ctr     <= THRESHOLD;
132
      elsif( or_reduce(RE_Threshold_Ctr) = '0' )then
133
        RE_Threshold_Ctr     <= (others => '0');
134
      end if;
135
 
136
      FE_Threshold_Ctr       <= FE_Threshold_Ctr - 1;
137
      if( Ref_In_FE = '1' )then
138
        FE_Threshold_Ctr     <= THRESHOLD;
139
      elsif( or_reduce(FE_Threshold_Ctr) = '0' )then
140
        FE_Threshold_Ctr     <= (others => '0');
141
      end if;
142
 
143
 
144
      Ref_Detect             <= or_reduce(RE_Threshold_Ctr) and
145
                                or_reduce(FE_Threshold_Ctr);
146
      Ref_Detect_q1          <= Ref_Detect;
147
      Ref_Detect_CoS         <= Ref_Detect xor Ref_Detect_q1;
148
 
149 191 jshamlet
      Interrupt              <= Ref_Detect_CoS;
150 173 jshamlet
    end if;
151
  end process;
152
 
153
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.