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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_clk_detect.vhd] - Blame information for rev 333

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Line No. Rev Author Line
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-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_clk_detect
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-- Description:  Provides up/down status and interrupt for monitoring a clock
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--
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-- Register Map:
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-- Offset  Bitfield Description                          Read/Write
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--  0x00   BA------ Recieve Clock Status                   (RO)
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--                    A = Clock Line State (follows input)
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--                    B = Clock Detect (1 = transition detected)
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/16/20 Revision block added
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_clk_detect is
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generic(
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  Threshold_Count            : integer;
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Ref_Clk_In                 : in  std_logic;
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  --
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  Rd_Data                    : out DATA_TYPE;
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  Interrupt                  : out std_logic
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);
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end entity;
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architecture behave of o8_clk_detect is
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  alias Clock                is Open8_Bus.Clock;
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  alias Reset                is Open8_Bus.Reset;
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  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
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  signal Addr_Match          : std_logic := '0';
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  signal Rd_En_d             : std_logic := '0';
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  signal Rd_En_q             : std_logic := '0';
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  constant Threshold_bits    : integer := ceil_log2(Threshold_Count);
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  constant THRESHOLD         : std_logic_vector(Threshold_bits - 1 downto 0) :=
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                        conv_std_logic_vector(Threshold_Count,Threshold_bits);
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  signal RE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0) :=
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                                (others => '0');
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  signal FE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0) :=
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                                (others => '0');
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  signal Ref_In_SR           : std_logic_vector(3 downto 0) := (others => '0');
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  alias  Ref_In_q1           is Ref_In_SR(2);
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  alias  Ref_In_q2           is Ref_In_SR(3);
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  signal Ref_In_RE           : std_logic := '0';
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  signal Ref_In_FE           : std_logic := '0';
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  signal Ref_Detect          : std_logic := '0';
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  signal Ref_Detect_q1       : std_logic := '0';
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  signal Ref_Detect_CoS      : std_logic := '0';
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Rd_En_q                <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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    elsif( rising_edge( Clock ) )then
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      Rd_En_q                <= Rd_En_d;
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      Rd_Data                <= OPEN8_NULLBUS;
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      if( Rd_En_q = '1' )then
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        Rd_Data(6)           <= Ref_In_q2;
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        Rd_Data(7)           <= Ref_Detect;
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      end if;
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    end if;
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  end process;
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  Detect_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Ref_In_SR              <= (others => '0');
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      Ref_In_RE              <= '0';
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      Ref_In_FE              <= '0';
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      RE_Threshold_Ctr       <= (others => '0');
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      FE_Threshold_Ctr       <= (others => '0');
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      Ref_Detect             <= '0';
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      Interrupt              <= '0';
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    elsif( rising_edge(Clock) )then
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      Ref_In_SR              <= Ref_In_SR(2 downto 0) & Ref_Clk_In;
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      Ref_In_RE              <= Ref_In_q1 and (not Ref_In_q2);
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      Ref_In_FE              <= (not Ref_In_q1) and Ref_In_q2;
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      RE_Threshold_Ctr       <= RE_Threshold_Ctr - 1;
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      if( Ref_In_RE = '1' )then
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        RE_Threshold_Ctr     <= THRESHOLD;
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      elsif( or_reduce(RE_Threshold_Ctr) = '0' )then
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        RE_Threshold_Ctr     <= (others => '0');
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      end if;
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      FE_Threshold_Ctr       <= FE_Threshold_Ctr - 1;
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      if( Ref_In_FE = '1' )then
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        FE_Threshold_Ctr     <= THRESHOLD;
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      elsif( or_reduce(FE_Threshold_Ctr) = '0' )then
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        FE_Threshold_Ctr     <= (others => '0');
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      end if;
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      Ref_Detect             <= or_reduce(RE_Threshold_Ctr) and
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                                or_reduce(FE_Threshold_Ctr);
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      Ref_Detect_q1          <= Ref_Detect;
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      Ref_Detect_CoS         <= Ref_Detect xor Ref_Detect_q1;
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      Interrupt              <= Ref_Detect_CoS;
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    end if;
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  end process;
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end architecture;

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