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-- Copyright (c)2006,2011,2012,2013,2015 Jeremy Seth Henry

-- All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution,

--       where applicable (as part of a user interface, debugging port, etc.)

--

-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

--

-- VHDL Units :  Open8_CPU

-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the

--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd

--            :

-- Notes      :  Generic definitions

--            :

--            :  Program_Start_Addr sets the initial value of the program

--            :   counter.

--            :

--            :  ISR_Start_Addr sets the location of the interrupt service

--            :   vector table. There are 8 service vectors, or 16 bytes, which

--            :   must be allocated to either ROM or RAM.

--            :

--            :  Stack_Start_Address sets the initial (reset) value of the

--            :   stack pointer. Also used for the RSP instruction if

--            :   Allow_Stack_Address_Move is false.

--            :

--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be

--            :   programmed via thet RSP instruction. If enabled, the contents

--            :   of R1:R0 are used to initialize the stack pointer.

--            :

--            :  The Enable_Auto_Increment generic can be used to modify the

--            :   indexed instructions such that specifying an odd register

--            :   will use the next lower register pair, post-incrementing the

--            :   value in that pair. IOW, specifying STX R1 will instead

--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1

--            :

--            :  BRK_Implements_WAI modifies the BRK instruction such that it

--            :   triggers the wait for interrupt state, but without triggering

--            :   a soft interrupt in lieu of its normal behavior, which is to

--            :   insert several dead clock cycles - essentially a long NOP

--            :

--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a

--            :   non-maskable interrupt at the highest priority. To remain

--            :   true to the original core, this should be set false.

--            :

--            :  Default_Interrupt_Mask sets the intial/reset value of the

--            :   interrupt mask. To remain true to the original core, which

--            :   had no interrupt mask, this should be set to x"FF". Otherwise

--            :   it can be initialized to any value. Note that Enable_NMI

--            :   will logically force the LSB high.

--            : 

--            :  Reset_Level determines whether the processor registers reset

--            :   on a high or low level from higher logic.

--            :

--            : Architecture notes

--            :  This model deviates from the original ISA in a few important

--            :   ways.

--            :

--            :  First, there is only one set of registers. Interrupt service

--            :   routines must explicitely preserve context since the the

--            :   hardware doesn't. This was done to decrease size and code

--            :   complexity. Older code that assumes this behavior will not

--            :   execute correctly on this processor model.

--            :

--            :  Second, this model adds an additional pipeline stage between

--            :   the instruction decoder and the ALU. Unfortunately, this

--            :   means that the instruction stream has to be restarted after

--            :   any math instruction is executed, implying that any ALU

--            :   instruction now has a latency of 2 instead of 0. The

--            :   advantage is that the maximum frequency has gone up

--            :   significantly, as the ALU code is vastly more efficient.

--            :   As an aside, this now means that all math instructions,

--            :   including MUL (see below) and UPP have the same instruction

--            :   latency.

--            :

--            :  Third, the original ISA, also a soft core, had two reserved

--            :   instructions, USR and USR2. These have been implemented as

--            :   DBNZ, and MUL respectively.

--            :

--            :  DBNZ decrements the specified register and branches if the

--            :   result is non-zero. The instruction effectively executes a

--            :   DEC Rn instruction prior to branching, so the same flags will

--            :   be set.

--            :

--            :  MUL places the result of R0 * Rn into R1:R0. Instruction

--            :   latency is identical to other ALU instructions. Only the Z

--            :   flag is set, since there is no defined overflow or "negative

--            :   16-bit values"

--            :

--            :  Fourth, indexed load/store instructions now have an (optional)

--            :   ability to post-increment their index registers. If enabled,

--            :   using an odd operand for LDO,LDX, STO, STX will cause the

--            :   register pair to be incremented after the storage access.

--            :

--            :  Fifth, the RSP instruction has been (optionally) altered to

--            :   allow the stack pointer to be sourced from R1:R0.

--            :

--            :  Sixth, the BRK instruction can optionally implement a WAI,

--            :   which is the same as the INT instruction without the soft

--            :   interrupt, as a way to put the processor to "sleep" until the

--            :   next external interrupt.

--            :

--            :  Seventh, the original CPU model had 8 non-maskable interrupts

--            :   with priority. This model has the same 8 interrupts, but

--            :   allows software to mask them (with an additional option to 

--            :   override the highest priority interrupt, making it the NMI.)

--            :

--            :  Lastly, previous unmapped instructions in the OP_STK opcode

--            :   were repurposed to support a new interrupt mask.

--            :   SMSK and GMSK transfer the contents of R0 (accumulator)

--            :   to/from the interrupt mask register. SMSK is immediate, while

--            :   GMSK has the same overhead as a math instruction.

--

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      07/19/06 Design Start

-- Seth Henry      01/18/11 Fixed BTT instruction to match V8

-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data

--                           corruption issues.

-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data

--                           path sections.

-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into

--                           single entity.

-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the

--                           processor to wait for an interrupt instead of the

--                           normal BRK behavior.

-- Seth Henry      12/20/11 Modified core to allow WAIT_FOR_INT state to idle

--                           the bus entirely (Rd_Enable is low)

-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,

--                           faster logic that simply does priority encoding.

-- Seth Henry      08/06/13 Removed HALT functionality

-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs

library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

  use ieee.std_logic_misc.all;

library work;

use work.Open8_pkg.all;

entity Open8_CPU is

  generic(

    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location

    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's

    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack

    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP

    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr

    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int

    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled

    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints

    Reset_Level              : std_logic    := '0' );   -- Active reset level

  port(

    Clock                    : in  std_logic;

    Reset                    : in  std_logic;

    Interrupts               : in  INTERRUPT_BUNDLE;

    --

    Address                  : out ADDRESS_TYPE;

    Rd_Data                  : in  DATA_TYPE;

    Rd_Enable                : out std_logic;

    Wr_Data                  : out DATA_TYPE;

    Wr_Enable                : out std_logic );

end entity;

architecture behave of Open8_CPU is

  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;

  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;

  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;

  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;

  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;

  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;

  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;

  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;

  signal Halt                : std_logic;

  signal CPU_Next_State      : CPU_STATES := PIPE_FILL_0;

  signal CPU_State           : CPU_STATES := PIPE_FILL_0;

  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;

  signal Opcode              : OPCODE_TYPE := (others => '0');

  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');

  signal Prefetch            : DATA_TYPE   := x"00";

  signal Operand1, Operand2  : DATA_TYPE   := x"00";

  signal Instr_Prefetch      : std_logic   := '0';

  signal PC_Ctrl             : PC_CTRL_TYPE;

  signal Program_Ctr         : ADDRESS_TYPE := x"0000";

  signal SP_Ctrl             : SP_CTRL_TYPE;

  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";

  signal DP_Ctrl             : DATA_CTRL_TYPE;

  signal INT_Ctrl            : INT_CTRL_TYPE;

  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';

  signal Int_Req, Int_Ack    : std_logic   := '0';

  signal Int_Mask            : DATA_TYPE   := x"00";

  signal ISR_Addr            : ADDRESS_TYPE := x"0000";

  signal i_Ints              : INTERRUPT_BUNDLE := x"00";

  signal Pending             : INTERRUPT_BUNDLE := x"00";

  signal Wait_for_FSM        : std_logic := '0';

  signal ALU_Ctrl            : ALU_CTRL_TYPE;

  signal Regfile             : REGFILE_TYPE;

  signal Flags               : FLAG_TYPE;

  signal Mult                : ADDRESS_TYPE := x"0000";

begin

-------------------------------------------------------------------------------

-- State Logic / Instruction Decoding & Execution

-- Combinatorial portion of CPU finite state machine

-------------------------------------------------------------------------------

  State_Logic: process(CPU_State, Regfile, Flags, Int_Mask, Opcode,

                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req,

                       Program_Ctr, Stack_Ptr, ISR_Addr )

    variable Reg, Reg_1      : integer range 0 to 7 := 0;

    variable Offset_SX       : ADDRESS_TYPE;

  begin

    CPU_Next_State           <= CPU_State;

    Cache_Ctrl               <= CACHE_IDLE;

    --

    ALU_Ctrl.Oper            <= ALU_IDLE;

    ALU_Ctrl.Reg             <= ACCUM;

    ALU_Ctrl.Data            <= x"00";

    --

    PC_Ctrl.Oper             <= PC_IDLE;

    PC_Ctrl.Offset           <= x"03";

    PC_Ctrl.Addr             <= x"0000";

    --

    SP_Ctrl.Oper             <= SP_IDLE;

    --

    Address                  <= Program_Ctr;

    --

    DP_Ctrl.Src              <= DATA_RD_MEM;

    DP_Ctrl.Reg              <= ACCUM;

    --

    INT_Ctrl.Mask_Set        <= '0';

    INT_Ctrl.Soft_Ints       <= x"00";

    INT_Ctrl.Incr_ISR        <= '0';

    Ack_D                    <= '0';

    -- Assign the most common value of Reg and Reg1 outside the case structure

    --  to simplify things.

    Reg                      := conv_integer(SubOp);

    Reg_1                    := conv_integer(SubOp_p1);

    Offset_SX(15 downto 0)   := (others => Operand1(7));

    Offset_SX(7 downto 0)    := Operand1;

    case CPU_State is

-------------------------------------------------------------------------------

-- Initial Instruction fetch & decode

-------------------------------------------------------------------------------

      when PIPE_FILL_0 =>

        CPU_Next_State       <= PIPE_FILL_1;

        PC_Ctrl.Oper         <= PC_INCR;

      when PIPE_FILL_1 =>

        CPU_Next_State       <= PIPE_FILL_2;

        PC_Ctrl.Oper         <= PC_INCR;

      when PIPE_FILL_2 =>

        CPU_Next_State       <= INSTR_DECODE;

        Cache_Ctrl           <= CACHE_INSTR;

        PC_Ctrl.Oper         <= PC_INCR;

      when INSTR_DECODE =>

        CPU_Next_State       <= INSTR_DECODE;

        Cache_Ctrl           <= CACHE_INSTR;

        case Opcode is

          when OP_PSH =>

            CPU_Next_State   <= PSH_C1;

            Cache_Ctrl       <= CACHE_PREFETCH;

            PC_Ctrl.Oper     <= PC_REV1;

            DP_Ctrl.Src      <= DATA_WR_REG;

            DP_Ctrl.Reg      <= SubOp;

          when OP_POP =>

            CPU_Next_State   <= POP_C1;

            Cache_Ctrl       <= CACHE_PREFETCH;

            PC_Ctrl.Oper     <= PC_REV2;

            SP_Ctrl.Oper     <= SP_POP;

          when OP_BR0 | OP_BR1 =>

            CPU_Next_State   <= BRN_C1;

            Cache_Ctrl       <= CACHE_OPER1;

            PC_Ctrl.Oper     <= PC_INCR;

          when OP_DBNZ =>

            CPU_Next_State   <= DBNZ_C1;

            Cache_Ctrl       <= CACHE_OPER1;

            PC_Ctrl.Oper     <= PC_INCR;

            ALU_Ctrl.Oper    <= ALU_DEC;

            ALU_Ctrl.Reg     <= SubOp;

          when OP_INT =>

            PC_Ctrl.Oper     <= PC_INCR;

            -- Make sure the requested interrupt is actually enabled first

            if( Int_Mask(Reg) = '1' )then

              CPU_Next_State <= WAIT_FOR_INT;

              INT_Ctrl.Soft_Ints(Reg) <= '1';

            end if;

          when OP_STK =>

            case SubOp is

              when SOP_RSP  =>

                PC_Ctrl.Oper <= PC_INCR;

                SP_Ctrl.Oper <= SP_RSET;

              when SOP_RTS | SOP_RTI =>

                CPU_Next_State <= RTS_C1;

                Cache_Ctrl   <= CACHE_IDLE;

                SP_Ctrl.Oper <= SP_POP;

              when SOP_BRK  =>

                CPU_Next_State   <= BRK_C1;

                PC_Ctrl.Oper     <= PC_REV2;

                -- If Break implements Wait for Interrupt, replace the normal

                --  flow with a modified version of the INT instruction

                if( BRK_Implements_WAI )then

                  CPU_Next_State <= WAIT_FOR_INT;

                  PC_Ctrl.Oper   <= PC_INCR;

                end if;

              when SOP_JMP  =>

                CPU_Next_State <= JMP_C1;

                Cache_Ctrl   <= CACHE_OPER1;

              when SOP_SMSK =>

                PC_Ctrl.Oper <= PC_INCR;

                INT_Ctrl.Mask_Set <= '1';

              when SOP_GMSK =>

                PC_Ctrl.Oper <= PC_INCR;

                ALU_Ctrl.Oper<= ALU_LDI;

                ALU_Ctrl.Reg <= ACCUM;

                ALU_Ctrl.Data<= Int_Mask;

              when SOP_JSR =>

                CPU_Next_State <= JSR_C1;

                Cache_Ctrl   <= CACHE_OPER1;

                DP_Ctrl.Src  <= DATA_WR_PC;

                DP_Ctrl.Reg  <= ACCUM+1;

              when others => null;

            end case;

          when OP_MUL =>

            CPU_Next_State   <= MUL_C1;

            -- We need to back the PC up by 1, and allow it to refill. An

            --  unfortunate consequence of the pipelining. We can get away with

            --  only 1 extra clock by pre-fetching the next instruction, though

            Cache_Ctrl       <= CACHE_PREFETCH;

            PC_Ctrl.Oper     <= PC_REV1;

            -- Multiplication is automatic, but requires a single clock cycle.

            --  We need to specify the register for Rn (R1:R0 = R0 * Rn) now,

            --   but will issue the multiply command on the next clock to copy

            --   the results to the specified register.

            ALU_Ctrl.Oper    <= ALU_IDLE;

            ALU_Ctrl.Reg     <= SubOp;

          when OP_UPP =>

            CPU_Next_State   <= UPP_C1;

            Cache_Ctrl       <= CACHE_PREFETCH;

            PC_Ctrl.Oper     <= PC_REV1;

            ALU_Ctrl.Oper    <= Opcode;

            ALU_Ctrl.Reg     <= SubOp;

          when OP_LDA =>

            CPU_Next_State   <= LDA_C1;

            Cache_Ctrl       <= CACHE_OPER1;

          when OP_LDI =>

            CPU_Next_State   <= LDI_C1;

            Cache_Ctrl       <= CACHE_OPER1;

            PC_Ctrl.Oper     <= PC_INCR;

          when OP_LDO =>

            CPU_Next_State   <= LDO_C1;

            Cache_Ctrl       <= CACHE_OPER1;

            PC_Ctrl.Oper     <= PC_REV2;

          when OP_LDX =>

            CPU_Next_State   <= LDX_C1;

            PC_Ctrl.Oper     <= PC_REV2;

            -- If auto-increment is disabled, use the specified register pair,

            --  otherwise, for an odd:even pair, and issue the first half of

            --  a UPP instruction to the ALU

            if( not Enable_Auto_Increment )then

              Address        <= Regfile(Reg_1) & Regfile(Reg);

            else

              Reg            := conv_integer(SubOp(2 downto 1) & '0');

              Reg_1          := conv_integer(SubOp(2 downto 1) & '1');

              Address        <= Regfile(Reg_1) & Regfile(Reg);

              if( SubOp(0) = '1' )then

                ALU_Ctrl.Oper<= ALU_UPP;

                ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';

              end if;

            end if;

          when OP_STA =>

            CPU_Next_State   <= STA_C1;

            Cache_Ctrl       <= CACHE_OPER1;

          when OP_STO =>

            CPU_Next_State   <= STO_C1;

            Cache_Ctrl       <= CACHE_OPER1;

            PC_Ctrl.Oper     <= PC_REV2;

            DP_Ctrl.Src      <= DATA_WR_REG;

            DP_Ctrl.Reg      <= ACCUM;

          when OP_STX =>

            CPU_Next_State   <= STX_C1;

            Cache_Ctrl       <= CACHE_PREFETCH;

            PC_Ctrl.Oper     <= PC_REV2;

            DP_Ctrl.Src      <= DATA_WR_REG;

            DP_Ctrl.Reg      <= ACCUM;

          when others =>

            PC_Ctrl.Oper     <= PC_INCR;

            ALU_Ctrl.Oper    <= Opcode;

            ALU_Ctrl.Reg     <= SubOp;

        end case;

-------------------------------------------------------------------------------

-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )

-------------------------------------------------------------------------------

      when BRN_C1 =>

        CPU_Next_State       <= INSTR_DECODE;

        Cache_Ctrl           <= CACHE_INSTR;

        PC_Ctrl.Oper         <= PC_INCR;

        if( Flags(Reg) = Opcode(0) )then

          CPU_Next_State     <= PIPE_FILL_0;

          Cache_Ctrl         <= CACHE_IDLE;

          PC_Ctrl.Offset     <= Operand1;

        end if;

      when DBNZ_C1 =>

        CPU_Next_State       <= INSTR_DECODE;

        Cache_Ctrl           <= CACHE_INSTR;

        PC_Ctrl.Oper         <= PC_INCR;

        if( Flags(FL_ZERO) = '0' )then

          CPU_Next_State     <= PIPE_FILL_0;

          Cache_Ctrl         <= CACHE_IDLE;

          PC_Ctrl.Offset     <= Operand1;

        end if;

      when JMP_C1 =>

        CPU_Next_State       <= JMP_C2;

        Cache_Ctrl           <= CACHE_OPER2;

      when JMP_C2 =>

        CPU_Next_State       <= PIPE_FILL_0;

        PC_Ctrl.Oper         <= PC_LOAD;

        PC_Ctrl.Addr         <= Operand2 & Operand1;

-------------------------------------------------------------------------------

-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)

-------------------------------------------------------------------------------

      when LDA_C1 =>

        CPU_Next_State       <= LDA_C2;

        Cache_Ctrl           <= CACHE_OPER2;

      when LDA_C2 =>

        CPU_Next_State       <= LDA_C3;

        Address              <= Operand2 & Operand1;

      when LDA_C3 =>

        CPU_Next_State       <= LDA_C4;

        PC_Ctrl.Oper         <= PC_INCR;

      when LDA_C4 =>

        CPU_Next_State       <= LDI_C1;

        Cache_Ctrl           <= CACHE_OPER1;

        PC_Ctrl.Oper         <= PC_INCR;

      when LDI_C1 =>

        CPU_Next_State       <= INSTR_DECODE;

        Cache_Ctrl           <= CACHE_INSTR;

        PC_Ctrl.Oper         <= PC_INCR;

        ALU_Ctrl.Oper        <= ALU_LDI;

        ALU_Ctrl.Reg         <= SubOp;

        ALU_Ctrl.Data        <= Operand1;

      when LDO_C1 =>

        CPU_Next_State       <= LDX_C1;

        PC_Ctrl.Oper         <= PC_INCR;

        if( Enable_Auto_Increment )then

          Reg                := conv_integer(SubOp(2 downto 1) & '0');

          Reg_1              := conv_integer(SubOp(2 downto 1) & '1');

          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;

          if( SubOp(0) = '1' )then

            ALU_Ctrl.Oper<= ALU_UPP;

            ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';

          end if;

        else

          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;

        end if;

      when LDX_C1 =>

        CPU_Next_State       <= LDX_C2;

        PC_Ctrl.Oper         <= PC_INCR;

      when LDX_C2 =>

        CPU_Next_State       <= LDX_C3;

        PC_Ctrl.Oper         <= PC_INCR;

        Cache_Ctrl           <= CACHE_OPER1;

      when LDX_C3 =>

        CPU_Next_State       <= INSTR_DECODE;

        Cache_Ctrl           <= CACHE_INSTR;

        PC_Ctrl.Oper         <= PC_INCR;

        ALU_Ctrl.Oper        <= ALU_LDX;

        ALU_Ctrl.Reg         <= ACCUM;

        ALU_Ctrl.Data        <= Operand1;

-------------------------------------------------------------------------------

-- Data Storage - Store to memory (STA, STO, STX)

-------------------------------------------------------------------------------

      when STA_C1 =>

        CPU_Next_State       <= STA_C2;

        Cache_Ctrl           <= CACHE_OPER2;

        DP_Ctrl.Src          <= DATA_WR_REG;

        DP_Ctrl.Reg          <= SubOp;

      when STA_C2 =>

        CPU_Next_State       <= STA_C3;

        Address              <= Operand2 & Operand1;

        PC_Ctrl.Oper         <= PC_INCR;

      when STA_C3 =>

        CPU_Next_State       <= PIPE_FILL_2;

        Cache_Ctrl           <= CACHE_PREFETCH;

        PC_Ctrl.Oper         <= PC_INCR;

      when STO_C1 =>

        Cache_Ctrl           <= CACHE_PREFETCH;

        PC_Ctrl.Oper         <= PC_INCR;

        -- If auto-increment is disabled, just load the registers normally

        if( not Enable_Auto_Increment )then

          CPU_Next_State     <= PIPE_FILL_1;

          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;

        -- Otherwise, enforce the even register rule, and check the LSB to see

        --  if we should perform the auto-increment on the register pair

        else

          CPU_Next_State     <= PIPE_FILL_0;

          Reg                := conv_integer(SubOp(2 downto 1) & '0');

          Reg_1              := conv_integer(SubOp(2 downto 1) & '1');

          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;

          if( SubOp(0) = '1' )then

            CPU_Next_State   <= STO_C2;

            ALU_Ctrl.Oper    <= ALU_UPP;

            ALU_Ctrl.Reg     <= SubOp(2 downto 1) & '0';

          end if;

        end if;

      when STO_C2 =>

        CPU_Next_State       <= PIPE_FILL_1;

        PC_Ctrl.Oper         <= PC_INCR;

        ALU_Ctrl.Oper        <= ALU_UPP2;

        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';

      when STX_C1 =>

        PC_Ctrl.Oper         <= PC_INCR;

        -- If auto-increment is disabled, just load the registers normally

        if( not Enable_Auto_Increment )then

          CPU_Next_State     <= PIPE_FILL_1;

          Address            <= (Regfile(Reg_1) & Regfile(Reg));

        -- Otherwise, enforce the even register rule, and check the LSB to see

        --  if we should perform the auto-increment on the register pair

        else

          CPU_Next_State     <= PIPE_FILL_1;

          Reg                := conv_integer(SubOp(2 downto 1) & '0');

          Reg_1              := conv_integer(SubOp(2 downto 1) & '1');

          Address            <= (Regfile(Reg_1) & Regfile(Reg));

          if( SubOp(0) = '1' )then

            CPU_Next_State   <= STX_C2;

            ALU_Ctrl.Oper    <= ALU_UPP;

            ALU_Ctrl.Reg     <= SubOp(2 downto 1) & '0';

          end if;

        end if;

      when STX_C2 =>

        CPU_Next_State       <= PIPE_FILL_2;

        PC_Ctrl.Oper         <= PC_INCR;

        ALU_Ctrl.Oper        <= ALU_UPP2;

        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';

-------------------------------------------------------------------------------

-- Multi-Cycle Math Operations (UPP, MUL)

-------------------------------------------------------------------------------

      -- Because we have to backup the pipeline by 1 to refetch the 2nd

      --  instruction/first operand, we have to return through PF2

      when MUL_C1 =>

        CPU_Next_State       <= PIPE_FILL_2;

        PC_Ctrl.Oper         <= PC_INCR;

        ALU_Ctrl.Oper        <= ALU_MUL;

      when UPP_C1 =>

        CPU_Next_State       <= PIPE_FILL_2;

        PC_Ctrl.Oper         <= PC_INCR;

        ALU_Ctrl.Oper        <= ALU_UPP2;

        ALU_Ctrl.Reg         <= SubOp_p1;

-------------------------------------------------------------------------------

-- Basic Stack Manipulation (PSH, POP, RSP)

-------------------------------------------------------------------------------

      when PSH_C1 =>

        CPU_Next_State       <= PIPE_FILL_1;

        Address              <= Stack_Ptr;

        SP_Ctrl.Oper         <= SP_PUSH;

      when POP_C1 =>

        CPU_Next_State       <= POP_C2;

        Address              <= Stack_Ptr;

      when POP_C2 =>

        CPU_Next_State       <= POP_C3;

        PC_Ctrl.Oper         <= PC_INCR;

      when POP_C3 =>

        CPU_Next_State       <= POP_C4;

        Cache_Ctrl           <= CACHE_OPER1;

        PC_Ctrl.Oper         <= PC_INCR;

      when POP_C4 =>

        CPU_Next_State       <= INSTR_DECODE;

        Cache_Ctrl           <= CACHE_INSTR;

        PC_Ctrl.Oper         <= PC_INCR;

        ALU_Ctrl.Oper        <= ALU_POP;

        ALU_Ctrl.Reg         <= SubOp;

        ALU_Ctrl.Data        <= Operand1;

-------------------------------------------------------------------------------

-- Subroutines & Interrupts (RTS, JSR)

-------------------------------------------------------------------------------

      when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr

        DP_Ctrl.Src          <= DATA_BUS_IDLE;

        CPU_Next_State       <= WAIT_FOR_INT;

      when ISR_C1 =>

        CPU_Next_State       <= ISR_C2;

        Address              <= ISR_Addr;

        INT_Ctrl.Incr_ISR    <= '1';

      when ISR_C2 =>

        CPU_Next_State       <= ISR_C3;

        Address              <= ISR_Addr;

        DP_Ctrl.Src          <= DATA_WR_FLAG;

      when ISR_C3 =>

        CPU_Next_State       <= JSR_C1;

        Cache_Ctrl           <= CACHE_OPER1;

        Address              <= Stack_Ptr;

        SP_Ctrl.Oper         <= SP_PUSH;

        DP_Ctrl.Src          <= DATA_WR_PC;

        DP_Ctrl.Reg          <= ACCUM+1;

        ALU_Ctrl.Oper        <= ALU_STP;

        ALU_Ctrl.Reg         <= INT_FLAG;

        Ack_D                <= '1';

      when JSR_C1 =>

        CPU_Next_State       <= JSR_C2;

        Cache_Ctrl           <= CACHE_OPER2;

        Address              <= Stack_Ptr;

        SP_Ctrl.Oper         <= SP_PUSH;

        DP_Ctrl.Src          <= DATA_WR_PC;

        DP_Ctrl.Reg          <= ACCUM;

      when JSR_C2 =>

        CPU_Next_State       <= PIPE_FILL_0;

        Address              <= Stack_Ptr;

        SP_Ctrl.Oper         <= SP_PUSH;

        PC_Ctrl.Oper         <= PC_LOAD;

        PC_Ctrl.Addr         <= Operand2 & Operand1;

      when RTS_C1 =>

        CPU_Next_State       <= RTS_C2;

        Address              <= Stack_Ptr;

        SP_Ctrl.Oper         <= SP_POP;

      when RTS_C2 =>

        CPU_Next_State       <= RTS_C3;

        Address              <= Stack_Ptr;

        -- if this is an RTI, then we need to POP the flags

        if( SubOp = SOP_RTI )then

          SP_Ctrl.Oper       <= SP_POP;

        end if;

      when RTS_C3 =>

        CPU_Next_State       <= RTS_C4;

        Cache_Ctrl           <= CACHE_OPER1;

        -- It doesn't really matter what is on the address bus for RTS, while

        --  it does for RTI, so we make this the default

        Address              <= Stack_Ptr;

      when RTS_C4 =>

        CPU_Next_State       <= RTS_C5;

        Cache_Ctrl           <= CACHE_OPER2;