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1 185 jshamlet
-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
2 169 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
24 181 jshamlet
-- VHDL Units :  o8_cpu
25 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44
--            :   specified by Stack_Xfer_Flag. If the flag is '0', RSP will
45
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 181 jshamlet
--            :  Stack_Xfer_Flag instructs the core to use the specified ALU
52
--            :   flag to alter the behavior of the RSP instruction when
53
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it is ignored.
54
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
74
--            :   after an interrupt. By default, all of the flag bits are put
75
--            :   back to their original state. If this flag is set true, only
76
--            :   the lower four bits are restored, allowing ISR code to alter
77
--            :   the GP flags persistently.
78
--            :
79 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
80
--            :   interrupt mask. To remain true to the original core, which
81
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
82
--            :   it can be initialized to any value. Note that Enable_NMI
83
--            :   will logically force the LSB high.
84 172 jshamlet
--            :
85 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
86
--            :   on a high or low level from higher logic.
87
--            :
88
--            : Architecture notes
89
--            :  This model deviates from the original ISA in a few important
90
--            :   ways.
91
--            :
92
--            :  First, there is only one set of registers. Interrupt service
93
--            :   routines must explicitely preserve context since the the
94
--            :   hardware doesn't. This was done to decrease size and code
95
--            :   complexity. Older code that assumes this behavior will not
96
--            :   execute correctly on this processor model.
97
--            :
98
--            :  Second, this model adds an additional pipeline stage between
99
--            :   the instruction decoder and the ALU. Unfortunately, this
100
--            :   means that the instruction stream has to be restarted after
101
--            :   any math instruction is executed, implying that any ALU
102
--            :   instruction now has a latency of 2 instead of 0. The
103
--            :   advantage is that the maximum frequency has gone up
104
--            :   significantly, as the ALU code is vastly more efficient.
105
--            :   As an aside, this now means that all math instructions,
106
--            :   including MUL (see below) and UPP have the same instruction
107
--            :   latency.
108
--            :
109
--            :  Third, the original ISA, also a soft core, had two reserved
110
--            :   instructions, USR and USR2. These have been implemented as
111
--            :   DBNZ, and MUL respectively.
112
--            :
113
--            :  DBNZ decrements the specified register and branches if the
114
--            :   result is non-zero. The instruction effectively executes a
115
--            :   DEC Rn instruction prior to branching, so the same flags will
116
--            :   be set.
117
--            :
118
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
119
--            :   latency is identical to other ALU instructions. Only the Z
120
--            :   flag is set, since there is no defined overflow or "negative
121
--            :   16-bit values"
122
--            :
123
--            :  Fourth, indexed load/store instructions now have an (optional)
124
--            :   ability to post-increment their index registers. If enabled,
125
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
126
--            :   register pair to be incremented after the storage access.
127
--            :
128
--            :  Fifth, the RSP instruction has been (optionally) altered to
129
--            :   allow the stack pointer to be sourced from R1:R0.
130
--            :
131
--            :  Sixth, the BRK instruction can optionally implement a WAI,
132
--            :   which is the same as the INT instruction without the soft
133
--            :   interrupt, as a way to put the processor to "sleep" until the
134
--            :   next external interrupt.
135
--            :
136
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
137
--            :   with priority. This model has the same 8 interrupts, but
138 172 jshamlet
--            :   allows software to mask them (with an additional option to
139 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
140
--            :
141
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
142
--            :   were repurposed to support a new interrupt mask.
143
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
144
--            :   to/from the interrupt mask register. SMSK is immediate, while
145
--            :   GMSK has the same overhead as a math instruction.
146
--
147
-- Revision History
148
-- Author          Date     Change
149
------------------ -------- ---------------------------------------------------
150
-- Seth Henry      07/19/06 Design Start
151
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
152
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
153
--                           corruption issues.
154
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
155
--                           path sections.
156
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
157
--                           single entity.
158
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
159
--                           processor to wait for an interrupt instead of the
160
--                           normal BRK behavior.
161 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
162 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
163
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
164
--                           faster logic that simply does priority encoding.
165
-- Seth Henry      08/06/13 Removed HALT functionality
166
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
167 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
168 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
169
--                           allowing true backup/restore of the stack pointer
170 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
171
--                           in order to simplify things and eliminate
172
--                           redundancies. Came across and fixed a problem with
173
--                           the STO instruction when Enable_Auto_Increment is
174
--                           NOT set.
175 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
176
--                           the assembler names. Also fixed an issue where
177
--                           the I bit wasn't being cleared after interrupts.
178
--                          Simplified the program counter logic to only use
179
--                           the offset for increments, redefining the
180
--                           original modes as fixed offset values.
181
--                          Modified the ALU section with a new ALU operation
182
--                           for GMSK. This allowed the .data field to be
183
--                           removed and Operand1 used in its place, which
184
--                           simplified the logic a great deal.
185 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
186
--                           the instruction decode state, where it acts as a
187
--                           modified form of the BRK instruction that holds
188
--                           state until CPU_Halt is deasserted. This has a
189
--                           much smaller impact on Fmax/complexity than the
190
--                           original clock enable, but imposes a mild impact
191
--                           due to the need to reset the instruction pipeline
192 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
193
--                           the flags, including the general purpose ones, or
194
--                           only the core ALU flags (Z, N, and C). Also
195
--                           brought out copies of the GP flags for external
196
--                           connection.
197 169 jshamlet
 
198
library ieee;
199
  use ieee.std_logic_1164.all;
200
  use ieee.std_logic_unsigned.all;
201
  use ieee.std_logic_arith.all;
202
  use ieee.std_logic_misc.all;
203
 
204
library work;
205
use work.Open8_pkg.all;
206
 
207 183 jshamlet
entity o8_cpu is
208 169 jshamlet
  generic(
209
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
210
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
211
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
212
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
213 188 jshamlet
    Stack_Xfer_Flag          : integer      := PSR_GP4; -- GP4 modifies RSP
214 169 jshamlet
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
215
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
216
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
217 188 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI restores all flags
218 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
219
    Reset_Level              : std_logic    := '0' );   -- Active reset level
220
  port(
221
    Clock                    : in  std_logic;
222
    Reset                    : in  std_logic;
223 187 jshamlet
    CPU_Halt                 : in  std_logic := '0';
224
    Interrupts               : in  INTERRUPT_BUNDLE := x"00";
225 188 jshamlet
    GP_Flags                 : out EXT_GP_FLAGS;
226 169 jshamlet
    --
227
    Address                  : out ADDRESS_TYPE;
228
    Rd_Data                  : in  DATA_TYPE;
229
    Rd_Enable                : out std_logic;
230
    Wr_Data                  : out DATA_TYPE;
231
    Wr_Enable                : out std_logic );
232
end entity;
233
 
234 183 jshamlet
architecture behave of o8_cpu is
235 169 jshamlet
 
236
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;
237
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;
238
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;
239
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;
240
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;
241
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;
242
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;
243
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;
244
 
245 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
246
  signal CPU_State           : CPU_STATES := IPF_C0;
247 169 jshamlet
 
248 187 jshamlet
  signal CPU_Halt_Req        : std_logic;
249
 
250 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
251
 
252
  signal Opcode              : OPCODE_TYPE := (others => '0');
253
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
254
 
255
  signal Prefetch            : DATA_TYPE   := x"00";
256
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
257
 
258
  signal Instr_Prefetch      : std_logic   := '0';
259
 
260
  signal PC_Ctrl             : PC_CTRL_TYPE;
261
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
262
 
263 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
264
  signal Regfile             : REGFILE_TYPE;
265
  signal Flags               : FLAG_TYPE;
266
  signal Mult                : ADDRESS_TYPE := x"0000";
267
 
268 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
269
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
270
 
271
  signal DP_Ctrl             : DATA_CTRL_TYPE;
272
 
273
  signal INT_Ctrl            : INT_CTRL_TYPE;
274
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
275
  signal Int_Req, Int_Ack    : std_logic   := '0';
276
  signal Int_Mask            : DATA_TYPE   := x"00";
277
  signal ISR_Addr            : ADDRESS_TYPE := x"0000";
278
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
279
  signal Pending             : INTERRUPT_BUNDLE := x"00";
280
  signal Wait_for_FSM        : std_logic := '0';
281
 
282
begin
283
 
284 185 jshamlet
 
285 169 jshamlet
-------------------------------------------------------------------------------
286 182 jshamlet
-- Address bus selection/generation logic
287 169 jshamlet
-------------------------------------------------------------------------------
288
 
289 185 jshamlet
  Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1,
290
                         Operand2, Program_Ctr, Stack_Ptr, ISR_Addr )
291 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
292
    variable Offset_SX       : ADDRESS_TYPE;
293
  begin
294 182 jshamlet
 
295
    if( Enable_Auto_Increment )then
296
      Reg                    := conv_integer(SubOp(2 downto 1) & '0');
297
      Reg_1                  := conv_integer(SubOp(2 downto 1) & '1');
298
    else
299
      Reg                    := conv_integer(SubOp);
300
      Reg_1                  := conv_integer(SubOp_p1);
301
    end if;
302
 
303
    Offset_SX(15 downto 0)   := (others => Operand1(7));
304
    Offset_SX(7 downto 0)    := Operand1;
305
 
306
    case( CPU_State )is
307
 
308
      when LDA_C2 | STA_C2 =>
309
        Address              <= Operand2 & Operand1;
310
 
311
      when LDX_C1 | STX_C1 =>
312
        Address              <= (Regfile(Reg_1) & Regfile(Reg));
313
 
314
      when LDO_C1 | STO_C1 =>
315
        Address              <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
316
 
317
      when ISR_C1 | ISR_C2 =>
318
        Address              <= ISR_Addr;
319
 
320
      when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
321
        Address              <= Stack_Ptr;
322
 
323
      when others =>
324
        Address              <= Program_Ctr;
325
 
326
    end case;
327
 
328
  end process;
329
 
330
-------------------------------------------------------------------------------
331
-- Combinatorial portion of CPU finite state machine
332
-- State Logic / Instruction Decoding & Execution
333
-------------------------------------------------------------------------------
334
 
335 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
336 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
337
    variable Reg             : integer range 0 to 7 := 0;
338
  begin
339 169 jshamlet
    CPU_Next_State           <= CPU_State;
340
    Cache_Ctrl               <= CACHE_IDLE;
341
    --
342 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
343
    PC_Ctrl.Offset           <= PC_IDLE;
344 182 jshamlet
    --
345 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
346
    ALU_Ctrl.Reg             <= ACCUM;
347
    --
348
    SP_Ctrl.Oper             <= SP_IDLE;
349
    --
350
    DP_Ctrl.Src              <= DATA_RD_MEM;
351
    DP_Ctrl.Reg              <= ACCUM;
352
    --
353
    INT_Ctrl.Mask_Set        <= '0';
354
    INT_Ctrl.Soft_Ints       <= x"00";
355
    INT_Ctrl.Incr_ISR        <= '0';
356
    Ack_D                    <= '0';
357
 
358 182 jshamlet
    Reg                     := conv_integer(SubOp);
359 169 jshamlet
 
360
    case CPU_State is
361
-------------------------------------------------------------------------------
362
-- Initial Instruction fetch & decode
363
-------------------------------------------------------------------------------
364 187 jshamlet
      when IPF_C0 =>
365
        CPU_Next_State       <= IPF_C1;
366 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
367 169 jshamlet
 
368 187 jshamlet
      when IPF_C1 =>
369
        CPU_Next_State       <= IPF_C2;
370 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
371 169 jshamlet
 
372 187 jshamlet
      when IPF_C2 =>
373
        CPU_Next_State       <= IDC_C0;
374 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
375 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
376 169 jshamlet
 
377 187 jshamlet
      when IDC_C0 =>
378
        CPU_Next_State       <= IDC_C0;
379 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
380
 
381
        case Opcode is
382
          when OP_PSH =>
383
            CPU_Next_State   <= PSH_C1;
384
            Cache_Ctrl       <= CACHE_PREFETCH;
385 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
386 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
387
            DP_Ctrl.Reg      <= SubOp;
388
 
389
          when OP_POP =>
390
            CPU_Next_State   <= POP_C1;
391
            Cache_Ctrl       <= CACHE_PREFETCH;
392 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
393 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
394
 
395
          when OP_BR0 | OP_BR1 =>
396
            CPU_Next_State   <= BRN_C1;
397
            Cache_Ctrl       <= CACHE_OPER1;
398 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
399 169 jshamlet
 
400 185 jshamlet
 
401 169 jshamlet
          when OP_DBNZ =>
402
            CPU_Next_State   <= DBNZ_C1;
403
            Cache_Ctrl       <= CACHE_OPER1;
404 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
405 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
406
            ALU_Ctrl.Reg     <= SubOp;
407
 
408
          when OP_INT =>
409 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
410 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
411
            --  Also, unlike CPU_Halt, the INT instruction is actually being
412
            --  executed, so go ahead and increment the program counter before
413
            --  pausing so the CPU restarts on the next instruction.
414 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
415 187 jshamlet
              CPU_Next_State <= WAI_Cx;
416 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
417
            end if;
418
 
419
          when OP_STK =>
420
            case SubOp is
421
              when SOP_RSP  =>
422 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
423 181 jshamlet
                if( not Allow_Stack_Address_Move )then
424 187 jshamlet
                  -- The default behavior for this instruction is to simply
425
                  --  repoint the SP to the HDL default
426 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
427 181 jshamlet
                end if;
428 187 jshamlet
                if( Allow_Stack_Address_Move and
429
                    Flags(Stack_Xfer_Flag) = '1' )then
430
                  -- If RSP is set to allow SP moves, and the specified flag
431
                  --  is true, then signal the stack pointer logic to load
432
                  --  from R1:R0
433 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
434 181 jshamlet
                end if;
435 187 jshamlet
                if( Allow_Stack_Address_Move and
436
                    Flags(Stack_Xfer_Flag) = '0')then
437
                  -- If RSP is set to allow SP moves, and the specified flag
438
                  --  is false, then signal the ALU to copy the stack pointer
439
                  --  to R1:R0
440 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
441 181 jshamlet
                end if;
442 169 jshamlet
 
443
              when SOP_RTS | SOP_RTI =>
444 185 jshamlet
                CPU_Next_State    <= RTS_C1;
445 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
446 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
447 169 jshamlet
 
448
              when SOP_BRK  =>
449
                if( BRK_Implements_WAI )then
450 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
451
                  --  increment the PC similar to an ISR flow.
452
                  CPU_Next_State  <= WAI_Cx;
453 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
454 187 jshamlet
                else
455
                -- If Break is implemented normally, back the PC up by
456
                --  2 and return through IPF_C0 in order to execute a 5
457
                --  clock cycle delay
458
                  CPU_Next_State  <= BRK_C1;
459
                  PC_Ctrl.Offset  <= PC_REV2;
460 169 jshamlet
                end if;
461
 
462
              when SOP_JMP  =>
463 185 jshamlet
                CPU_Next_State    <= JMP_C1;
464
                Cache_Ctrl        <= CACHE_OPER1;
465 169 jshamlet
 
466
              when SOP_SMSK =>
467 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
468 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
469
 
470
              when SOP_GMSK =>
471 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
472
                ALU_Ctrl.Oper     <= ALU_GMSK;
473 169 jshamlet
 
474
              when SOP_JSR =>
475
                CPU_Next_State <= JSR_C1;
476 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
477
                DP_Ctrl.Src       <= DATA_WR_PC;
478
                DP_Ctrl.Reg       <= PC_MSB;
479 169 jshamlet
 
480
              when others => null;
481
            end case;
482
 
483
          when OP_MUL =>
484
            CPU_Next_State   <= MUL_C1;
485 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
486
            --  to the ALU writing the result to registers. As a result, this
487
            --  state needs to idle the ALU initially, and back the PC up by 1
488
            -- We can get away with only 1 extra clock by pre-fetching the
489
            --  next instruction, though.
490 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
491 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
492 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
493
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
494
            --  now, but hold off on the ALU command until the next state.
495 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
496
            ALU_Ctrl.Reg     <= SubOp;
497
 
498
          when OP_UPP =>
499
            CPU_Next_State   <= UPP_C1;
500
            Cache_Ctrl       <= CACHE_PREFETCH;
501 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
502 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
503
            ALU_Ctrl.Reg     <= SubOp;
504
 
505
          when OP_LDA =>
506
            CPU_Next_State   <= LDA_C1;
507
            Cache_Ctrl       <= CACHE_OPER1;
508
 
509
          when OP_LDI =>
510
            CPU_Next_State   <= LDI_C1;
511
            Cache_Ctrl       <= CACHE_OPER1;
512 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
513 169 jshamlet
 
514
          when OP_LDO =>
515
            CPU_Next_State   <= LDO_C1;
516
            Cache_Ctrl       <= CACHE_OPER1;
517 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
518 169 jshamlet
 
519
          when OP_LDX =>
520
            CPU_Next_State   <= LDX_C1;
521 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
522 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
523 169 jshamlet
 
524
          when OP_STA =>
525
            CPU_Next_State   <= STA_C1;
526
            Cache_Ctrl       <= CACHE_OPER1;
527
 
528
          when OP_STO =>
529
            CPU_Next_State   <= STO_C1;
530
            Cache_Ctrl       <= CACHE_OPER1;
531 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
532 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
533
            DP_Ctrl.Reg      <= ACCUM;
534
 
535
          when OP_STX =>
536
            CPU_Next_State   <= STX_C1;
537
            Cache_Ctrl       <= CACHE_PREFETCH;
538 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
539 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
540
            DP_Ctrl.Reg      <= ACCUM;
541
 
542
          when others =>
543 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
544 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
545
            ALU_Ctrl.Reg     <= SubOp;
546
 
547
        end case;
548
 
549 186 jshamlet
        if( Int_Req = '1' )then
550
          CPU_Next_State     <= ISR_C1;
551 187 jshamlet
        end if;
552
 
553
        if( CPU_Halt_Req = '1' )then
554
          CPU_Next_State     <= WAH_Cx;
555
        end if;
556
 
557
        -- If either of these override conditions are true, the decoder needs
558
        --  to undo everything it just setup, since even "single-cycle"
559
        --  instructions will be executed again upon return.
560
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
561
          -- In either case, we want to skip loading the cache, as the cache
562
          --  will be invalid by the time we get back.
563 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
564 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
565
          -- compensating for the pipeline registers.
566 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
567
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
568 187 jshamlet
          --  operation due to the current instruction.
569 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
570
          SP_Ctrl.Oper       <= SP_IDLE;
571 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
572
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
573 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
574 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
575
          --  executed again when normal processing resumes, so axe their
576
          --  requests for now.
577
          INT_Ctrl.Mask_Set       <= '0';
578
          INT_Ctrl.Soft_Ints(Reg) <= '0';
579 186 jshamlet
        end if;
580
 
581 169 jshamlet
-------------------------------------------------------------------------------
582
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
583
-------------------------------------------------------------------------------
584
 
585
      when BRN_C1 =>
586 187 jshamlet
        CPU_Next_State       <= IDC_C0;
587 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
588 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
589 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
590 187 jshamlet
          CPU_Next_State     <= IPF_C0;
591 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
592
          PC_Ctrl.Offset     <= Operand1;
593
        end if;
594
 
595
      when DBNZ_C1 =>
596 187 jshamlet
        CPU_Next_State       <= IDC_C0;
597 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
598 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
599
        if( Flags(PSR_Z) = '0' )then
600 187 jshamlet
          CPU_Next_State     <= IPF_C0;
601 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
602
          PC_Ctrl.Offset     <= Operand1;
603
        end if;
604
 
605
      when JMP_C1 =>
606
        CPU_Next_State       <= JMP_C2;
607
        Cache_Ctrl           <= CACHE_OPER2;
608
 
609
      when JMP_C2 =>
610 187 jshamlet
        CPU_Next_State       <= IPF_C0;
611 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
612
 
613
-------------------------------------------------------------------------------
614
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
615
-------------------------------------------------------------------------------
616
 
617
      when LDA_C1 =>
618
        CPU_Next_State       <= LDA_C2;
619
        Cache_Ctrl           <= CACHE_OPER2;
620
 
621
      when LDA_C2 =>
622
        CPU_Next_State       <= LDA_C3;
623
 
624
      when LDA_C3 =>
625
        CPU_Next_State       <= LDA_C4;
626 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
627 169 jshamlet
 
628
      when LDA_C4 =>
629
        CPU_Next_State       <= LDI_C1;
630
        Cache_Ctrl           <= CACHE_OPER1;
631 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
632 169 jshamlet
 
633
      when LDI_C1 =>
634 187 jshamlet
        CPU_Next_State       <= IDC_C0;
635 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
636 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
637 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
638
        ALU_Ctrl.Reg         <= SubOp;
639
 
640
      when LDO_C1 =>
641 181 jshamlet
        CPU_Next_State       <= LDX_C2;
642 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
643 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
644
          ALU_Ctrl.Oper      <= ALU_UPP;
645
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
646 169 jshamlet
        end if;
647
 
648
      when LDX_C1 =>
649
        CPU_Next_State       <= LDX_C2;
650 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
651
          ALU_Ctrl.Oper      <= ALU_UPP;
652
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
653 181 jshamlet
        end if;
654 169 jshamlet
 
655
      when LDX_C2 =>
656
        CPU_Next_State       <= LDX_C3;
657 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
658 181 jshamlet
 
659
      when LDX_C3 =>
660
        CPU_Next_State       <= LDX_C4;
661 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
662 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
663 169 jshamlet
 
664 181 jshamlet
      when LDX_C4 =>
665 187 jshamlet
        CPU_Next_State       <= IDC_C0;
666 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
667 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
668 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
669 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
670
 
671
-------------------------------------------------------------------------------
672
-- Data Storage - Store to memory (STA, STO, STX)
673
-------------------------------------------------------------------------------
674
      when STA_C1 =>
675
        CPU_Next_State       <= STA_C2;
676
        Cache_Ctrl           <= CACHE_OPER2;
677
        DP_Ctrl.Src          <= DATA_WR_REG;
678
        DP_Ctrl.Reg          <= SubOp;
679
 
680
      when STA_C2 =>
681
        CPU_Next_State       <= STA_C3;
682 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
683 169 jshamlet
 
684
      when STA_C3 =>
685 187 jshamlet
        CPU_Next_State       <= IPF_C2;
686 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
687 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
688 169 jshamlet
 
689
      when STO_C1 =>
690 187 jshamlet
        CPU_Next_State       <= IPF_C0;
691 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
692 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
693 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
694
          CPU_Next_State     <= STO_C2;
695
          ALU_Ctrl.Oper      <= ALU_UPP;
696
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
697 169 jshamlet
        end if;
698
 
699
      when STO_C2 =>
700 187 jshamlet
        CPU_Next_State       <= IPF_C1;
701 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
702 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
703
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
704
 
705
      when STX_C1 =>
706 187 jshamlet
        CPU_Next_State       <= IPF_C1;
707 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
708 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
709
          CPU_Next_State     <= STX_C2;
710
          ALU_Ctrl.Oper      <= ALU_UPP;
711
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
712 169 jshamlet
        end if;
713
 
714
      when STX_C2 =>
715 187 jshamlet
        CPU_Next_State       <= IPF_C2;
716 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
717 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
718
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
719
 
720
-------------------------------------------------------------------------------
721
-- Multi-Cycle Math Operations (UPP, MUL)
722
-------------------------------------------------------------------------------
723
 
724
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
725 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
726
      --  need to tell the ALU to store the results to R1:R0 here. Note that
727
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
728 169 jshamlet
      when MUL_C1 =>
729 187 jshamlet
        CPU_Next_State       <= IPF_C2;
730 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
731 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
732
 
733
      when UPP_C1 =>
734 187 jshamlet
        CPU_Next_State       <= IPF_C2;
735 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
736 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
737
        ALU_Ctrl.Reg         <= SubOp_p1;
738
 
739
-------------------------------------------------------------------------------
740
-- Basic Stack Manipulation (PSH, POP, RSP)
741
-------------------------------------------------------------------------------
742
      when PSH_C1 =>
743 187 jshamlet
        CPU_Next_State       <= IPF_C1;
744 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
745
 
746
      when POP_C1 =>
747
        CPU_Next_State       <= POP_C2;
748
 
749
      when POP_C2 =>
750
        CPU_Next_State       <= POP_C3;
751 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
752 169 jshamlet
 
753
      when POP_C3 =>
754
        CPU_Next_State       <= POP_C4;
755
        Cache_Ctrl           <= CACHE_OPER1;
756 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
757 169 jshamlet
 
758
      when POP_C4 =>
759 187 jshamlet
        CPU_Next_State       <= IDC_C0;
760 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
761 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
762 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
763
        ALU_Ctrl.Reg         <= SubOp;
764 172 jshamlet
 
765 169 jshamlet
-------------------------------------------------------------------------------
766
-- Subroutines & Interrupts (RTS, JSR)
767
-------------------------------------------------------------------------------
768 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
769 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
770 186 jshamlet
        if( Int_Req = '1' )then
771
          CPU_Next_State     <= ISR_C1;
772 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
773
          --  instruction, compensating for the pipeline registers.
774 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
775
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
776
          --  operation due to the current instruction
777
          DP_Ctrl.Src        <= DATA_RD_MEM;
778
        end if;
779 169 jshamlet
 
780 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
781
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
782
        if( CPU_Halt_Req = '0' )then
783
          CPU_Next_State     <= IPF_C0;
784
          DP_Ctrl.Src        <= DATA_RD_MEM;
785
        end if;
786
 
787
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
788
        CPU_Next_State       <= IPF_C0;
789
 
790 169 jshamlet
      when ISR_C1 =>
791
        CPU_Next_State       <= ISR_C2;
792
        INT_Ctrl.Incr_ISR    <= '1';
793
 
794
      when ISR_C2 =>
795
        CPU_Next_State       <= ISR_C3;
796
        DP_Ctrl.Src          <= DATA_WR_FLAG;
797
 
798
      when ISR_C3 =>
799
        CPU_Next_State       <= JSR_C1;
800
        Cache_Ctrl           <= CACHE_OPER1;
801 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
802 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
803 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
804
        DP_Ctrl.Src          <= DATA_WR_PC;
805 182 jshamlet
        DP_Ctrl.Reg          <= PC_MSB;
806 169 jshamlet
        Ack_D                <= '1';
807
 
808
      when JSR_C1 =>
809
        CPU_Next_State       <= JSR_C2;
810
        Cache_Ctrl           <= CACHE_OPER2;
811
        SP_Ctrl.Oper         <= SP_PUSH;
812
        DP_Ctrl.Src          <= DATA_WR_PC;
813 182 jshamlet
        DP_Ctrl.Reg          <= PC_LSB;
814 169 jshamlet
 
815
      when JSR_C2 =>
816 187 jshamlet
        CPU_Next_State       <= IPF_C0;
817 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
818 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
819 169 jshamlet
 
820
      when RTS_C1 =>
821
        CPU_Next_State       <= RTS_C2;
822
        SP_Ctrl.Oper         <= SP_POP;
823
 
824
      when RTS_C2 =>
825
        CPU_Next_State       <= RTS_C3;
826
        -- if this is an RTI, then we need to POP the flags
827
        if( SubOp = SOP_RTI )then
828
          SP_Ctrl.Oper       <= SP_POP;
829
        end if;
830
 
831
      when RTS_C3 =>
832
        CPU_Next_State       <= RTS_C4;
833
        Cache_Ctrl           <= CACHE_OPER1;
834
 
835
      when RTS_C4 =>
836
        CPU_Next_State       <= RTS_C5;
837
        Cache_Ctrl           <= CACHE_OPER2;
838
 
839
      when RTS_C5 =>
840 187 jshamlet
        CPU_Next_State       <= IPF_C0;
841 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
842 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
843 169 jshamlet
        if( SubOp = SOP_RTI )then
844
          CPU_Next_State     <= RTI_C6;
845
          Cache_Ctrl         <= CACHE_OPER1;
846 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
847
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
848 169 jshamlet
        end if;
849
 
850
      when RTI_C6 =>
851 187 jshamlet
        CPU_Next_State       <= IPF_C1;
852 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
853 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
854
 
855
      when others =>
856
        null;
857
    end case;
858
 
859
  end process;
860
 
861
-------------------------------------------------------------------------------
862
-- Registered portion of CPU finite state machine
863
-------------------------------------------------------------------------------
864 182 jshamlet
 
865 169 jshamlet
  CPU_Regs: process( Reset, Clock )
866
    variable Offset_SX       : ADDRESS_TYPE;
867 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
868 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
869
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
870
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
871
  begin
872
    if( Reset = Reset_Level )then
873 187 jshamlet
      CPU_State              <= IPF_C0;
874 169 jshamlet
      Opcode                 <= OP_INC;
875
      SubOp                  <= ACCUM;
876
      SubOp_p1               <= ACCUM;
877
      Operand1               <= x"00";
878
      Operand2               <= x"00";
879
      Instr_Prefetch         <= '0';
880
      Prefetch               <= x"00";
881
 
882 187 jshamlet
      CPU_Halt_Req           <= '0';
883
 
884 191 jshamlet
      Wr_Data                <= OPEN8_NULLBUS;
885 169 jshamlet
      Wr_Enable              <= '0';
886
      Rd_Enable              <= '1';
887
 
888
      Program_Ctr            <= Program_Start_Addr;
889
      Stack_Ptr              <= Stack_Start_Addr;
890
 
891
      Ack_Q                  <= '0';
892
      Ack_Q1                 <= '0';
893
      Int_Ack                <= '0';
894
 
895
      Int_Req                <= '0';
896
      Pending                <= x"00";
897
      Wait_for_FSM           <= '0';
898
      if( Enable_NMI )then
899
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
900
      else
901
        Int_Mask             <= Default_Interrupt_Mask;
902
      end if;
903
      ISR_Addr               <= INT_VECTOR_0;
904
 
905
      for i in 0 to 7 loop
906 188 jshamlet
        Regfile(i)           <= x"00";
907 169 jshamlet
      end loop;
908
      Flags                  <= x"00";
909
 
910 188 jshamlet
      GP_Flags               <= x"0";
911
 
912 169 jshamlet
    elsif( rising_edge(Clock) )then
913 187 jshamlet
 
914
      CPU_Halt_Req           <= CPU_Halt;
915
 
916 169 jshamlet
      Wr_Enable              <= '0';
917 191 jshamlet
      Wr_Data                <= OPEN8_NULLBUS;
918 169 jshamlet
      Rd_Enable              <= '0';
919
 
920
-------------------------------------------------------------------------------
921
-- Instruction/Operand caching for pipelined memory access
922
-------------------------------------------------------------------------------
923
      CPU_State              <= CPU_Next_State;
924
      case Cache_Ctrl is
925
        when CACHE_INSTR =>
926
          Opcode             <= Rd_Data(7 downto 3);
927
          SubOp              <= Rd_Data(2 downto 0);
928
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
929
          if( Instr_Prefetch = '1' )then
930
            Opcode           <= Prefetch(7 downto 3);
931
            SubOp            <= Prefetch(2 downto 0);
932
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
933
            Instr_Prefetch   <= '0';
934
          end if;
935
 
936
        when CACHE_OPER1 =>
937
          Operand1           <= Rd_Data;
938
 
939
        when CACHE_OPER2 =>
940
          Operand2           <= Rd_Data;
941
 
942
        when CACHE_PREFETCH =>
943
          Prefetch           <= Rd_Data;
944
          Instr_Prefetch     <= '1';
945
 
946
        when CACHE_IDLE =>
947
          null;
948
      end case;
949
 
950
-------------------------------------------------------------------------------
951
-- Program Counter
952
-------------------------------------------------------------------------------
953
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
954
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
955
 
956
      case PC_Ctrl.Oper is
957
        when PC_INCR =>
958
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
959
 
960
        when PC_LOAD =>
961 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
962 169 jshamlet
 
963
        when others =>
964
          null;
965
      end case;
966
 
967
-------------------------------------------------------------------------------
968
-- (Write) Data Path
969
-------------------------------------------------------------------------------
970
      case DP_Ctrl.Src is
971
        when DATA_BUS_IDLE =>
972
          null;
973
 
974
        when DATA_RD_MEM =>
975
          Rd_Enable          <= '1';
976
 
977
        when DATA_WR_REG =>
978
          Wr_Enable          <= '1';
979
          Wr_Data            <= Regfile(conv_integer(DP_Ctrl.Reg));
980
 
981
        when DATA_WR_FLAG =>
982
          Wr_Enable          <= '1';
983
          Wr_Data            <= Flags;
984
 
985
        when DATA_WR_PC =>
986
          Wr_Enable          <= '1';
987
          Wr_Data            <= Program_Ctr(15 downto 8);
988 182 jshamlet
          if( DP_Ctrl.Reg = PC_LSB )then
989 169 jshamlet
            Wr_Data          <= Program_Ctr(7 downto 0);
990
          end if;
991
 
992
        when others =>
993
          null;
994
      end case;
995
 
996
-------------------------------------------------------------------------------
997
-- Stack Pointer
998
-------------------------------------------------------------------------------
999
      case SP_Ctrl.Oper is
1000
        when SP_IDLE =>
1001
          null;
1002
 
1003 181 jshamlet
        when SP_CLR =>
1004 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1005
 
1006 181 jshamlet
        when SP_SET =>
1007
          Stack_Ptr          <= Regfile(1) & Regfile(0);
1008
 
1009 169 jshamlet
        when SP_POP  =>
1010
          Stack_Ptr          <= Stack_Ptr + 1;
1011
 
1012
        when SP_PUSH =>
1013
          Stack_Ptr          <= Stack_Ptr - 1;
1014
 
1015
        when others =>
1016
          null;
1017
 
1018
      end case;
1019
 
1020
-------------------------------------------------------------------------------
1021
-- Interrupt Controller
1022
-------------------------------------------------------------------------------
1023
      -- The interrupt control mask is always sourced out of R0
1024
      if( INT_Ctrl.Mask_Set = '1' )then
1025
        if( Enable_NMI )then
1026
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1027
        else
1028
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1029
        end if;
1030
      end if;
1031
 
1032
      -- Combine external and internal interrupts, and mask the OR of the two
1033
      --  with the mask. Record any incoming interrupts to the pending buffer
1034
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1035
                                Int_Mask;
1036 172 jshamlet
 
1037 169 jshamlet
      Pending                <= i_Ints or Pending;
1038
 
1039
      if( Wait_for_FSM = '0' )then
1040
        if(    Pending(0) = '1' )then
1041
          ISR_Addr           <= INT_VECTOR_0;
1042
          Pending(0)         <= '0';
1043
        elsif( Pending(1) = '1' )then
1044
          ISR_Addr           <= INT_VECTOR_1;
1045
          Pending(1)         <= '0';
1046
        elsif( Pending(2) = '1' )then
1047
          ISR_Addr           <= INT_VECTOR_2;
1048
          Pending(2)         <= '0';
1049
        elsif( Pending(3) = '1' )then
1050
          ISR_Addr           <= INT_VECTOR_3;
1051
          Pending(3)         <= '0';
1052
        elsif( Pending(4) = '1' )then
1053
          ISR_Addr           <= INT_VECTOR_4;
1054
          Pending(4)         <= '0';
1055
        elsif( Pending(5) = '1' )then
1056
          ISR_Addr           <= INT_VECTOR_5;
1057
          Pending(5)         <= '0';
1058
        elsif( Pending(6) = '1' )then
1059
          ISR_Addr           <= INT_VECTOR_6;
1060
          Pending(6)         <= '0';
1061
        elsif( Pending(7) = '1' )then
1062
          ISR_Addr           <= INT_VECTOR_7;
1063
          Pending(7)         <= '0';
1064
        end if;
1065 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1066 169 jshamlet
      end if;
1067
 
1068
      -- Reset the Wait_for_FSM flag on Int_Ack
1069
      Ack_Q                  <= Ack_D;
1070
      Ack_Q1                 <= Ack_Q;
1071
      Int_Ack                <= Ack_Q1;
1072
      if( Int_Ack = '1' )then
1073
        Wait_for_FSM         <= '0';
1074
      end if;
1075
 
1076
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1077
 
1078
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1079
      --  lower half of the address.
1080
      if( INT_Ctrl.Incr_ISR = '1' )then
1081
        ISR_Addr             <= ISR_Addr + 1;
1082
      end if;
1083
 
1084
-------------------------------------------------------------------------------
1085
-- ALU (Arithmetic / Logic Unit)
1086
-------------------------------------------------------------------------------
1087
      Index                  := conv_integer(ALU_Ctrl.Reg);
1088
      Sum                    := (others => '0');
1089
      Temp                   := (others => '0');
1090
 
1091
      case ALU_Ctrl.Oper is
1092
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1093
          Sum                := ("0" & x"01") +
1094
                                ("0" & Regfile(Index));
1095 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1096
          Flags(PSR_C)       <= Sum(8);
1097
          Flags(PSR_N)      <= Sum(7);
1098 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1099
 
1100
        when ALU_UPP => -- Rn = Rn + 1
1101
          Sum                := ("0" & x"01") +
1102
                                ("0" & Regfile(Index));
1103 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1104 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1105
 
1106
        when ALU_UPP2 => -- Rn = Rn + C
1107
          Sum                := ("0" & x"00") +
1108
                                ("0" & Regfile(Index)) +
1109 185 jshamlet
                                Flags(PSR_C);
1110
          Flags(PSR_C)       <= Sum(8);
1111 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1112
 
1113
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1114
          Sum                := ("0" & Regfile(0)) +
1115
                                ("0" & Regfile(Index)) +
1116 185 jshamlet
                                Flags(PSR_C);
1117
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1118
          Flags(PSR_C)       <= Sum(8);
1119
          Flags(PSR_N)       <= Sum(7);
1120 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1121
 
1122
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1123
          Temp               := "0" & Regfile(Index);
1124 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1125
          Flags(PSR_N)       <= Temp(7);
1126 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1127
 
1128
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1129
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1130 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1131
          Flags(PSR_N)       <= Temp(7);
1132 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1133
 
1134
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1135
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1136 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1137
          Flags(PSR_N)       <= Temp(7);
1138 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1139
 
1140
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1141
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1142 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1143
          Flags(PSR_N)       <= Temp(7);
1144 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1145
 
1146
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1147 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1148
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1149
          Flags(PSR_C)       <= Temp(8);
1150
          Flags(PSR_N)       <= Temp(7);
1151 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1152
 
1153
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1154 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1155 169 jshamlet
                                Regfile(Index)(7 downto 1);
1156 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1157
          Flags(PSR_C)       <= Temp(8);
1158
          Flags(PSR_N)       <= Temp(7);
1159 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1160
 
1161
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1162
          Sum                := ("0" & Regfile(Index)) +
1163
                                ("0" & x"FF");
1164 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1165
          Flags(PSR_C)       <= Sum(8);
1166
          Flags(PSR_N)       <= Sum(7);
1167 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1168
 
1169
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1170
          Sum                := ("0" & Regfile(0)) +
1171
                                ("1" & (not Regfile(Index))) +
1172 185 jshamlet
                                Flags(PSR_C);
1173
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1174
          Flags(PSR_C)       <= Sum(8);
1175
          Flags(PSR_N)       <= Sum(7);
1176 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1177
 
1178
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1179
          Sum                := ("0" & Regfile(0)) +
1180
                                ("0" & Regfile(Index));
1181 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1182 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1183 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1184
          Flags(PSR_N)       <= Sum(7);
1185 169 jshamlet
 
1186
        when ALU_STP => -- Sets bit(n) in the Flags register
1187
          Flags(Index)       <= '1';
1188
 
1189
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1190 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1191
          Flags(PSR_N)       <= Regfile(0)(7);
1192 169 jshamlet
 
1193
        when ALU_CLP => -- Clears bit(n) in the Flags register
1194
          Flags(Index)       <= '0';
1195
 
1196
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1197
          Temp               := "0" & Regfile(0);
1198 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1199
          Flags(PSR_N)       <= Temp(7);
1200 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1201
 
1202
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1203
          Sum                := ("0" & Regfile(0)) +
1204
                                ("1" & (not Regfile(Index))) +
1205
                                '1';
1206 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1207
          Flags(PSR_C)       <= Sum(8);
1208
          Flags(PSR_N)       <= Sum(7);
1209 169 jshamlet
 
1210
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1211
          Regfile(0)         <= Mult(7 downto 0);
1212
          Regfile(1)         <= Mult(15 downto 8);
1213 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1214 169 jshamlet
 
1215
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1216 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1217
          Flags(PSR_N)       <= Operand1(7);
1218
          Regfile(Index)     <= Operand1;
1219 169 jshamlet
 
1220
        when ALU_POP => -- Rn <= Data
1221 185 jshamlet
          Regfile(Index)     <= Operand1;
1222 169 jshamlet
 
1223
        when ALU_RFLG =>
1224 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1225
          if( not RTI_Ignores_GP_Flags )then
1226
            Flags(7 downto 4)<= Operand1(7 downto 4);
1227
          end if;
1228 169 jshamlet
 
1229 185 jshamlet
        when ALU_RSP =>
1230 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1231
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1232
 
1233 185 jshamlet
        when ALU_GMSK =>
1234
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1235
          Regfile(0)         <= Int_Mask;
1236
 
1237 169 jshamlet
        when others =>
1238
          null;
1239
      end case;
1240
 
1241 188 jshamlet
      GP_Flags               <= Flags(7 downto 4);
1242
 
1243 169 jshamlet
    end if;
1244
  end process;
1245
 
1246 182 jshamlet
-------------------------------------------------------------------------------
1247
-- Multiplier Logic
1248
--
1249
-- We need to infer a hardware multipler, so we create a special clocked
1250
--  process with no reset or clock enable
1251
-------------------------------------------------------------------------------
1252
 
1253
  Multiplier_proc: process( Clock )
1254
  begin
1255
    if( rising_edge(Clock) )then
1256
      Mult                   <= Regfile(0) *
1257 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1258
    end if;
1259
  end process;
1260
 
1261
end architecture;

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