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1 185 jshamlet
-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
2 169 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
24 181 jshamlet
-- VHDL Units :  o8_cpu
25 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44
--            :   specified by Stack_Xfer_Flag. If the flag is '0', RSP will
45
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 181 jshamlet
--            :  Stack_Xfer_Flag instructs the core to use the specified ALU
52
--            :   flag to alter the behavior of the RSP instruction when
53
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it is ignored.
54
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
74
--            :   after an interrupt. By default, all of the flag bits are put
75
--            :   back to their original state. If this flag is set true, only
76
--            :   the lower four bits are restored, allowing ISR code to alter
77
--            :   the GP flags persistently.
78
--            :
79 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
80
--            :   interrupt mask. To remain true to the original core, which
81
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
82
--            :   it can be initialized to any value. Note that Enable_NMI
83
--            :   will logically force the LSB high.
84 172 jshamlet
--            :
85 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
86
--            :   on a high or low level from higher logic.
87
--            :
88
--            : Architecture notes
89
--            :  This model deviates from the original ISA in a few important
90
--            :   ways.
91
--            :
92
--            :  First, there is only one set of registers. Interrupt service
93
--            :   routines must explicitely preserve context since the the
94
--            :   hardware doesn't. This was done to decrease size and code
95
--            :   complexity. Older code that assumes this behavior will not
96
--            :   execute correctly on this processor model.
97
--            :
98
--            :  Second, this model adds an additional pipeline stage between
99
--            :   the instruction decoder and the ALU. Unfortunately, this
100
--            :   means that the instruction stream has to be restarted after
101
--            :   any math instruction is executed, implying that any ALU
102
--            :   instruction now has a latency of 2 instead of 0. The
103
--            :   advantage is that the maximum frequency has gone up
104
--            :   significantly, as the ALU code is vastly more efficient.
105
--            :   As an aside, this now means that all math instructions,
106
--            :   including MUL (see below) and UPP have the same instruction
107
--            :   latency.
108
--            :
109
--            :  Third, the original ISA, also a soft core, had two reserved
110
--            :   instructions, USR and USR2. These have been implemented as
111
--            :   DBNZ, and MUL respectively.
112
--            :
113
--            :  DBNZ decrements the specified register and branches if the
114
--            :   result is non-zero. The instruction effectively executes a
115
--            :   DEC Rn instruction prior to branching, so the same flags will
116
--            :   be set.
117
--            :
118
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
119
--            :   latency is identical to other ALU instructions. Only the Z
120
--            :   flag is set, since there is no defined overflow or "negative
121
--            :   16-bit values"
122
--            :
123
--            :  Fourth, indexed load/store instructions now have an (optional)
124
--            :   ability to post-increment their index registers. If enabled,
125
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
126
--            :   register pair to be incremented after the storage access.
127
--            :
128
--            :  Fifth, the RSP instruction has been (optionally) altered to
129
--            :   allow the stack pointer to be sourced from R1:R0.
130
--            :
131
--            :  Sixth, the BRK instruction can optionally implement a WAI,
132
--            :   which is the same as the INT instruction without the soft
133
--            :   interrupt, as a way to put the processor to "sleep" until the
134
--            :   next external interrupt.
135
--            :
136
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
137
--            :   with priority. This model has the same 8 interrupts, but
138 172 jshamlet
--            :   allows software to mask them (with an additional option to
139 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
140
--            :
141
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
142
--            :   were repurposed to support a new interrupt mask.
143
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
144
--            :   to/from the interrupt mask register. SMSK is immediate, while
145
--            :   GMSK has the same overhead as a math instruction.
146
--
147
-- Revision History
148
-- Author          Date     Change
149
------------------ -------- ---------------------------------------------------
150
-- Seth Henry      07/19/06 Design Start
151
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
152
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
153
--                           corruption issues.
154
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
155
--                           path sections.
156
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
157
--                           single entity.
158
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
159
--                           processor to wait for an interrupt instead of the
160
--                           normal BRK behavior.
161 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
162 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
163
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
164
--                           faster logic that simply does priority encoding.
165
-- Seth Henry      08/06/13 Removed HALT functionality
166
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
167 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
168 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
169
--                           allowing true backup/restore of the stack pointer
170 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
171
--                           in order to simplify things and eliminate
172
--                           redundancies. Came across and fixed a problem with
173
--                           the STO instruction when Enable_Auto_Increment is
174
--                           NOT set.
175 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
176
--                           the assembler names. Also fixed an issue where
177
--                           the I bit wasn't being cleared after interrupts.
178
--                          Simplified the program counter logic to only use
179
--                           the offset for increments, redefining the
180
--                           original modes as fixed offset values.
181
--                          Modified the ALU section with a new ALU operation
182
--                           for GMSK. This allowed the .data field to be
183
--                           removed and Operand1 used in its place, which
184
--                           simplified the logic a great deal.
185 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
186
--                           the instruction decode state, where it acts as a
187
--                           modified form of the BRK instruction that holds
188
--                           state until CPU_Halt is deasserted. This has a
189
--                           much smaller impact on Fmax/complexity than the
190
--                           original clock enable, but imposes a mild impact
191
--                           due to the need to reset the instruction pipeline
192 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
193
--                           the flags, including the general purpose ones, or
194
--                           only the core ALU flags (Z, N, and C). Also
195
--                           brought out copies of the GP flags for external
196
--                           connection.
197 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
198
--                           while the I bit is set to avoid reentering ISRs
199
--                           This may slightly affect timing, as this will
200
--                           potentially block higher priority interrupts
201
--                           until the lower priority ISR returns or clears
202
--                           the I bit.
203
--                          Also added the I bit to the exported flags for
204
--                           use in memory protection schemes.
205 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
206 225 jshamlet
--                           reset and usec_tick logic to drive utility
207
--                           signals. Also added Halt_Ack output.
208 169 jshamlet
 
209
library ieee;
210
  use ieee.std_logic_1164.all;
211
  use ieee.std_logic_unsigned.all;
212
  use ieee.std_logic_arith.all;
213
  use ieee.std_logic_misc.all;
214
 
215
library work;
216 227 jshamlet
  use work.Open8_pkg.all;
217 169 jshamlet
 
218 183 jshamlet
entity o8_cpu is
219 169 jshamlet
  generic(
220
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
221
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
222
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
223
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
224 188 jshamlet
    Stack_Xfer_Flag          : integer      := PSR_GP4; -- GP4 modifies RSP
225 169 jshamlet
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
226
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
227
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
228 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
229 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
230 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
231 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
232
);
233 169 jshamlet
  port(
234
    Clock                    : in  std_logic;
235 224 jshamlet
    PLL_Locked               : in  std_logic;
236 169 jshamlet
    --
237 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
238
    Halt_Ack                 : out std_logic;
239
    --
240 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
241 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
242 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
243
);
244 169 jshamlet
end entity;
245
 
246 183 jshamlet
architecture behave of o8_cpu is
247 169 jshamlet
 
248 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
249
  signal Reset               : std_logic := Reset_Level;
250
 
251
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
252
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
253
  constant USEC_DLY          : std_logic_vector :=
254
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
255
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
256
  signal uSec_Tick           : std_logic;
257
 
258 169 jshamlet
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;
259
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;
260
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;
261
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;
262
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;
263
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;
264
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;
265
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;
266
 
267 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
268
  signal CPU_State           : CPU_STATES := IPF_C0;
269 169 jshamlet
 
270 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
271
  signal CPU_Halt_Ack        : std_logic := '0';
272 187 jshamlet
 
273 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
274
 
275
  signal Opcode              : OPCODE_TYPE := (others => '0');
276
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
277
 
278
  signal Prefetch            : DATA_TYPE   := x"00";
279
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
280
 
281
  signal Instr_Prefetch      : std_logic   := '0';
282
 
283
  signal PC_Ctrl             : PC_CTRL_TYPE;
284
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
285
 
286 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
287
  signal Regfile             : REGFILE_TYPE;
288
  signal Flags               : FLAG_TYPE;
289
  signal Mult                : ADDRESS_TYPE := x"0000";
290
 
291 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
292
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
293
 
294
  signal DP_Ctrl             : DATA_CTRL_TYPE;
295
 
296
  signal INT_Ctrl            : INT_CTRL_TYPE;
297
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
298
  signal Int_Req, Int_Ack    : std_logic   := '0';
299
  signal Int_Mask            : DATA_TYPE   := x"00";
300
  signal ISR_Addr            : ADDRESS_TYPE := x"0000";
301
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
302
  signal Pending             : INTERRUPT_BUNDLE := x"00";
303
  signal Wait_for_FSM        : std_logic := '0';
304 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
305 169 jshamlet
 
306
begin
307
 
308 224 jshamlet
-------------------------------------------------------------------------------
309
-- Reset & uSec Tick
310
-------------------------------------------------------------------------------
311 185 jshamlet
 
312 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
313
  begin
314
    if( PLL_Locked = '0' )then
315
      Reset_q                <= Reset_Level;
316
      Reset                  <= Reset_Level;
317
    elsif( rising_edge(Clock) )then
318
      Reset_q                <= not Reset_Level;
319
      Reset                  <= Reset_q;
320
    end if;
321
  end process;
322
 
323
  uSec_Tick_proc: process( Clock, Reset )
324
  begin
325
    if( Reset = Reset_Level )then
326
      uSec_Cntr              <= USEC_DLY;
327
      uSec_Tick              <= '0';
328
    elsif( rising_edge( Clock ) )then
329
      uSec_Cntr              <= uSec_Cntr - 1;
330
      if( or_reduce(uSec_Cntr) = '0' )then
331
        uSec_Cntr            <= USEC_DLY;
332
      end if;
333
      uSec_Tick              <= nor_reduce(uSec_Cntr);
334
    end if;
335
  end process;
336
 
337
  Open8_Bus.Clock            <= Clock;
338
  Open8_Bus.Reset            <= Reset;
339
  Open8_Bus.uSec_Tick        <= uSec_Tick;
340
 
341 169 jshamlet
-------------------------------------------------------------------------------
342 182 jshamlet
-- Address bus selection/generation logic
343 169 jshamlet
-------------------------------------------------------------------------------
344
 
345 185 jshamlet
  Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1,
346
                         Operand2, Program_Ctr, Stack_Ptr, ISR_Addr )
347 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
348
    variable Offset_SX       : ADDRESS_TYPE;
349
  begin
350 182 jshamlet
 
351
    if( Enable_Auto_Increment )then
352
      Reg                    := conv_integer(SubOp(2 downto 1) & '0');
353
      Reg_1                  := conv_integer(SubOp(2 downto 1) & '1');
354
    else
355
      Reg                    := conv_integer(SubOp);
356
      Reg_1                  := conv_integer(SubOp_p1);
357
    end if;
358
 
359
    Offset_SX(15 downto 0)   := (others => Operand1(7));
360
    Offset_SX(7 downto 0)    := Operand1;
361
 
362
    case( CPU_State )is
363
 
364
      when LDA_C2 | STA_C2 =>
365 223 jshamlet
        Open8_Bus.Address    <= Operand2 & Operand1;
366 182 jshamlet
 
367
      when LDX_C1 | STX_C1 =>
368 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg));
369 182 jshamlet
 
370
      when LDO_C1 | STO_C1 =>
371 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
372 182 jshamlet
 
373
      when ISR_C1 | ISR_C2 =>
374 223 jshamlet
        Open8_Bus.Address    <= ISR_Addr;
375 182 jshamlet
 
376
      when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
377 223 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
378 182 jshamlet
 
379
      when others =>
380 223 jshamlet
        Open8_Bus.Address    <= Program_Ctr;
381 182 jshamlet
 
382
    end case;
383
 
384
  end process;
385
 
386
-------------------------------------------------------------------------------
387
-- Combinatorial portion of CPU finite state machine
388
-- State Logic / Instruction Decoding & Execution
389
-------------------------------------------------------------------------------
390
 
391 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
392 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
393
    variable Reg             : integer range 0 to 7 := 0;
394
  begin
395 169 jshamlet
    CPU_Next_State           <= CPU_State;
396
    Cache_Ctrl               <= CACHE_IDLE;
397
    --
398 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
399
    PC_Ctrl.Offset           <= PC_IDLE;
400 182 jshamlet
    --
401 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
402
    ALU_Ctrl.Reg             <= ACCUM;
403
    --
404
    SP_Ctrl.Oper             <= SP_IDLE;
405
    --
406
    DP_Ctrl.Src              <= DATA_RD_MEM;
407
    DP_Ctrl.Reg              <= ACCUM;
408
    --
409
    INT_Ctrl.Mask_Set        <= '0';
410
    INT_Ctrl.Soft_Ints       <= x"00";
411
    INT_Ctrl.Incr_ISR        <= '0';
412
    Ack_D                    <= '0';
413 225 jshamlet
    --
414 182 jshamlet
    Reg                     := conv_integer(SubOp);
415 225 jshamlet
    --
416
    CPU_Halt_Ack             <= '0';
417 169 jshamlet
 
418
    case CPU_State is
419
-------------------------------------------------------------------------------
420
-- Initial Instruction fetch & decode
421
-------------------------------------------------------------------------------
422 187 jshamlet
      when IPF_C0 =>
423
        CPU_Next_State       <= IPF_C1;
424 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
425 169 jshamlet
 
426 187 jshamlet
      when IPF_C1 =>
427
        CPU_Next_State       <= IPF_C2;
428 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
429 169 jshamlet
 
430 187 jshamlet
      when IPF_C2 =>
431
        CPU_Next_State       <= IDC_C0;
432 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
433 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
434 169 jshamlet
 
435 187 jshamlet
      when IDC_C0 =>
436
        CPU_Next_State       <= IDC_C0;
437 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
438
 
439
        case Opcode is
440
          when OP_PSH =>
441
            CPU_Next_State   <= PSH_C1;
442
            Cache_Ctrl       <= CACHE_PREFETCH;
443 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
444 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
445
            DP_Ctrl.Reg      <= SubOp;
446
 
447
          when OP_POP =>
448
            CPU_Next_State   <= POP_C1;
449
            Cache_Ctrl       <= CACHE_PREFETCH;
450 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
451 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
452
 
453
          when OP_BR0 | OP_BR1 =>
454
            CPU_Next_State   <= BRN_C1;
455
            Cache_Ctrl       <= CACHE_OPER1;
456 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
457 169 jshamlet
 
458 185 jshamlet
 
459 169 jshamlet
          when OP_DBNZ =>
460
            CPU_Next_State   <= DBNZ_C1;
461
            Cache_Ctrl       <= CACHE_OPER1;
462 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
463 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
464
            ALU_Ctrl.Reg     <= SubOp;
465
 
466
          when OP_INT =>
467 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
468 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
469
            --  Also, unlike CPU_Halt, the INT instruction is actually being
470
            --  executed, so go ahead and increment the program counter before
471
            --  pausing so the CPU restarts on the next instruction.
472 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
473 187 jshamlet
              CPU_Next_State <= WAI_Cx;
474 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
475
            end if;
476
 
477
          when OP_STK =>
478
            case SubOp is
479
              when SOP_RSP  =>
480 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
481 181 jshamlet
                if( not Allow_Stack_Address_Move )then
482 187 jshamlet
                  -- The default behavior for this instruction is to simply
483
                  --  repoint the SP to the HDL default
484 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
485 181 jshamlet
                end if;
486 187 jshamlet
                if( Allow_Stack_Address_Move and
487
                    Flags(Stack_Xfer_Flag) = '1' )then
488
                  -- If RSP is set to allow SP moves, and the specified flag
489
                  --  is true, then signal the stack pointer logic to load
490
                  --  from R1:R0
491 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
492 181 jshamlet
                end if;
493 187 jshamlet
                if( Allow_Stack_Address_Move and
494
                    Flags(Stack_Xfer_Flag) = '0')then
495
                  -- If RSP is set to allow SP moves, and the specified flag
496
                  --  is false, then signal the ALU to copy the stack pointer
497
                  --  to R1:R0
498 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
499 181 jshamlet
                end if;
500 169 jshamlet
 
501
              when SOP_RTS | SOP_RTI =>
502 185 jshamlet
                CPU_Next_State    <= RTS_C1;
503 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
504 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
505 169 jshamlet
 
506
              when SOP_BRK  =>
507
                if( BRK_Implements_WAI )then
508 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
509
                  --  increment the PC similar to an ISR flow.
510
                  CPU_Next_State  <= WAI_Cx;
511 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
512 187 jshamlet
                else
513
                -- If Break is implemented normally, back the PC up by
514
                --  2 and return through IPF_C0 in order to execute a 5
515
                --  clock cycle delay
516
                  CPU_Next_State  <= BRK_C1;
517
                  PC_Ctrl.Offset  <= PC_REV2;
518 169 jshamlet
                end if;
519
 
520
              when SOP_JMP  =>
521 185 jshamlet
                CPU_Next_State    <= JMP_C1;
522
                Cache_Ctrl        <= CACHE_OPER1;
523 169 jshamlet
 
524
              when SOP_SMSK =>
525 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
526 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
527
 
528
              when SOP_GMSK =>
529 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
530
                ALU_Ctrl.Oper     <= ALU_GMSK;
531 169 jshamlet
 
532
              when SOP_JSR =>
533
                CPU_Next_State <= JSR_C1;
534 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
535
                DP_Ctrl.Src       <= DATA_WR_PC;
536
                DP_Ctrl.Reg       <= PC_MSB;
537 169 jshamlet
 
538
              when others => null;
539
            end case;
540
 
541
          when OP_MUL =>
542
            CPU_Next_State   <= MUL_C1;
543 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
544
            --  to the ALU writing the result to registers. As a result, this
545
            --  state needs to idle the ALU initially, and back the PC up by 1
546
            -- We can get away with only 1 extra clock by pre-fetching the
547
            --  next instruction, though.
548 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
549 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
550 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
551
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
552
            --  now, but hold off on the ALU command until the next state.
553 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
554
            ALU_Ctrl.Reg     <= SubOp;
555
 
556
          when OP_UPP =>
557
            CPU_Next_State   <= UPP_C1;
558
            Cache_Ctrl       <= CACHE_PREFETCH;
559 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
560 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
561
            ALU_Ctrl.Reg     <= SubOp;
562
 
563
          when OP_LDA =>
564
            CPU_Next_State   <= LDA_C1;
565
            Cache_Ctrl       <= CACHE_OPER1;
566
 
567
          when OP_LDI =>
568
            CPU_Next_State   <= LDI_C1;
569
            Cache_Ctrl       <= CACHE_OPER1;
570 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
571 169 jshamlet
 
572
          when OP_LDO =>
573
            CPU_Next_State   <= LDO_C1;
574
            Cache_Ctrl       <= CACHE_OPER1;
575 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
576 169 jshamlet
 
577
          when OP_LDX =>
578
            CPU_Next_State   <= LDX_C1;
579 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
580 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
581 169 jshamlet
 
582
          when OP_STA =>
583
            CPU_Next_State   <= STA_C1;
584
            Cache_Ctrl       <= CACHE_OPER1;
585
 
586
          when OP_STO =>
587
            CPU_Next_State   <= STO_C1;
588
            Cache_Ctrl       <= CACHE_OPER1;
589 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
590 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
591
            DP_Ctrl.Reg      <= ACCUM;
592
 
593
          when OP_STX =>
594
            CPU_Next_State   <= STX_C1;
595
            Cache_Ctrl       <= CACHE_PREFETCH;
596 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
597 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
598
            DP_Ctrl.Reg      <= ACCUM;
599
 
600
          when others =>
601 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
602 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
603
            ALU_Ctrl.Reg     <= SubOp;
604
 
605
        end case;
606
 
607 186 jshamlet
        if( Int_Req = '1' )then
608
          CPU_Next_State     <= ISR_C1;
609 187 jshamlet
        end if;
610
 
611
        if( CPU_Halt_Req = '1' )then
612
          CPU_Next_State     <= WAH_Cx;
613
        end if;
614
 
615
        -- If either of these override conditions are true, the decoder needs
616
        --  to undo everything it just setup, since even "single-cycle"
617
        --  instructions will be executed again upon return.
618
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
619
          -- In either case, we want to skip loading the cache, as the cache
620
          --  will be invalid by the time we get back.
621 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
622 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
623
          -- compensating for the pipeline registers.
624 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
625
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
626 187 jshamlet
          --  operation due to the current instruction.
627 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
628
          SP_Ctrl.Oper       <= SP_IDLE;
629 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
630
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
631 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
632 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
633
          --  executed again when normal processing resumes, so axe their
634
          --  requests for now.
635
          INT_Ctrl.Mask_Set       <= '0';
636
          INT_Ctrl.Soft_Ints(Reg) <= '0';
637 186 jshamlet
        end if;
638
 
639 169 jshamlet
-------------------------------------------------------------------------------
640
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
641
-------------------------------------------------------------------------------
642
 
643
      when BRN_C1 =>
644 187 jshamlet
        CPU_Next_State       <= IDC_C0;
645 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
646 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
647 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
648 187 jshamlet
          CPU_Next_State     <= IPF_C0;
649 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
650
          PC_Ctrl.Offset     <= Operand1;
651
        end if;
652
 
653
      when DBNZ_C1 =>
654 187 jshamlet
        CPU_Next_State       <= IDC_C0;
655 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
656 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
657
        if( Flags(PSR_Z) = '0' )then
658 187 jshamlet
          CPU_Next_State     <= IPF_C0;
659 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
660
          PC_Ctrl.Offset     <= Operand1;
661
        end if;
662
 
663
      when JMP_C1 =>
664
        CPU_Next_State       <= JMP_C2;
665
        Cache_Ctrl           <= CACHE_OPER2;
666
 
667
      when JMP_C2 =>
668 187 jshamlet
        CPU_Next_State       <= IPF_C0;
669 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
670
 
671
-------------------------------------------------------------------------------
672
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
673
-------------------------------------------------------------------------------
674
 
675
      when LDA_C1 =>
676
        CPU_Next_State       <= LDA_C2;
677
        Cache_Ctrl           <= CACHE_OPER2;
678
 
679
      when LDA_C2 =>
680
        CPU_Next_State       <= LDA_C3;
681
 
682
      when LDA_C3 =>
683
        CPU_Next_State       <= LDA_C4;
684 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
685 169 jshamlet
 
686
      when LDA_C4 =>
687
        CPU_Next_State       <= LDI_C1;
688
        Cache_Ctrl           <= CACHE_OPER1;
689 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
690 169 jshamlet
 
691
      when LDI_C1 =>
692 187 jshamlet
        CPU_Next_State       <= IDC_C0;
693 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
694 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
695 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
696
        ALU_Ctrl.Reg         <= SubOp;
697
 
698
      when LDO_C1 =>
699 181 jshamlet
        CPU_Next_State       <= LDX_C2;
700 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
701 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
702
          ALU_Ctrl.Oper      <= ALU_UPP;
703
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
704 169 jshamlet
        end if;
705
 
706
      when LDX_C1 =>
707
        CPU_Next_State       <= LDX_C2;
708 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
709
          ALU_Ctrl.Oper      <= ALU_UPP;
710
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
711 181 jshamlet
        end if;
712 169 jshamlet
 
713
      when LDX_C2 =>
714
        CPU_Next_State       <= LDX_C3;
715 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
716 181 jshamlet
 
717
      when LDX_C3 =>
718
        CPU_Next_State       <= LDX_C4;
719 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
720 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
721 169 jshamlet
 
722 181 jshamlet
      when LDX_C4 =>
723 187 jshamlet
        CPU_Next_State       <= IDC_C0;
724 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
725 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
726 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
727 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
728
 
729
-------------------------------------------------------------------------------
730
-- Data Storage - Store to memory (STA, STO, STX)
731
-------------------------------------------------------------------------------
732
      when STA_C1 =>
733
        CPU_Next_State       <= STA_C2;
734
        Cache_Ctrl           <= CACHE_OPER2;
735
        DP_Ctrl.Src          <= DATA_WR_REG;
736
        DP_Ctrl.Reg          <= SubOp;
737
 
738
      when STA_C2 =>
739
        CPU_Next_State       <= STA_C3;
740 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
741 169 jshamlet
 
742
      when STA_C3 =>
743 187 jshamlet
        CPU_Next_State       <= IPF_C2;
744 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
745 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
746 169 jshamlet
 
747
      when STO_C1 =>
748 187 jshamlet
        CPU_Next_State       <= IPF_C0;
749 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
750 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
751 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
752
          CPU_Next_State     <= STO_C2;
753
          ALU_Ctrl.Oper      <= ALU_UPP;
754
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
755 169 jshamlet
        end if;
756
 
757
      when STO_C2 =>
758 187 jshamlet
        CPU_Next_State       <= IPF_C1;
759 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
760 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
761
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
762
 
763
      when STX_C1 =>
764 187 jshamlet
        CPU_Next_State       <= IPF_C1;
765 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
766 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
767
          CPU_Next_State     <= STX_C2;
768
          ALU_Ctrl.Oper      <= ALU_UPP;
769
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
770 169 jshamlet
        end if;
771
 
772
      when STX_C2 =>
773 187 jshamlet
        CPU_Next_State       <= IPF_C2;
774 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
775 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
776
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
777
 
778
-------------------------------------------------------------------------------
779
-- Multi-Cycle Math Operations (UPP, MUL)
780
-------------------------------------------------------------------------------
781
 
782
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
783 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
784
      --  need to tell the ALU to store the results to R1:R0 here. Note that
785
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
786 169 jshamlet
      when MUL_C1 =>
787 187 jshamlet
        CPU_Next_State       <= IPF_C2;
788 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
789 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
790
 
791
      when UPP_C1 =>
792 187 jshamlet
        CPU_Next_State       <= IPF_C2;
793 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
794 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
795
        ALU_Ctrl.Reg         <= SubOp_p1;
796
 
797
-------------------------------------------------------------------------------
798
-- Basic Stack Manipulation (PSH, POP, RSP)
799
-------------------------------------------------------------------------------
800
      when PSH_C1 =>
801 187 jshamlet
        CPU_Next_State       <= IPF_C1;
802 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
803
 
804
      when POP_C1 =>
805
        CPU_Next_State       <= POP_C2;
806
 
807
      when POP_C2 =>
808
        CPU_Next_State       <= POP_C3;
809 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
810 169 jshamlet
 
811
      when POP_C3 =>
812
        CPU_Next_State       <= POP_C4;
813
        Cache_Ctrl           <= CACHE_OPER1;
814 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
815 169 jshamlet
 
816
      when POP_C4 =>
817 187 jshamlet
        CPU_Next_State       <= IDC_C0;
818 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
819 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
820 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
821
        ALU_Ctrl.Reg         <= SubOp;
822 172 jshamlet
 
823 169 jshamlet
-------------------------------------------------------------------------------
824
-- Subroutines & Interrupts (RTS, JSR)
825
-------------------------------------------------------------------------------
826 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
827 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
828 186 jshamlet
        if( Int_Req = '1' )then
829
          CPU_Next_State     <= ISR_C1;
830 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
831
          --  instruction, compensating for the pipeline registers.
832 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
833
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
834
          --  operation due to the current instruction
835
          DP_Ctrl.Src        <= DATA_RD_MEM;
836
        end if;
837 169 jshamlet
 
838 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
839 225 jshamlet
        CPU_Halt_Ack         <= '1';
840 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
841
        if( CPU_Halt_Req = '0' )then
842
          CPU_Next_State     <= IPF_C0;
843
          DP_Ctrl.Src        <= DATA_RD_MEM;
844
        end if;
845
 
846
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
847
        CPU_Next_State       <= IPF_C0;
848
 
849 169 jshamlet
      when ISR_C1 =>
850
        CPU_Next_State       <= ISR_C2;
851
        INT_Ctrl.Incr_ISR    <= '1';
852
 
853
      when ISR_C2 =>
854
        CPU_Next_State       <= ISR_C3;
855
        DP_Ctrl.Src          <= DATA_WR_FLAG;
856
 
857
      when ISR_C3 =>
858
        CPU_Next_State       <= JSR_C1;
859
        Cache_Ctrl           <= CACHE_OPER1;
860 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
861 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
862 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
863
        DP_Ctrl.Src          <= DATA_WR_PC;
864 182 jshamlet
        DP_Ctrl.Reg          <= PC_MSB;
865 169 jshamlet
        Ack_D                <= '1';
866
 
867
      when JSR_C1 =>
868
        CPU_Next_State       <= JSR_C2;
869
        Cache_Ctrl           <= CACHE_OPER2;
870
        SP_Ctrl.Oper         <= SP_PUSH;
871
        DP_Ctrl.Src          <= DATA_WR_PC;
872 182 jshamlet
        DP_Ctrl.Reg          <= PC_LSB;
873 169 jshamlet
 
874
      when JSR_C2 =>
875 187 jshamlet
        CPU_Next_State       <= IPF_C0;
876 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
877 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
878 169 jshamlet
 
879
      when RTS_C1 =>
880
        CPU_Next_State       <= RTS_C2;
881
        SP_Ctrl.Oper         <= SP_POP;
882
 
883
      when RTS_C2 =>
884
        CPU_Next_State       <= RTS_C3;
885
        -- if this is an RTI, then we need to POP the flags
886
        if( SubOp = SOP_RTI )then
887
          SP_Ctrl.Oper       <= SP_POP;
888
        end if;
889
 
890
      when RTS_C3 =>
891
        CPU_Next_State       <= RTS_C4;
892
        Cache_Ctrl           <= CACHE_OPER1;
893
 
894
      when RTS_C4 =>
895
        CPU_Next_State       <= RTS_C5;
896
        Cache_Ctrl           <= CACHE_OPER2;
897
 
898
      when RTS_C5 =>
899 187 jshamlet
        CPU_Next_State       <= IPF_C0;
900 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
901 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
902 169 jshamlet
        if( SubOp = SOP_RTI )then
903
          CPU_Next_State     <= RTI_C6;
904
          Cache_Ctrl         <= CACHE_OPER1;
905 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
906
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
907 169 jshamlet
        end if;
908
 
909
      when RTI_C6 =>
910 187 jshamlet
        CPU_Next_State       <= IPF_C1;
911 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
912 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
913
 
914
      when others =>
915
        null;
916
    end case;
917
 
918
  end process;
919
 
920
-------------------------------------------------------------------------------
921
-- Registered portion of CPU finite state machine
922
-------------------------------------------------------------------------------
923 182 jshamlet
 
924 169 jshamlet
  CPU_Regs: process( Reset, Clock )
925
    variable Offset_SX       : ADDRESS_TYPE;
926 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
927 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
928
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
929
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
930
  begin
931
    if( Reset = Reset_Level )then
932 187 jshamlet
      CPU_State              <= IPF_C0;
933 169 jshamlet
      Opcode                 <= OP_INC;
934
      SubOp                  <= ACCUM;
935
      SubOp_p1               <= ACCUM;
936
      Operand1               <= x"00";
937
      Operand2               <= x"00";
938
      Instr_Prefetch         <= '0';
939
      Prefetch               <= x"00";
940
 
941 187 jshamlet
      CPU_Halt_Req           <= '0';
942 225 jshamlet
      Halt_Ack               <= '0';
943 187 jshamlet
 
944 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
945
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
946
      Open8_Bus.Rd_En        <= '1';
947 169 jshamlet
 
948
      Program_Ctr            <= Program_Start_Addr;
949
      Stack_Ptr              <= Stack_Start_Addr;
950
 
951
      Ack_Q                  <= '0';
952
      Ack_Q1                 <= '0';
953
      Int_Ack                <= '0';
954
 
955
      Int_Req                <= '0';
956
      Pending                <= x"00";
957
      Wait_for_FSM           <= '0';
958 210 jshamlet
      Wait_for_ISR           <= '0';
959 169 jshamlet
      if( Enable_NMI )then
960
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
961
      else
962
        Int_Mask             <= Default_Interrupt_Mask;
963
      end if;
964
      ISR_Addr               <= INT_VECTOR_0;
965
 
966
      for i in 0 to 7 loop
967 188 jshamlet
        Regfile(i)           <= x"00";
968 169 jshamlet
      end loop;
969
      Flags                  <= x"00";
970
 
971 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
972 188 jshamlet
 
973 169 jshamlet
    elsif( rising_edge(Clock) )then
974 187 jshamlet
 
975 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
976
      Halt_Ack               <= CPU_Halt_Ack;
977 187 jshamlet
 
978 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
979
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
980
      Open8_Bus.Rd_En        <= '0';
981 169 jshamlet
 
982
-------------------------------------------------------------------------------
983
-- Instruction/Operand caching for pipelined memory access
984
-------------------------------------------------------------------------------
985
      CPU_State              <= CPU_Next_State;
986
      case Cache_Ctrl is
987
        when CACHE_INSTR =>
988
          Opcode             <= Rd_Data(7 downto 3);
989
          SubOp              <= Rd_Data(2 downto 0);
990
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
991
          if( Instr_Prefetch = '1' )then
992
            Opcode           <= Prefetch(7 downto 3);
993
            SubOp            <= Prefetch(2 downto 0);
994
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
995
            Instr_Prefetch   <= '0';
996
          end if;
997
 
998
        when CACHE_OPER1 =>
999
          Operand1           <= Rd_Data;
1000
 
1001
        when CACHE_OPER2 =>
1002
          Operand2           <= Rd_Data;
1003
 
1004
        when CACHE_PREFETCH =>
1005
          Prefetch           <= Rd_Data;
1006
          Instr_Prefetch     <= '1';
1007
 
1008
        when CACHE_IDLE =>
1009
          null;
1010
      end case;
1011
 
1012
-------------------------------------------------------------------------------
1013
-- Program Counter
1014
-------------------------------------------------------------------------------
1015
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1016
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1017
 
1018
      case PC_Ctrl.Oper is
1019
        when PC_INCR =>
1020
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1021
 
1022
        when PC_LOAD =>
1023 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1024 169 jshamlet
 
1025
        when others =>
1026
          null;
1027
      end case;
1028
 
1029
-------------------------------------------------------------------------------
1030
-- (Write) Data Path
1031
-------------------------------------------------------------------------------
1032
      case DP_Ctrl.Src is
1033
        when DATA_BUS_IDLE =>
1034
          null;
1035
 
1036
        when DATA_RD_MEM =>
1037 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1038 169 jshamlet
 
1039
        when DATA_WR_REG =>
1040 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1041
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1042 169 jshamlet
 
1043
        when DATA_WR_FLAG =>
1044 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1045
          Open8_Bus.Wr_Data  <= Flags;
1046 169 jshamlet
 
1047
        when DATA_WR_PC =>
1048 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1049
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1050 182 jshamlet
          if( DP_Ctrl.Reg = PC_LSB )then
1051 223 jshamlet
            Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
1052 169 jshamlet
          end if;
1053
 
1054
        when others =>
1055
          null;
1056
      end case;
1057
 
1058
-------------------------------------------------------------------------------
1059
-- Stack Pointer
1060
-------------------------------------------------------------------------------
1061
      case SP_Ctrl.Oper is
1062
        when SP_IDLE =>
1063
          null;
1064
 
1065 181 jshamlet
        when SP_CLR =>
1066 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1067
 
1068 181 jshamlet
        when SP_SET =>
1069
          Stack_Ptr          <= Regfile(1) & Regfile(0);
1070
 
1071 169 jshamlet
        when SP_POP  =>
1072
          Stack_Ptr          <= Stack_Ptr + 1;
1073
 
1074
        when SP_PUSH =>
1075
          Stack_Ptr          <= Stack_Ptr - 1;
1076
 
1077
        when others =>
1078
          null;
1079
 
1080
      end case;
1081
 
1082
-------------------------------------------------------------------------------
1083
-- Interrupt Controller
1084
-------------------------------------------------------------------------------
1085
      -- The interrupt control mask is always sourced out of R0
1086
      if( INT_Ctrl.Mask_Set = '1' )then
1087
        if( Enable_NMI )then
1088
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1089
        else
1090
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1091
        end if;
1092
      end if;
1093
 
1094
      -- Combine external and internal interrupts, and mask the OR of the two
1095
      --  with the mask. Record any incoming interrupts to the pending buffer
1096
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1097
                                Int_Mask;
1098 172 jshamlet
 
1099 169 jshamlet
      Pending                <= i_Ints or Pending;
1100
 
1101 210 jshamlet
      if( Sequential_Interrupts )then
1102
        Wait_for_ISR         <= Flags(PSR_I);
1103
      else
1104
        Wait_for_ISR         <= '0';
1105
      end if;
1106
 
1107
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1108 169 jshamlet
        if(    Pending(0) = '1' )then
1109
          ISR_Addr           <= INT_VECTOR_0;
1110
          Pending(0)         <= '0';
1111
        elsif( Pending(1) = '1' )then
1112
          ISR_Addr           <= INT_VECTOR_1;
1113
          Pending(1)         <= '0';
1114
        elsif( Pending(2) = '1' )then
1115
          ISR_Addr           <= INT_VECTOR_2;
1116
          Pending(2)         <= '0';
1117
        elsif( Pending(3) = '1' )then
1118
          ISR_Addr           <= INT_VECTOR_3;
1119
          Pending(3)         <= '0';
1120
        elsif( Pending(4) = '1' )then
1121
          ISR_Addr           <= INT_VECTOR_4;
1122
          Pending(4)         <= '0';
1123
        elsif( Pending(5) = '1' )then
1124
          ISR_Addr           <= INT_VECTOR_5;
1125
          Pending(5)         <= '0';
1126
        elsif( Pending(6) = '1' )then
1127
          ISR_Addr           <= INT_VECTOR_6;
1128
          Pending(6)         <= '0';
1129
        elsif( Pending(7) = '1' )then
1130
          ISR_Addr           <= INT_VECTOR_7;
1131
          Pending(7)         <= '0';
1132
        end if;
1133 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1134 169 jshamlet
      end if;
1135
 
1136
      -- Reset the Wait_for_FSM flag on Int_Ack
1137
      Ack_Q                  <= Ack_D;
1138
      Ack_Q1                 <= Ack_Q;
1139
      Int_Ack                <= Ack_Q1;
1140
      if( Int_Ack = '1' )then
1141
        Wait_for_FSM         <= '0';
1142
      end if;
1143
 
1144
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1145
 
1146
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1147
      --  lower half of the address.
1148
      if( INT_Ctrl.Incr_ISR = '1' )then
1149
        ISR_Addr             <= ISR_Addr + 1;
1150
      end if;
1151
 
1152
-------------------------------------------------------------------------------
1153
-- ALU (Arithmetic / Logic Unit)
1154
-------------------------------------------------------------------------------
1155
      Index                  := conv_integer(ALU_Ctrl.Reg);
1156
      Sum                    := (others => '0');
1157
      Temp                   := (others => '0');
1158
 
1159
      case ALU_Ctrl.Oper is
1160
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1161
          Sum                := ("0" & x"01") +
1162
                                ("0" & Regfile(Index));
1163 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1164
          Flags(PSR_C)       <= Sum(8);
1165 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1166 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1167
 
1168
        when ALU_UPP => -- Rn = Rn + 1
1169
          Sum                := ("0" & x"01") +
1170
                                ("0" & Regfile(Index));
1171 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1172 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1173
 
1174
        when ALU_UPP2 => -- Rn = Rn + C
1175
          Sum                := ("0" & x"00") +
1176
                                ("0" & Regfile(Index)) +
1177 185 jshamlet
                                Flags(PSR_C);
1178
          Flags(PSR_C)       <= Sum(8);
1179 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1180
 
1181
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1182
          Sum                := ("0" & Regfile(0)) +
1183
                                ("0" & Regfile(Index)) +
1184 185 jshamlet
                                Flags(PSR_C);
1185
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1186
          Flags(PSR_C)       <= Sum(8);
1187
          Flags(PSR_N)       <= Sum(7);
1188 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1189
 
1190
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1191
          Temp               := "0" & Regfile(Index);
1192 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1193
          Flags(PSR_N)       <= Temp(7);
1194 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1195
 
1196
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1197
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1198 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1199
          Flags(PSR_N)       <= Temp(7);
1200 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1201
 
1202
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1203
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1204 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1205
          Flags(PSR_N)       <= Temp(7);
1206 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1207
 
1208
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1209
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1210 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1211
          Flags(PSR_N)       <= Temp(7);
1212 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1213
 
1214
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1215 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1216
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1217
          Flags(PSR_C)       <= Temp(8);
1218
          Flags(PSR_N)       <= Temp(7);
1219 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1220
 
1221
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1222 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1223 169 jshamlet
                                Regfile(Index)(7 downto 1);
1224 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1225
          Flags(PSR_C)       <= Temp(8);
1226
          Flags(PSR_N)       <= Temp(7);
1227 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1228
 
1229
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1230
          Sum                := ("0" & Regfile(Index)) +
1231
                                ("0" & x"FF");
1232 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1233
          Flags(PSR_C)       <= Sum(8);
1234
          Flags(PSR_N)       <= Sum(7);
1235 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1236
 
1237
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1238
          Sum                := ("0" & Regfile(0)) +
1239
                                ("1" & (not Regfile(Index))) +
1240 185 jshamlet
                                Flags(PSR_C);
1241
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1242
          Flags(PSR_C)       <= Sum(8);
1243
          Flags(PSR_N)       <= Sum(7);
1244 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1245
 
1246
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1247
          Sum                := ("0" & Regfile(0)) +
1248
                                ("0" & Regfile(Index));
1249 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1250 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1251 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1252
          Flags(PSR_N)       <= Sum(7);
1253 169 jshamlet
 
1254
        when ALU_STP => -- Sets bit(n) in the Flags register
1255
          Flags(Index)       <= '1';
1256
 
1257
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1258 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1259
          Flags(PSR_N)       <= Regfile(0)(7);
1260 169 jshamlet
 
1261
        when ALU_CLP => -- Clears bit(n) in the Flags register
1262
          Flags(Index)       <= '0';
1263
 
1264
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1265
          Temp               := "0" & Regfile(0);
1266 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1267
          Flags(PSR_N)       <= Temp(7);
1268 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1269
 
1270
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1271
          Sum                := ("0" & Regfile(0)) +
1272
                                ("1" & (not Regfile(Index))) +
1273
                                '1';
1274 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1275
          Flags(PSR_C)       <= Sum(8);
1276
          Flags(PSR_N)       <= Sum(7);
1277 169 jshamlet
 
1278
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1279
          Regfile(0)         <= Mult(7 downto 0);
1280
          Regfile(1)         <= Mult(15 downto 8);
1281 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1282 169 jshamlet
 
1283
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1284 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1285
          Flags(PSR_N)       <= Operand1(7);
1286
          Regfile(Index)     <= Operand1;
1287 169 jshamlet
 
1288
        when ALU_POP => -- Rn <= Data
1289 185 jshamlet
          Regfile(Index)     <= Operand1;
1290 169 jshamlet
 
1291
        when ALU_RFLG =>
1292 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1293
          if( not RTI_Ignores_GP_Flags )then
1294
            Flags(7 downto 4)<= Operand1(7 downto 4);
1295
          end if;
1296 169 jshamlet
 
1297 185 jshamlet
        when ALU_RSP =>
1298 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1299
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1300
 
1301 185 jshamlet
        when ALU_GMSK =>
1302
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1303
          Regfile(0)         <= Int_Mask;
1304
 
1305 169 jshamlet
        when others =>
1306
          null;
1307
      end case;
1308
 
1309 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1310 188 jshamlet
 
1311 169 jshamlet
    end if;
1312
  end process;
1313
 
1314 182 jshamlet
-------------------------------------------------------------------------------
1315
-- Multiplier Logic
1316
--
1317
-- We need to infer a hardware multipler, so we create a special clocked
1318
--  process with no reset or clock enable
1319
-------------------------------------------------------------------------------
1320
 
1321
  Multiplier_proc: process( Clock )
1322
  begin
1323
    if( rising_edge(Clock) )then
1324
      Mult                   <= Regfile(0) *
1325 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1326
    end if;
1327
  end process;
1328
 
1329
end architecture;

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