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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
2 169 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
24 181 jshamlet
-- VHDL Units :  o8_cpu
25 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44
--            :   specified by Stack_Xfer_Flag. If the flag is '0', RSP will
45
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 181 jshamlet
--            :  Stack_Xfer_Flag instructs the core to use the specified ALU
52
--            :   flag to alter the behavior of the RSP instruction when
53
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it is ignored.
54
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
74
--            :   after an interrupt. By default, all of the flag bits are put
75
--            :   back to their original state. If this flag is set true, only
76
--            :   the lower four bits are restored, allowing ISR code to alter
77
--            :   the GP flags persistently.
78
--            :
79 244 jshamlet
--            :  Supervisor_Mode, when set, disables the STP PSR_I instruction
80
--            :   preventing code from setting the I bit. When enabled, only
81
--            :   interrupts can set the I bit, allowing for more robust memory
82
--            :   protection by preventing errant code execution from
83
--            :   inadvertently entering an interrupt state.
84
--            :
85
--            :  Default_Int_Flag allows the initial state of the I bit to be
86
--            :   set at startup. If set, initialization code may be run in an
87
--            :   ISR context, disabling memory protection initially. Init code
88
--            :   should clear the I bit when done;
89
--            :
90 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
91
--            :   interrupt mask. To remain true to the original core, which
92
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
93
--            :   it can be initialized to any value. Note that Enable_NMI
94
--            :   will logically force the LSB high.
95 172 jshamlet
--            :
96 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
97
--            :   on a high or low level from higher logic.
98
--            :
99
--            : Architecture notes
100
--            :  This model deviates from the original ISA in a few important
101
--            :   ways.
102
--            :
103
--            :  First, there is only one set of registers. Interrupt service
104
--            :   routines must explicitely preserve context since the the
105
--            :   hardware doesn't. This was done to decrease size and code
106
--            :   complexity. Older code that assumes this behavior will not
107
--            :   execute correctly on this processor model.
108
--            :
109
--            :  Second, this model adds an additional pipeline stage between
110
--            :   the instruction decoder and the ALU. Unfortunately, this
111
--            :   means that the instruction stream has to be restarted after
112
--            :   any math instruction is executed, implying that any ALU
113
--            :   instruction now has a latency of 2 instead of 0. The
114
--            :   advantage is that the maximum frequency has gone up
115
--            :   significantly, as the ALU code is vastly more efficient.
116
--            :   As an aside, this now means that all math instructions,
117
--            :   including MUL (see below) and UPP have the same instruction
118
--            :   latency.
119
--            :
120
--            :  Third, the original ISA, also a soft core, had two reserved
121
--            :   instructions, USR and USR2. These have been implemented as
122
--            :   DBNZ, and MUL respectively.
123
--            :
124
--            :  DBNZ decrements the specified register and branches if the
125
--            :   result is non-zero. The instruction effectively executes a
126
--            :   DEC Rn instruction prior to branching, so the same flags will
127
--            :   be set.
128
--            :
129
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
130
--            :   latency is identical to other ALU instructions. Only the Z
131
--            :   flag is set, since there is no defined overflow or "negative
132
--            :   16-bit values"
133
--            :
134
--            :  Fourth, indexed load/store instructions now have an (optional)
135
--            :   ability to post-increment their index registers. If enabled,
136
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
137
--            :   register pair to be incremented after the storage access.
138
--            :
139
--            :  Fifth, the RSP instruction has been (optionally) altered to
140
--            :   allow the stack pointer to be sourced from R1:R0.
141
--            :
142
--            :  Sixth, the BRK instruction can optionally implement a WAI,
143
--            :   which is the same as the INT instruction without the soft
144
--            :   interrupt, as a way to put the processor to "sleep" until the
145
--            :   next external interrupt.
146
--            :
147
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
148
--            :   with priority. This model has the same 8 interrupts, but
149 172 jshamlet
--            :   allows software to mask them (with an additional option to
150 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
151
--            :
152
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
153
--            :   were repurposed to support a new interrupt mask.
154
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
155
--            :   to/from the interrupt mask register. SMSK is immediate, while
156
--            :   GMSK has the same overhead as a math instruction.
157
--
158
-- Revision History
159
-- Author          Date     Change
160
------------------ -------- ---------------------------------------------------
161
-- Seth Henry      07/19/06 Design Start
162
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
163
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
164
--                           corruption issues.
165
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
166
--                           path sections.
167
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
168
--                           single entity.
169
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
170
--                           processor to wait for an interrupt instead of the
171
--                           normal BRK behavior.
172 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
173 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
174
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
175
--                           faster logic that simply does priority encoding.
176
-- Seth Henry      08/06/13 Removed HALT functionality
177
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
178 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
179 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
180
--                           allowing true backup/restore of the stack pointer
181 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
182
--                           in order to simplify things and eliminate
183
--                           redundancies. Came across and fixed a problem with
184
--                           the STO instruction when Enable_Auto_Increment is
185
--                           NOT set.
186 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
187
--                           the assembler names. Also fixed an issue where
188
--                           the I bit wasn't being cleared after interrupts.
189
--                          Simplified the program counter logic to only use
190
--                           the offset for increments, redefining the
191
--                           original modes as fixed offset values.
192
--                          Modified the ALU section with a new ALU operation
193
--                           for GMSK. This allowed the .data field to be
194
--                           removed and Operand1 used in its place, which
195
--                           simplified the logic a great deal.
196 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
197
--                           the instruction decode state, where it acts as a
198
--                           modified form of the BRK instruction that holds
199
--                           state until CPU_Halt is deasserted. This has a
200
--                           much smaller impact on Fmax/complexity than the
201
--                           original clock enable, but imposes a mild impact
202
--                           due to the need to reset the instruction pipeline
203 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
204
--                           the flags, including the general purpose ones, or
205
--                           only the core ALU flags (Z, N, and C). Also
206
--                           brought out copies of the GP flags for external
207
--                           connection.
208 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
209
--                           while the I bit is set to avoid reentering ISRs
210
--                           This may slightly affect timing, as this will
211
--                           potentially block higher priority interrupts
212
--                           until the lower priority ISR returns or clears
213
--                           the I bit.
214
--                          Also added the I bit to the exported flags for
215
--                           use in memory protection schemes.
216 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
217 225 jshamlet
--                           reset and usec_tick logic to drive utility
218
--                           signals. Also added Halt_Ack output.
219 244 jshamlet
-- Seth Henry      05/20/20 Added two new generics to alter the way the I bit
220
--                           is handled. The Supervisor_Mode setting disables
221
--                           STP PSR_I from being executed, preventing it
222
--                           from being set outside of an ISR. The
223
--                           Default_Int_Flag setting allows the I bit to
224
--                           start set so that initialization code can run,
225
--                           but not be hijacked later to corrupt any memory
226
--                           write protection later.
227 245 jshamlet
-- Seth Henry      05/21/20 Supervisor_Mode now protects the interrupt mask
228
--                           and stack pointer as well.
229 169 jshamlet
 
230
library ieee;
231
  use ieee.std_logic_1164.all;
232
  use ieee.std_logic_unsigned.all;
233
  use ieee.std_logic_arith.all;
234
  use ieee.std_logic_misc.all;
235
 
236
library work;
237 227 jshamlet
  use work.Open8_pkg.all;
238 169 jshamlet
 
239 183 jshamlet
entity o8_cpu is
240 169 jshamlet
  generic(
241
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
242
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
243
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
244
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
245 188 jshamlet
    Stack_Xfer_Flag          : integer      := PSR_GP4; -- GP4 modifies RSP
246 169 jshamlet
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
247
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
248
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
249 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
250 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
251 244 jshamlet
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
252
    Default_Int_Flag         : boolean      := false;   -- Start with I bit set
253 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
254 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
255
);
256 169 jshamlet
  port(
257
    Clock                    : in  std_logic;
258 224 jshamlet
    PLL_Locked               : in  std_logic;
259 169 jshamlet
    --
260 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
261
    Halt_Ack                 : out std_logic;
262
    --
263 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
264 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
265 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
266
);
267 169 jshamlet
end entity;
268
 
269 183 jshamlet
architecture behave of o8_cpu is
270 169 jshamlet
 
271 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
272
  signal Reset               : std_logic := Reset_Level;
273
 
274
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
275
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
276
  constant USEC_DLY          : std_logic_vector :=
277
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
278
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
279
  signal uSec_Tick           : std_logic;
280
 
281 169 jshamlet
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;
282
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;
283
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;
284
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;
285
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;
286
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;
287
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;
288
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;
289
 
290 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
291
  signal CPU_State           : CPU_STATES := IPF_C0;
292 169 jshamlet
 
293 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
294
  signal CPU_Halt_Ack        : std_logic := '0';
295 187 jshamlet
 
296 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
297
 
298
  signal Opcode              : OPCODE_TYPE := (others => '0');
299
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
300
 
301
  signal Prefetch            : DATA_TYPE   := x"00";
302
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
303
 
304
  signal Instr_Prefetch      : std_logic   := '0';
305
 
306
  signal PC_Ctrl             : PC_CTRL_TYPE;
307
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
308
 
309 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
310
  signal Regfile             : REGFILE_TYPE;
311
  signal Flags               : FLAG_TYPE;
312
  signal Mult                : ADDRESS_TYPE := x"0000";
313
 
314 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
315
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
316
 
317
  signal DP_Ctrl             : DATA_CTRL_TYPE;
318
 
319
  signal INT_Ctrl            : INT_CTRL_TYPE;
320
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
321
  signal Int_Req, Int_Ack    : std_logic   := '0';
322 245 jshamlet
  signal Set_Mask            : std_logic   := '0';
323 169 jshamlet
  signal Int_Mask            : DATA_TYPE   := x"00";
324
  signal ISR_Addr            : ADDRESS_TYPE := x"0000";
325
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
326
  signal Pending             : INTERRUPT_BUNDLE := x"00";
327
  signal Wait_for_FSM        : std_logic := '0';
328 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
329 169 jshamlet
 
330
begin
331
 
332 224 jshamlet
-------------------------------------------------------------------------------
333
-- Reset & uSec Tick
334
-------------------------------------------------------------------------------
335 185 jshamlet
 
336 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
337
  begin
338
    if( PLL_Locked = '0' )then
339
      Reset_q                <= Reset_Level;
340
      Reset                  <= Reset_Level;
341
    elsif( rising_edge(Clock) )then
342
      Reset_q                <= not Reset_Level;
343
      Reset                  <= Reset_q;
344
    end if;
345
  end process;
346
 
347
  uSec_Tick_proc: process( Clock, Reset )
348
  begin
349
    if( Reset = Reset_Level )then
350
      uSec_Cntr              <= USEC_DLY;
351
      uSec_Tick              <= '0';
352
    elsif( rising_edge( Clock ) )then
353
      uSec_Cntr              <= uSec_Cntr - 1;
354
      if( or_reduce(uSec_Cntr) = '0' )then
355
        uSec_Cntr            <= USEC_DLY;
356
      end if;
357
      uSec_Tick              <= nor_reduce(uSec_Cntr);
358
    end if;
359
  end process;
360
 
361
  Open8_Bus.Clock            <= Clock;
362
  Open8_Bus.Reset            <= Reset;
363
  Open8_Bus.uSec_Tick        <= uSec_Tick;
364
 
365 169 jshamlet
-------------------------------------------------------------------------------
366 182 jshamlet
-- Address bus selection/generation logic
367 169 jshamlet
-------------------------------------------------------------------------------
368
 
369 185 jshamlet
  Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1,
370
                         Operand2, Program_Ctr, Stack_Ptr, ISR_Addr )
371 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
372
    variable Offset_SX       : ADDRESS_TYPE;
373
  begin
374 182 jshamlet
 
375
    if( Enable_Auto_Increment )then
376
      Reg                    := conv_integer(SubOp(2 downto 1) & '0');
377
      Reg_1                  := conv_integer(SubOp(2 downto 1) & '1');
378
    else
379
      Reg                    := conv_integer(SubOp);
380
      Reg_1                  := conv_integer(SubOp_p1);
381
    end if;
382
 
383
    Offset_SX(15 downto 0)   := (others => Operand1(7));
384
    Offset_SX(7 downto 0)    := Operand1;
385
 
386
    case( CPU_State )is
387
 
388
      when LDA_C2 | STA_C2 =>
389 223 jshamlet
        Open8_Bus.Address    <= Operand2 & Operand1;
390 182 jshamlet
 
391
      when LDX_C1 | STX_C1 =>
392 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg));
393 182 jshamlet
 
394
      when LDO_C1 | STO_C1 =>
395 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
396 182 jshamlet
 
397
      when ISR_C1 | ISR_C2 =>
398 223 jshamlet
        Open8_Bus.Address    <= ISR_Addr;
399 182 jshamlet
 
400
      when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
401 223 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
402 182 jshamlet
 
403
      when others =>
404 223 jshamlet
        Open8_Bus.Address    <= Program_Ctr;
405 182 jshamlet
 
406
    end case;
407
 
408
  end process;
409
 
410
-------------------------------------------------------------------------------
411
-- Combinatorial portion of CPU finite state machine
412
-- State Logic / Instruction Decoding & Execution
413
-------------------------------------------------------------------------------
414
 
415 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
416 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
417
    variable Reg             : integer range 0 to 7 := 0;
418
  begin
419 169 jshamlet
    CPU_Next_State           <= CPU_State;
420
    Cache_Ctrl               <= CACHE_IDLE;
421
    --
422 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
423
    PC_Ctrl.Offset           <= PC_IDLE;
424 182 jshamlet
    --
425 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
426
    ALU_Ctrl.Reg             <= ACCUM;
427
    --
428
    SP_Ctrl.Oper             <= SP_IDLE;
429
    --
430
    DP_Ctrl.Src              <= DATA_RD_MEM;
431
    DP_Ctrl.Reg              <= ACCUM;
432
    --
433
    INT_Ctrl.Mask_Set        <= '0';
434
    INT_Ctrl.Soft_Ints       <= x"00";
435
    INT_Ctrl.Incr_ISR        <= '0';
436
    Ack_D                    <= '0';
437 225 jshamlet
    --
438 182 jshamlet
    Reg                     := conv_integer(SubOp);
439 225 jshamlet
    --
440
    CPU_Halt_Ack             <= '0';
441 169 jshamlet
 
442
    case CPU_State is
443
-------------------------------------------------------------------------------
444
-- Initial Instruction fetch & decode
445
-------------------------------------------------------------------------------
446 187 jshamlet
      when IPF_C0 =>
447
        CPU_Next_State       <= IPF_C1;
448 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
449 169 jshamlet
 
450 187 jshamlet
      when IPF_C1 =>
451
        CPU_Next_State       <= IPF_C2;
452 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
453 169 jshamlet
 
454 187 jshamlet
      when IPF_C2 =>
455
        CPU_Next_State       <= IDC_C0;
456 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
457 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
458 169 jshamlet
 
459 187 jshamlet
      when IDC_C0 =>
460
        CPU_Next_State       <= IDC_C0;
461 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
462
 
463
        case Opcode is
464
          when OP_PSH =>
465
            CPU_Next_State   <= PSH_C1;
466
            Cache_Ctrl       <= CACHE_PREFETCH;
467 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
468 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
469
            DP_Ctrl.Reg      <= SubOp;
470
 
471
          when OP_POP =>
472
            CPU_Next_State   <= POP_C1;
473
            Cache_Ctrl       <= CACHE_PREFETCH;
474 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
475 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
476
 
477
          when OP_BR0 | OP_BR1 =>
478
            CPU_Next_State   <= BRN_C1;
479
            Cache_Ctrl       <= CACHE_OPER1;
480 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
481 169 jshamlet
 
482 185 jshamlet
 
483 169 jshamlet
          when OP_DBNZ =>
484
            CPU_Next_State   <= DBNZ_C1;
485
            Cache_Ctrl       <= CACHE_OPER1;
486 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
487 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
488
            ALU_Ctrl.Reg     <= SubOp;
489
 
490
          when OP_INT =>
491 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
492 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
493
            --  Also, unlike CPU_Halt, the INT instruction is actually being
494
            --  executed, so go ahead and increment the program counter before
495
            --  pausing so the CPU restarts on the next instruction.
496 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
497 187 jshamlet
              CPU_Next_State <= WAI_Cx;
498 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
499
            end if;
500
 
501
          when OP_STK =>
502
            case SubOp is
503
              when SOP_RSP  =>
504 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
505 181 jshamlet
                if( not Allow_Stack_Address_Move )then
506 187 jshamlet
                  -- The default behavior for this instruction is to simply
507
                  --  repoint the SP to the HDL default
508 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
509 181 jshamlet
                end if;
510 187 jshamlet
                if( Allow_Stack_Address_Move and
511
                    Flags(Stack_Xfer_Flag) = '1' )then
512
                  -- If RSP is set to allow SP moves, and the specified flag
513
                  --  is true, then signal the stack pointer logic to load
514
                  --  from R1:R0
515 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
516 181 jshamlet
                end if;
517 187 jshamlet
                if( Allow_Stack_Address_Move and
518
                    Flags(Stack_Xfer_Flag) = '0')then
519
                  -- If RSP is set to allow SP moves, and the specified flag
520
                  --  is false, then signal the ALU to copy the stack pointer
521
                  --  to R1:R0
522 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
523 181 jshamlet
                end if;
524 169 jshamlet
 
525
              when SOP_RTS | SOP_RTI =>
526 185 jshamlet
                CPU_Next_State    <= RTS_C1;
527 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
528 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
529 169 jshamlet
 
530
              when SOP_BRK  =>
531
                if( BRK_Implements_WAI )then
532 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
533
                  --  increment the PC similar to an ISR flow.
534
                  CPU_Next_State  <= WAI_Cx;
535 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
536 187 jshamlet
                else
537
                -- If Break is implemented normally, back the PC up by
538
                --  2 and return through IPF_C0 in order to execute a 5
539
                --  clock cycle delay
540
                  CPU_Next_State  <= BRK_C1;
541
                  PC_Ctrl.Offset  <= PC_REV2;
542 169 jshamlet
                end if;
543
 
544
              when SOP_JMP  =>
545 185 jshamlet
                CPU_Next_State    <= JMP_C1;
546
                Cache_Ctrl        <= CACHE_OPER1;
547 169 jshamlet
 
548
              when SOP_SMSK =>
549 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
550 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
551
 
552
              when SOP_GMSK =>
553 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
554
                ALU_Ctrl.Oper     <= ALU_GMSK;
555 169 jshamlet
 
556
              when SOP_JSR =>
557
                CPU_Next_State <= JSR_C1;
558 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
559
                DP_Ctrl.Src       <= DATA_WR_PC;
560
                DP_Ctrl.Reg       <= PC_MSB;
561 169 jshamlet
 
562
              when others => null;
563
            end case;
564
 
565
          when OP_MUL =>
566
            CPU_Next_State   <= MUL_C1;
567 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
568
            --  to the ALU writing the result to registers. As a result, this
569
            --  state needs to idle the ALU initially, and back the PC up by 1
570
            -- We can get away with only 1 extra clock by pre-fetching the
571
            --  next instruction, though.
572 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
573 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
574 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
575
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
576
            --  now, but hold off on the ALU command until the next state.
577 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
578
            ALU_Ctrl.Reg     <= SubOp;
579
 
580
          when OP_UPP =>
581
            CPU_Next_State   <= UPP_C1;
582
            Cache_Ctrl       <= CACHE_PREFETCH;
583 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
584 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
585
            ALU_Ctrl.Reg     <= SubOp;
586
 
587
          when OP_LDA =>
588
            CPU_Next_State   <= LDA_C1;
589
            Cache_Ctrl       <= CACHE_OPER1;
590
 
591
          when OP_LDI =>
592
            CPU_Next_State   <= LDI_C1;
593
            Cache_Ctrl       <= CACHE_OPER1;
594 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
595 169 jshamlet
 
596
          when OP_LDO =>
597
            CPU_Next_State   <= LDO_C1;
598
            Cache_Ctrl       <= CACHE_OPER1;
599 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
600 169 jshamlet
 
601
          when OP_LDX =>
602
            CPU_Next_State   <= LDX_C1;
603 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
604 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
605 169 jshamlet
 
606
          when OP_STA =>
607
            CPU_Next_State   <= STA_C1;
608
            Cache_Ctrl       <= CACHE_OPER1;
609
 
610
          when OP_STO =>
611
            CPU_Next_State   <= STO_C1;
612
            Cache_Ctrl       <= CACHE_OPER1;
613 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
614 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
615
            DP_Ctrl.Reg      <= ACCUM;
616
 
617
          when OP_STX =>
618
            CPU_Next_State   <= STX_C1;
619
            Cache_Ctrl       <= CACHE_PREFETCH;
620 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
621 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
622
            DP_Ctrl.Reg      <= ACCUM;
623
 
624 244 jshamlet
          when OP_STP =>
625
            PC_Ctrl.Offset   <= PC_NEXT;
626
            if( Supervisor_Mode )then
627
              if( SubOp /= PSR_I )then
628
                ALU_Ctrl.Oper  <= Opcode;
629
                ALU_Ctrl.Reg   <= SubOp;
630
              end if;
631
            else
632
              ALU_Ctrl.Oper  <= Opcode;
633
              ALU_Ctrl.Reg   <= SubOp;
634
            end if;
635
 
636 169 jshamlet
          when others =>
637 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
638 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
639
            ALU_Ctrl.Reg     <= SubOp;
640
 
641
        end case;
642
 
643 186 jshamlet
        if( Int_Req = '1' )then
644
          CPU_Next_State     <= ISR_C1;
645 187 jshamlet
        end if;
646
 
647
        if( CPU_Halt_Req = '1' )then
648
          CPU_Next_State     <= WAH_Cx;
649
        end if;
650
 
651
        -- If either of these override conditions are true, the decoder needs
652
        --  to undo everything it just setup, since even "single-cycle"
653
        --  instructions will be executed again upon return.
654
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
655
          -- In either case, we want to skip loading the cache, as the cache
656
          --  will be invalid by the time we get back.
657 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
658 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
659
          -- compensating for the pipeline registers.
660 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
661
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
662 187 jshamlet
          --  operation due to the current instruction.
663 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
664
          SP_Ctrl.Oper       <= SP_IDLE;
665 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
666
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
667 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
668 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
669
          --  executed again when normal processing resumes, so axe their
670
          --  requests for now.
671
          INT_Ctrl.Mask_Set       <= '0';
672
          INT_Ctrl.Soft_Ints(Reg) <= '0';
673 186 jshamlet
        end if;
674
 
675 169 jshamlet
-------------------------------------------------------------------------------
676
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
677
-------------------------------------------------------------------------------
678
 
679
      when BRN_C1 =>
680 187 jshamlet
        CPU_Next_State       <= IDC_C0;
681 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
682 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
683 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
684 187 jshamlet
          CPU_Next_State     <= IPF_C0;
685 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
686
          PC_Ctrl.Offset     <= Operand1;
687
        end if;
688
 
689
      when DBNZ_C1 =>
690 187 jshamlet
        CPU_Next_State       <= IDC_C0;
691 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
692 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
693
        if( Flags(PSR_Z) = '0' )then
694 187 jshamlet
          CPU_Next_State     <= IPF_C0;
695 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
696
          PC_Ctrl.Offset     <= Operand1;
697
        end if;
698
 
699
      when JMP_C1 =>
700
        CPU_Next_State       <= JMP_C2;
701
        Cache_Ctrl           <= CACHE_OPER2;
702
 
703
      when JMP_C2 =>
704 187 jshamlet
        CPU_Next_State       <= IPF_C0;
705 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
706
 
707
-------------------------------------------------------------------------------
708
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
709
-------------------------------------------------------------------------------
710
 
711
      when LDA_C1 =>
712
        CPU_Next_State       <= LDA_C2;
713
        Cache_Ctrl           <= CACHE_OPER2;
714
 
715
      when LDA_C2 =>
716
        CPU_Next_State       <= LDA_C3;
717
 
718
      when LDA_C3 =>
719
        CPU_Next_State       <= LDA_C4;
720 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
721 169 jshamlet
 
722
      when LDA_C4 =>
723
        CPU_Next_State       <= LDI_C1;
724
        Cache_Ctrl           <= CACHE_OPER1;
725 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
726 169 jshamlet
 
727
      when LDI_C1 =>
728 187 jshamlet
        CPU_Next_State       <= IDC_C0;
729 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
730 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
731 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
732
        ALU_Ctrl.Reg         <= SubOp;
733
 
734
      when LDO_C1 =>
735 181 jshamlet
        CPU_Next_State       <= LDX_C2;
736 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
737 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
738
          ALU_Ctrl.Oper      <= ALU_UPP;
739
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
740 169 jshamlet
        end if;
741
 
742
      when LDX_C1 =>
743
        CPU_Next_State       <= LDX_C2;
744 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
745
          ALU_Ctrl.Oper      <= ALU_UPP;
746
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
747 181 jshamlet
        end if;
748 169 jshamlet
 
749
      when LDX_C2 =>
750
        CPU_Next_State       <= LDX_C3;
751 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
752 181 jshamlet
 
753
      when LDX_C3 =>
754
        CPU_Next_State       <= LDX_C4;
755 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
756 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
757 169 jshamlet
 
758 181 jshamlet
      when LDX_C4 =>
759 187 jshamlet
        CPU_Next_State       <= IDC_C0;
760 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
761 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
762 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
763 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
764
 
765
-------------------------------------------------------------------------------
766
-- Data Storage - Store to memory (STA, STO, STX)
767
-------------------------------------------------------------------------------
768
      when STA_C1 =>
769
        CPU_Next_State       <= STA_C2;
770
        Cache_Ctrl           <= CACHE_OPER2;
771
        DP_Ctrl.Src          <= DATA_WR_REG;
772
        DP_Ctrl.Reg          <= SubOp;
773
 
774
      when STA_C2 =>
775
        CPU_Next_State       <= STA_C3;
776 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
777 169 jshamlet
 
778
      when STA_C3 =>
779 187 jshamlet
        CPU_Next_State       <= IPF_C2;
780 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
781 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
782 169 jshamlet
 
783
      when STO_C1 =>
784 187 jshamlet
        CPU_Next_State       <= IPF_C0;
785 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
786 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
787 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
788
          CPU_Next_State     <= STO_C2;
789
          ALU_Ctrl.Oper      <= ALU_UPP;
790
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
791 169 jshamlet
        end if;
792
 
793
      when STO_C2 =>
794 187 jshamlet
        CPU_Next_State       <= IPF_C1;
795 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
796 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
797
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
798
 
799
      when STX_C1 =>
800 187 jshamlet
        CPU_Next_State       <= IPF_C1;
801 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
802 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
803
          CPU_Next_State     <= STX_C2;
804
          ALU_Ctrl.Oper      <= ALU_UPP;
805
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
806 169 jshamlet
        end if;
807
 
808
      when STX_C2 =>
809 187 jshamlet
        CPU_Next_State       <= IPF_C2;
810 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
811 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
812
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
813
 
814
-------------------------------------------------------------------------------
815
-- Multi-Cycle Math Operations (UPP, MUL)
816
-------------------------------------------------------------------------------
817
 
818
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
819 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
820
      --  need to tell the ALU to store the results to R1:R0 here. Note that
821
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
822 169 jshamlet
      when MUL_C1 =>
823 187 jshamlet
        CPU_Next_State       <= IPF_C2;
824 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
825 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
826
 
827
      when UPP_C1 =>
828 187 jshamlet
        CPU_Next_State       <= IPF_C2;
829 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
830 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
831
        ALU_Ctrl.Reg         <= SubOp_p1;
832
 
833
-------------------------------------------------------------------------------
834
-- Basic Stack Manipulation (PSH, POP, RSP)
835
-------------------------------------------------------------------------------
836
      when PSH_C1 =>
837 187 jshamlet
        CPU_Next_State       <= IPF_C1;
838 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
839
 
840
      when POP_C1 =>
841
        CPU_Next_State       <= POP_C2;
842
 
843
      when POP_C2 =>
844
        CPU_Next_State       <= POP_C3;
845 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
846 169 jshamlet
 
847
      when POP_C3 =>
848
        CPU_Next_State       <= POP_C4;
849
        Cache_Ctrl           <= CACHE_OPER1;
850 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
851 169 jshamlet
 
852
      when POP_C4 =>
853 187 jshamlet
        CPU_Next_State       <= IDC_C0;
854 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
855 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
856 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
857
        ALU_Ctrl.Reg         <= SubOp;
858 172 jshamlet
 
859 169 jshamlet
-------------------------------------------------------------------------------
860
-- Subroutines & Interrupts (RTS, JSR)
861
-------------------------------------------------------------------------------
862 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
863 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
864 186 jshamlet
        if( Int_Req = '1' )then
865
          CPU_Next_State     <= ISR_C1;
866 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
867
          --  instruction, compensating for the pipeline registers.
868 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
869
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
870
          --  operation due to the current instruction
871
          DP_Ctrl.Src        <= DATA_RD_MEM;
872
        end if;
873 169 jshamlet
 
874 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
875 225 jshamlet
        CPU_Halt_Ack         <= '1';
876 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
877
        if( CPU_Halt_Req = '0' )then
878
          CPU_Next_State     <= IPF_C0;
879
          DP_Ctrl.Src        <= DATA_RD_MEM;
880
        end if;
881
 
882
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
883
        CPU_Next_State       <= IPF_C0;
884
 
885 169 jshamlet
      when ISR_C1 =>
886
        CPU_Next_State       <= ISR_C2;
887
        INT_Ctrl.Incr_ISR    <= '1';
888
 
889
      when ISR_C2 =>
890
        CPU_Next_State       <= ISR_C3;
891
        DP_Ctrl.Src          <= DATA_WR_FLAG;
892
 
893
      when ISR_C3 =>
894
        CPU_Next_State       <= JSR_C1;
895
        Cache_Ctrl           <= CACHE_OPER1;
896 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
897 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
898 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
899
        DP_Ctrl.Src          <= DATA_WR_PC;
900 182 jshamlet
        DP_Ctrl.Reg          <= PC_MSB;
901 169 jshamlet
        Ack_D                <= '1';
902
 
903
      when JSR_C1 =>
904
        CPU_Next_State       <= JSR_C2;
905
        Cache_Ctrl           <= CACHE_OPER2;
906
        SP_Ctrl.Oper         <= SP_PUSH;
907
        DP_Ctrl.Src          <= DATA_WR_PC;
908 182 jshamlet
        DP_Ctrl.Reg          <= PC_LSB;
909 169 jshamlet
 
910
      when JSR_C2 =>
911 187 jshamlet
        CPU_Next_State       <= IPF_C0;
912 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
913 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
914 169 jshamlet
 
915
      when RTS_C1 =>
916
        CPU_Next_State       <= RTS_C2;
917
        SP_Ctrl.Oper         <= SP_POP;
918
 
919
      when RTS_C2 =>
920
        CPU_Next_State       <= RTS_C3;
921
        -- if this is an RTI, then we need to POP the flags
922
        if( SubOp = SOP_RTI )then
923
          SP_Ctrl.Oper       <= SP_POP;
924
        end if;
925
 
926
      when RTS_C3 =>
927
        CPU_Next_State       <= RTS_C4;
928
        Cache_Ctrl           <= CACHE_OPER1;
929
 
930
      when RTS_C4 =>
931
        CPU_Next_State       <= RTS_C5;
932
        Cache_Ctrl           <= CACHE_OPER2;
933
 
934
      when RTS_C5 =>
935 187 jshamlet
        CPU_Next_State       <= IPF_C0;
936 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
937 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
938 169 jshamlet
        if( SubOp = SOP_RTI )then
939
          CPU_Next_State     <= RTI_C6;
940
          Cache_Ctrl         <= CACHE_OPER1;
941 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
942
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
943 169 jshamlet
        end if;
944
 
945
      when RTI_C6 =>
946 187 jshamlet
        CPU_Next_State       <= IPF_C1;
947 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
948 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
949
 
950
      when others =>
951
        null;
952
    end case;
953
 
954
  end process;
955
 
956
-------------------------------------------------------------------------------
957
-- Registered portion of CPU finite state machine
958
-------------------------------------------------------------------------------
959 182 jshamlet
 
960 169 jshamlet
  CPU_Regs: process( Reset, Clock )
961
    variable Offset_SX       : ADDRESS_TYPE;
962 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
963 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
964
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
965
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
966
  begin
967
    if( Reset = Reset_Level )then
968 187 jshamlet
      CPU_State              <= IPF_C0;
969 169 jshamlet
      Opcode                 <= OP_INC;
970
      SubOp                  <= ACCUM;
971
      SubOp_p1               <= ACCUM;
972
      Operand1               <= x"00";
973
      Operand2               <= x"00";
974
      Instr_Prefetch         <= '0';
975
      Prefetch               <= x"00";
976
 
977 187 jshamlet
      CPU_Halt_Req           <= '0';
978 225 jshamlet
      Halt_Ack               <= '0';
979 187 jshamlet
 
980 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
981
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
982
      Open8_Bus.Rd_En        <= '1';
983 169 jshamlet
 
984
      Program_Ctr            <= Program_Start_Addr;
985
      Stack_Ptr              <= Stack_Start_Addr;
986
 
987
      Ack_Q                  <= '0';
988
      Ack_Q1                 <= '0';
989
      Int_Ack                <= '0';
990
 
991
      Int_Req                <= '0';
992
      Pending                <= x"00";
993
      Wait_for_FSM           <= '0';
994 210 jshamlet
      Wait_for_ISR           <= '0';
995 245 jshamlet
      Set_Mask               <= '0';
996 169 jshamlet
      if( Enable_NMI )then
997
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
998
      else
999
        Int_Mask             <= Default_Interrupt_Mask;
1000
      end if;
1001
      ISR_Addr               <= INT_VECTOR_0;
1002
 
1003
      for i in 0 to 7 loop
1004 188 jshamlet
        Regfile(i)           <= x"00";
1005 169 jshamlet
      end loop;
1006
      Flags                  <= x"00";
1007 244 jshamlet
      if( Default_Int_Flag )then
1008
        Flags(PSR_I)         <= '1';
1009
      end if;
1010 169 jshamlet
 
1011 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
1012 188 jshamlet
 
1013 169 jshamlet
    elsif( rising_edge(Clock) )then
1014 187 jshamlet
 
1015 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
1016
      Halt_Ack               <= CPU_Halt_Ack;
1017 187 jshamlet
 
1018 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1019
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1020
      Open8_Bus.Rd_En        <= '0';
1021 169 jshamlet
 
1022
-------------------------------------------------------------------------------
1023
-- Instruction/Operand caching for pipelined memory access
1024
-------------------------------------------------------------------------------
1025
      CPU_State              <= CPU_Next_State;
1026
      case Cache_Ctrl is
1027
        when CACHE_INSTR =>
1028
          Opcode             <= Rd_Data(7 downto 3);
1029
          SubOp              <= Rd_Data(2 downto 0);
1030
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
1031
          if( Instr_Prefetch = '1' )then
1032
            Opcode           <= Prefetch(7 downto 3);
1033
            SubOp            <= Prefetch(2 downto 0);
1034
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
1035
            Instr_Prefetch   <= '0';
1036
          end if;
1037
 
1038
        when CACHE_OPER1 =>
1039
          Operand1           <= Rd_Data;
1040
 
1041
        when CACHE_OPER2 =>
1042
          Operand2           <= Rd_Data;
1043
 
1044
        when CACHE_PREFETCH =>
1045
          Prefetch           <= Rd_Data;
1046
          Instr_Prefetch     <= '1';
1047
 
1048
        when CACHE_IDLE =>
1049
          null;
1050
      end case;
1051
 
1052
-------------------------------------------------------------------------------
1053
-- Program Counter
1054
-------------------------------------------------------------------------------
1055
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1056
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1057
 
1058
      case PC_Ctrl.Oper is
1059
        when PC_INCR =>
1060
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1061
 
1062
        when PC_LOAD =>
1063 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1064 169 jshamlet
 
1065
        when others =>
1066
          null;
1067
      end case;
1068
 
1069
-------------------------------------------------------------------------------
1070
-- (Write) Data Path
1071
-------------------------------------------------------------------------------
1072
      case DP_Ctrl.Src is
1073
        when DATA_BUS_IDLE =>
1074
          null;
1075
 
1076
        when DATA_RD_MEM =>
1077 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1078 169 jshamlet
 
1079
        when DATA_WR_REG =>
1080 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1081
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1082 169 jshamlet
 
1083
        when DATA_WR_FLAG =>
1084 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1085
          Open8_Bus.Wr_Data  <= Flags;
1086 169 jshamlet
 
1087
        when DATA_WR_PC =>
1088 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1089
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1090 182 jshamlet
          if( DP_Ctrl.Reg = PC_LSB )then
1091 223 jshamlet
            Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
1092 169 jshamlet
          end if;
1093
 
1094
        when others =>
1095
          null;
1096
      end case;
1097
 
1098
-------------------------------------------------------------------------------
1099
-- Stack Pointer
1100
-------------------------------------------------------------------------------
1101
      case SP_Ctrl.Oper is
1102
        when SP_IDLE =>
1103
          null;
1104
 
1105 181 jshamlet
        when SP_CLR =>
1106 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1107
 
1108 181 jshamlet
        when SP_SET =>
1109 245 jshamlet
          if( Supervisor_Mode )then
1110
            if( Flags(PSR_I) = '1' )then
1111
              Stack_Ptr      <= Regfile(1) & Regfile(0);
1112
            end if;
1113
          else
1114
            Stack_Ptr        <= Regfile(1) & Regfile(0);
1115
          end if;
1116 181 jshamlet
 
1117 169 jshamlet
        when SP_POP  =>
1118
          Stack_Ptr          <= Stack_Ptr + 1;
1119
 
1120
        when SP_PUSH =>
1121
          Stack_Ptr          <= Stack_Ptr - 1;
1122
 
1123
        when others =>
1124
          null;
1125
 
1126
      end case;
1127
 
1128
-------------------------------------------------------------------------------
1129
-- Interrupt Controller
1130
-------------------------------------------------------------------------------
1131 245 jshamlet
 
1132
      -- If Supervisor_Mode is set, restrict the SMSK instruction such that it
1133
      --  requires the I bit to be set.
1134
      if( Supervisor_Mode )then
1135
        Set_Mask             <= INT_Ctrl.Mask_Set and Flags(PSR_I);
1136
      else
1137
        Set_Mask             <= INT_Ctrl.Mask_Set;
1138
      end if;
1139
 
1140 169 jshamlet
      -- The interrupt control mask is always sourced out of R0
1141 245 jshamlet
      if( Set_Mask = '1' )then
1142 169 jshamlet
        if( Enable_NMI )then
1143
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1144
        else
1145
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1146
        end if;
1147
      end if;
1148
 
1149
      -- Combine external and internal interrupts, and mask the OR of the two
1150
      --  with the mask. Record any incoming interrupts to the pending buffer
1151
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1152
                                Int_Mask;
1153 172 jshamlet
 
1154 169 jshamlet
      Pending                <= i_Ints or Pending;
1155
 
1156 210 jshamlet
      if( Sequential_Interrupts )then
1157
        Wait_for_ISR         <= Flags(PSR_I);
1158
      else
1159
        Wait_for_ISR         <= '0';
1160
      end if;
1161
 
1162
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1163 169 jshamlet
        if(    Pending(0) = '1' )then
1164
          ISR_Addr           <= INT_VECTOR_0;
1165
          Pending(0)         <= '0';
1166
        elsif( Pending(1) = '1' )then
1167
          ISR_Addr           <= INT_VECTOR_1;
1168
          Pending(1)         <= '0';
1169
        elsif( Pending(2) = '1' )then
1170
          ISR_Addr           <= INT_VECTOR_2;
1171
          Pending(2)         <= '0';
1172
        elsif( Pending(3) = '1' )then
1173
          ISR_Addr           <= INT_VECTOR_3;
1174
          Pending(3)         <= '0';
1175
        elsif( Pending(4) = '1' )then
1176
          ISR_Addr           <= INT_VECTOR_4;
1177
          Pending(4)         <= '0';
1178
        elsif( Pending(5) = '1' )then
1179
          ISR_Addr           <= INT_VECTOR_5;
1180
          Pending(5)         <= '0';
1181
        elsif( Pending(6) = '1' )then
1182
          ISR_Addr           <= INT_VECTOR_6;
1183
          Pending(6)         <= '0';
1184
        elsif( Pending(7) = '1' )then
1185
          ISR_Addr           <= INT_VECTOR_7;
1186
          Pending(7)         <= '0';
1187
        end if;
1188 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1189 169 jshamlet
      end if;
1190
 
1191
      -- Reset the Wait_for_FSM flag on Int_Ack
1192
      Ack_Q                  <= Ack_D;
1193
      Ack_Q1                 <= Ack_Q;
1194
      Int_Ack                <= Ack_Q1;
1195
      if( Int_Ack = '1' )then
1196
        Wait_for_FSM         <= '0';
1197
      end if;
1198
 
1199
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1200
 
1201
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1202
      --  lower half of the address.
1203
      if( INT_Ctrl.Incr_ISR = '1' )then
1204
        ISR_Addr             <= ISR_Addr + 1;
1205
      end if;
1206
 
1207
-------------------------------------------------------------------------------
1208
-- ALU (Arithmetic / Logic Unit)
1209
-------------------------------------------------------------------------------
1210
      Index                  := conv_integer(ALU_Ctrl.Reg);
1211
      Sum                    := (others => '0');
1212
      Temp                   := (others => '0');
1213
 
1214
      case ALU_Ctrl.Oper is
1215
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1216
          Sum                := ("0" & x"01") +
1217
                                ("0" & Regfile(Index));
1218 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1219
          Flags(PSR_C)       <= Sum(8);
1220 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1221 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1222
 
1223
        when ALU_UPP => -- Rn = Rn + 1
1224
          Sum                := ("0" & x"01") +
1225
                                ("0" & Regfile(Index));
1226 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1227 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1228
 
1229
        when ALU_UPP2 => -- Rn = Rn + C
1230
          Sum                := ("0" & x"00") +
1231
                                ("0" & Regfile(Index)) +
1232 185 jshamlet
                                Flags(PSR_C);
1233
          Flags(PSR_C)       <= Sum(8);
1234 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1235
 
1236
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1237
          Sum                := ("0" & Regfile(0)) +
1238
                                ("0" & Regfile(Index)) +
1239 185 jshamlet
                                Flags(PSR_C);
1240
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1241
          Flags(PSR_C)       <= Sum(8);
1242
          Flags(PSR_N)       <= Sum(7);
1243 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1244
 
1245
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1246
          Temp               := "0" & Regfile(Index);
1247 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1248
          Flags(PSR_N)       <= Temp(7);
1249 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1250
 
1251
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1252
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1253 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1254
          Flags(PSR_N)       <= Temp(7);
1255 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1256
 
1257
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1258
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1259 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1260
          Flags(PSR_N)       <= Temp(7);
1261 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1262
 
1263
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1264
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1265 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1266
          Flags(PSR_N)       <= Temp(7);
1267 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1268
 
1269
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1270 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1271
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1272
          Flags(PSR_C)       <= Temp(8);
1273
          Flags(PSR_N)       <= Temp(7);
1274 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1275
 
1276
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1277 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1278 169 jshamlet
                                Regfile(Index)(7 downto 1);
1279 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1280
          Flags(PSR_C)       <= Temp(8);
1281
          Flags(PSR_N)       <= Temp(7);
1282 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1283
 
1284
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1285
          Sum                := ("0" & Regfile(Index)) +
1286
                                ("0" & x"FF");
1287 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1288
          Flags(PSR_C)       <= Sum(8);
1289
          Flags(PSR_N)       <= Sum(7);
1290 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1291
 
1292
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1293
          Sum                := ("0" & Regfile(0)) +
1294
                                ("1" & (not Regfile(Index))) +
1295 185 jshamlet
                                Flags(PSR_C);
1296
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1297
          Flags(PSR_C)       <= Sum(8);
1298
          Flags(PSR_N)       <= Sum(7);
1299 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1300
 
1301
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1302
          Sum                := ("0" & Regfile(0)) +
1303
                                ("0" & Regfile(Index));
1304 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1305 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1306 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1307
          Flags(PSR_N)       <= Sum(7);
1308 169 jshamlet
 
1309
        when ALU_STP => -- Sets bit(n) in the Flags register
1310
          Flags(Index)       <= '1';
1311
 
1312
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1313 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1314
          Flags(PSR_N)       <= Regfile(0)(7);
1315 169 jshamlet
 
1316
        when ALU_CLP => -- Clears bit(n) in the Flags register
1317
          Flags(Index)       <= '0';
1318
 
1319
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1320
          Temp               := "0" & Regfile(0);
1321 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1322
          Flags(PSR_N)       <= Temp(7);
1323 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1324
 
1325
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1326
          Sum                := ("0" & Regfile(0)) +
1327
                                ("1" & (not Regfile(Index))) +
1328
                                '1';
1329 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1330
          Flags(PSR_C)       <= Sum(8);
1331
          Flags(PSR_N)       <= Sum(7);
1332 169 jshamlet
 
1333
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1334
          Regfile(0)         <= Mult(7 downto 0);
1335
          Regfile(1)         <= Mult(15 downto 8);
1336 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1337 169 jshamlet
 
1338
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1339 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1340
          Flags(PSR_N)       <= Operand1(7);
1341
          Regfile(Index)     <= Operand1;
1342 169 jshamlet
 
1343
        when ALU_POP => -- Rn <= Data
1344 185 jshamlet
          Regfile(Index)     <= Operand1;
1345 169 jshamlet
 
1346
        when ALU_RFLG =>
1347 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1348
          if( not RTI_Ignores_GP_Flags )then
1349
            Flags(7 downto 4)<= Operand1(7 downto 4);
1350
          end if;
1351 169 jshamlet
 
1352 185 jshamlet
        when ALU_RSP =>
1353 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1354
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1355
 
1356 185 jshamlet
        when ALU_GMSK =>
1357
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1358
          Regfile(0)         <= Int_Mask;
1359
 
1360 169 jshamlet
        when others =>
1361
          null;
1362
      end case;
1363
 
1364 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1365 188 jshamlet
 
1366 169 jshamlet
    end if;
1367
  end process;
1368
 
1369 182 jshamlet
-------------------------------------------------------------------------------
1370
-- Multiplier Logic
1371
--
1372
-- We need to infer a hardware multipler, so we create a special clocked
1373
--  process with no reset or clock enable
1374
-------------------------------------------------------------------------------
1375
 
1376
  Multiplier_proc: process( Clock )
1377
  begin
1378
    if( rising_edge(Clock) )then
1379
      Mult                   <= Regfile(0) *
1380 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1381
    end if;
1382
  end process;
1383
 
1384
end architecture;

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