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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
2 169 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
24 181 jshamlet
-- VHDL Units :  o8_cpu
25 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44
--            :   specified by Stack_Xfer_Flag. If the flag is '0', RSP will
45
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 181 jshamlet
--            :  Stack_Xfer_Flag instructs the core to use the specified ALU
52
--            :   flag to alter the behavior of the RSP instruction when
53
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it is ignored.
54
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
74
--            :   after an interrupt. By default, all of the flag bits are put
75
--            :   back to their original state. If this flag is set true, only
76
--            :   the lower four bits are restored, allowing ISR code to alter
77
--            :   the GP flags persistently.
78
--            :
79 244 jshamlet
--            :  Supervisor_Mode, when set, disables the STP PSR_I instruction
80
--            :   preventing code from setting the I bit. When enabled, only
81
--            :   interrupts can set the I bit, allowing for more robust memory
82
--            :   protection by preventing errant code execution from
83
--            :   inadvertently entering an interrupt state.
84
--            :
85 248 jshamlet
--            :   This setting also sets I bit at startup so that any
86
--            :   initialization code may be run in an ISR context, initially
87
--            :   bypassing memory protection. Init code should clear the I bit
88
--            :   when done;
89 244 jshamlet
--            :
90 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
91
--            :   interrupt mask. To remain true to the original core, which
92
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
93
--            :   it can be initialized to any value. Note that Enable_NMI
94
--            :   will logically force the LSB high.
95 172 jshamlet
--            :
96 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
97
--            :   on a high or low level from higher logic.
98
--            :
99
--            : Architecture notes
100
--            :  This model deviates from the original ISA in a few important
101
--            :   ways.
102
--            :
103
--            :  First, there is only one set of registers. Interrupt service
104
--            :   routines must explicitely preserve context since the the
105
--            :   hardware doesn't. This was done to decrease size and code
106
--            :   complexity. Older code that assumes this behavior will not
107
--            :   execute correctly on this processor model.
108
--            :
109
--            :  Second, this model adds an additional pipeline stage between
110
--            :   the instruction decoder and the ALU. Unfortunately, this
111
--            :   means that the instruction stream has to be restarted after
112
--            :   any math instruction is executed, implying that any ALU
113
--            :   instruction now has a latency of 2 instead of 0. The
114
--            :   advantage is that the maximum frequency has gone up
115
--            :   significantly, as the ALU code is vastly more efficient.
116
--            :   As an aside, this now means that all math instructions,
117
--            :   including MUL (see below) and UPP have the same instruction
118
--            :   latency.
119
--            :
120
--            :  Third, the original ISA, also a soft core, had two reserved
121
--            :   instructions, USR and USR2. These have been implemented as
122
--            :   DBNZ, and MUL respectively.
123
--            :
124
--            :  DBNZ decrements the specified register and branches if the
125
--            :   result is non-zero. The instruction effectively executes a
126
--            :   DEC Rn instruction prior to branching, so the same flags will
127
--            :   be set.
128
--            :
129
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
130
--            :   latency is identical to other ALU instructions. Only the Z
131
--            :   flag is set, since there is no defined overflow or "negative
132
--            :   16-bit values"
133
--            :
134
--            :  Fourth, indexed load/store instructions now have an (optional)
135
--            :   ability to post-increment their index registers. If enabled,
136
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
137
--            :   register pair to be incremented after the storage access.
138
--            :
139
--            :  Fifth, the RSP instruction has been (optionally) altered to
140
--            :   allow the stack pointer to be sourced from R1:R0.
141
--            :
142
--            :  Sixth, the BRK instruction can optionally implement a WAI,
143
--            :   which is the same as the INT instruction without the soft
144
--            :   interrupt, as a way to put the processor to "sleep" until the
145
--            :   next external interrupt.
146
--            :
147
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
148
--            :   with priority. This model has the same 8 interrupts, but
149 172 jshamlet
--            :   allows software to mask them (with an additional option to
150 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
151
--            :
152
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
153
--            :   were repurposed to support a new interrupt mask.
154
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
155
--            :   to/from the interrupt mask register. SMSK is immediate, while
156
--            :   GMSK has the same overhead as a math instruction.
157
--
158
-- Revision History
159
-- Author          Date     Change
160
------------------ -------- ---------------------------------------------------
161
-- Seth Henry      07/19/06 Design Start
162
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
163
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
164
--                           corruption issues.
165
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
166
--                           path sections.
167
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
168
--                           single entity.
169
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
170
--                           processor to wait for an interrupt instead of the
171
--                           normal BRK behavior.
172 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
173 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
174
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
175
--                           faster logic that simply does priority encoding.
176
-- Seth Henry      08/06/13 Removed HALT functionality
177
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
178 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
179 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
180
--                           allowing true backup/restore of the stack pointer
181 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
182
--                           in order to simplify things and eliminate
183
--                           redundancies. Came across and fixed a problem with
184
--                           the STO instruction when Enable_Auto_Increment is
185
--                           NOT set.
186 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
187
--                           the assembler names. Also fixed an issue where
188
--                           the I bit wasn't being cleared after interrupts.
189
--                          Simplified the program counter logic to only use
190
--                           the offset for increments, redefining the
191
--                           original modes as fixed offset values.
192
--                          Modified the ALU section with a new ALU operation
193
--                           for GMSK. This allowed the .data field to be
194
--                           removed and Operand1 used in its place, which
195
--                           simplified the logic a great deal.
196 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
197
--                           the instruction decode state, where it acts as a
198
--                           modified form of the BRK instruction that holds
199
--                           state until CPU_Halt is deasserted. This has a
200
--                           much smaller impact on Fmax/complexity than the
201
--                           original clock enable, but imposes a mild impact
202
--                           due to the need to reset the instruction pipeline
203 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
204
--                           the flags, including the general purpose ones, or
205
--                           only the core ALU flags (Z, N, and C). Also
206
--                           brought out copies of the GP flags for external
207
--                           connection.
208 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
209
--                           while the I bit is set to avoid reentering ISRs
210
--                           This may slightly affect timing, as this will
211
--                           potentially block higher priority interrupts
212
--                           until the lower priority ISR returns or clears
213
--                           the I bit.
214
--                          Also added the I bit to the exported flags for
215
--                           use in memory protection schemes.
216 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
217 225 jshamlet
--                           reset and usec_tick logic to drive utility
218
--                           signals. Also added Halt_Ack output.
219 244 jshamlet
-- Seth Henry      05/20/20 Added two new generics to alter the way the I bit
220
--                           is handled. The Supervisor_Mode setting disables
221
--                           STP PSR_I from being executed, preventing it
222
--                           from being set outside of an ISR. The
223
--                           Default_Int_Flag setting allows the I bit to
224
--                           start set so that initialization code can run,
225
--                           but not be hijacked later to corrupt any memory
226
--                           write protection later.
227 245 jshamlet
-- Seth Henry      05/21/20 Supervisor_Mode now protects the interrupt mask
228
--                           and stack pointer as well.
229 248 jshamlet
-- Seth Henry      05/24/20 Removed the Default_Int_Flag, as it is covered by
230
--                           Supervisor_Mode. If Supervisor_Mode isn't set,
231
--                           code can simply use STP to set the bit
232 169 jshamlet
 
233
library ieee;
234
  use ieee.std_logic_1164.all;
235
  use ieee.std_logic_unsigned.all;
236
  use ieee.std_logic_arith.all;
237
  use ieee.std_logic_misc.all;
238
 
239
library work;
240 227 jshamlet
  use work.Open8_pkg.all;
241 169 jshamlet
 
242 183 jshamlet
entity o8_cpu is
243 169 jshamlet
  generic(
244
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
245
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
246
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
247
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
248 188 jshamlet
    Stack_Xfer_Flag          : integer      := PSR_GP4; -- GP4 modifies RSP
249 169 jshamlet
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
250
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
251
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
252 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
253 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
254 244 jshamlet
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
255 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
256 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
257
);
258 169 jshamlet
  port(
259
    Clock                    : in  std_logic;
260 224 jshamlet
    PLL_Locked               : in  std_logic;
261 169 jshamlet
    --
262 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
263
    Halt_Ack                 : out std_logic;
264
    --
265 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
266 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
267 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
268
);
269 169 jshamlet
end entity;
270
 
271 183 jshamlet
architecture behave of o8_cpu is
272 169 jshamlet
 
273 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
274
  signal Reset               : std_logic := Reset_Level;
275
 
276
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
277
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
278
  constant USEC_DLY          : std_logic_vector :=
279
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
280
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
281
  signal uSec_Tick           : std_logic;
282
 
283 169 jshamlet
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;
284
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;
285
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;
286
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;
287
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;
288
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;
289
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;
290
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;
291
 
292 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
293
  signal CPU_State           : CPU_STATES := IPF_C0;
294 169 jshamlet
 
295 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
296
  signal CPU_Halt_Ack        : std_logic := '0';
297 187 jshamlet
 
298 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
299
 
300
  signal Opcode              : OPCODE_TYPE := (others => '0');
301
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
302
 
303
  signal Prefetch            : DATA_TYPE   := x"00";
304
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
305
 
306
  signal Instr_Prefetch      : std_logic   := '0';
307
 
308
  signal PC_Ctrl             : PC_CTRL_TYPE;
309
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
310
 
311 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
312
  signal Regfile             : REGFILE_TYPE;
313
  signal Flags               : FLAG_TYPE;
314
  signal Mult                : ADDRESS_TYPE := x"0000";
315
 
316 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
317
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
318
 
319
  signal DP_Ctrl             : DATA_CTRL_TYPE;
320
 
321
  signal INT_Ctrl            : INT_CTRL_TYPE;
322
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
323
  signal Int_Req, Int_Ack    : std_logic   := '0';
324 245 jshamlet
  signal Set_Mask            : std_logic   := '0';
325 169 jshamlet
  signal Int_Mask            : DATA_TYPE   := x"00";
326
  signal ISR_Addr            : ADDRESS_TYPE := x"0000";
327
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
328
  signal Pending             : INTERRUPT_BUNDLE := x"00";
329
  signal Wait_for_FSM        : std_logic := '0';
330 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
331 169 jshamlet
 
332
begin
333
 
334 224 jshamlet
-------------------------------------------------------------------------------
335
-- Reset & uSec Tick
336
-------------------------------------------------------------------------------
337 185 jshamlet
 
338 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
339
  begin
340
    if( PLL_Locked = '0' )then
341
      Reset_q                <= Reset_Level;
342
      Reset                  <= Reset_Level;
343
    elsif( rising_edge(Clock) )then
344
      Reset_q                <= not Reset_Level;
345
      Reset                  <= Reset_q;
346
    end if;
347
  end process;
348
 
349
  uSec_Tick_proc: process( Clock, Reset )
350
  begin
351
    if( Reset = Reset_Level )then
352
      uSec_Cntr              <= USEC_DLY;
353
      uSec_Tick              <= '0';
354
    elsif( rising_edge( Clock ) )then
355
      uSec_Cntr              <= uSec_Cntr - 1;
356
      if( or_reduce(uSec_Cntr) = '0' )then
357
        uSec_Cntr            <= USEC_DLY;
358
      end if;
359
      uSec_Tick              <= nor_reduce(uSec_Cntr);
360
    end if;
361
  end process;
362
 
363
  Open8_Bus.Clock            <= Clock;
364
  Open8_Bus.Reset            <= Reset;
365
  Open8_Bus.uSec_Tick        <= uSec_Tick;
366
 
367 169 jshamlet
-------------------------------------------------------------------------------
368 182 jshamlet
-- Address bus selection/generation logic
369 169 jshamlet
-------------------------------------------------------------------------------
370
 
371 185 jshamlet
  Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1,
372
                         Operand2, Program_Ctr, Stack_Ptr, ISR_Addr )
373 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
374
    variable Offset_SX       : ADDRESS_TYPE;
375
  begin
376 182 jshamlet
 
377
    if( Enable_Auto_Increment )then
378
      Reg                    := conv_integer(SubOp(2 downto 1) & '0');
379
      Reg_1                  := conv_integer(SubOp(2 downto 1) & '1');
380
    else
381
      Reg                    := conv_integer(SubOp);
382
      Reg_1                  := conv_integer(SubOp_p1);
383
    end if;
384
 
385
    Offset_SX(15 downto 0)   := (others => Operand1(7));
386
    Offset_SX(7 downto 0)    := Operand1;
387
 
388
    case( CPU_State )is
389
 
390
      when LDA_C2 | STA_C2 =>
391 223 jshamlet
        Open8_Bus.Address    <= Operand2 & Operand1;
392 182 jshamlet
 
393
      when LDX_C1 | STX_C1 =>
394 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg));
395 182 jshamlet
 
396
      when LDO_C1 | STO_C1 =>
397 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
398 182 jshamlet
 
399
      when ISR_C1 | ISR_C2 =>
400 223 jshamlet
        Open8_Bus.Address    <= ISR_Addr;
401 182 jshamlet
 
402
      when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
403 223 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
404 182 jshamlet
 
405
      when others =>
406 223 jshamlet
        Open8_Bus.Address    <= Program_Ctr;
407 182 jshamlet
 
408
    end case;
409
 
410
  end process;
411
 
412
-------------------------------------------------------------------------------
413
-- Combinatorial portion of CPU finite state machine
414
-- State Logic / Instruction Decoding & Execution
415
-------------------------------------------------------------------------------
416
 
417 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
418 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
419
    variable Reg             : integer range 0 to 7 := 0;
420
  begin
421 169 jshamlet
    CPU_Next_State           <= CPU_State;
422
    Cache_Ctrl               <= CACHE_IDLE;
423
    --
424 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
425
    PC_Ctrl.Offset           <= PC_IDLE;
426 182 jshamlet
    --
427 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
428
    ALU_Ctrl.Reg             <= ACCUM;
429
    --
430
    SP_Ctrl.Oper             <= SP_IDLE;
431
    --
432
    DP_Ctrl.Src              <= DATA_RD_MEM;
433
    DP_Ctrl.Reg              <= ACCUM;
434
    --
435
    INT_Ctrl.Mask_Set        <= '0';
436
    INT_Ctrl.Soft_Ints       <= x"00";
437
    INT_Ctrl.Incr_ISR        <= '0';
438
    Ack_D                    <= '0';
439 225 jshamlet
    --
440 182 jshamlet
    Reg                     := conv_integer(SubOp);
441 225 jshamlet
    --
442
    CPU_Halt_Ack             <= '0';
443 169 jshamlet
 
444
    case CPU_State is
445
-------------------------------------------------------------------------------
446
-- Initial Instruction fetch & decode
447
-------------------------------------------------------------------------------
448 187 jshamlet
      when IPF_C0 =>
449
        CPU_Next_State       <= IPF_C1;
450 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
451 169 jshamlet
 
452 187 jshamlet
      when IPF_C1 =>
453
        CPU_Next_State       <= IPF_C2;
454 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
455 169 jshamlet
 
456 187 jshamlet
      when IPF_C2 =>
457
        CPU_Next_State       <= IDC_C0;
458 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
459 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
460 169 jshamlet
 
461 187 jshamlet
      when IDC_C0 =>
462
        CPU_Next_State       <= IDC_C0;
463 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
464
 
465
        case Opcode is
466
          when OP_PSH =>
467
            CPU_Next_State   <= PSH_C1;
468
            Cache_Ctrl       <= CACHE_PREFETCH;
469 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
470 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
471
            DP_Ctrl.Reg      <= SubOp;
472
 
473
          when OP_POP =>
474
            CPU_Next_State   <= POP_C1;
475
            Cache_Ctrl       <= CACHE_PREFETCH;
476 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
477 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
478
 
479
          when OP_BR0 | OP_BR1 =>
480
            CPU_Next_State   <= BRN_C1;
481
            Cache_Ctrl       <= CACHE_OPER1;
482 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
483 169 jshamlet
 
484 185 jshamlet
 
485 169 jshamlet
          when OP_DBNZ =>
486
            CPU_Next_State   <= DBNZ_C1;
487
            Cache_Ctrl       <= CACHE_OPER1;
488 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
489 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
490
            ALU_Ctrl.Reg     <= SubOp;
491
 
492
          when OP_INT =>
493 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
494 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
495
            --  Also, unlike CPU_Halt, the INT instruction is actually being
496
            --  executed, so go ahead and increment the program counter before
497
            --  pausing so the CPU restarts on the next instruction.
498 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
499 187 jshamlet
              CPU_Next_State <= WAI_Cx;
500 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
501
            end if;
502
 
503
          when OP_STK =>
504
            case SubOp is
505
              when SOP_RSP  =>
506 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
507 181 jshamlet
                if( not Allow_Stack_Address_Move )then
508 187 jshamlet
                  -- The default behavior for this instruction is to simply
509
                  --  repoint the SP to the HDL default
510 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
511 181 jshamlet
                end if;
512 187 jshamlet
                if( Allow_Stack_Address_Move and
513
                    Flags(Stack_Xfer_Flag) = '1' )then
514
                  -- If RSP is set to allow SP moves, and the specified flag
515
                  --  is true, then signal the stack pointer logic to load
516
                  --  from R1:R0
517 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
518 181 jshamlet
                end if;
519 187 jshamlet
                if( Allow_Stack_Address_Move and
520
                    Flags(Stack_Xfer_Flag) = '0')then
521
                  -- If RSP is set to allow SP moves, and the specified flag
522
                  --  is false, then signal the ALU to copy the stack pointer
523
                  --  to R1:R0
524 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
525 181 jshamlet
                end if;
526 169 jshamlet
 
527
              when SOP_RTS | SOP_RTI =>
528 185 jshamlet
                CPU_Next_State    <= RTS_C1;
529 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
530 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
531 169 jshamlet
 
532
              when SOP_BRK  =>
533
                if( BRK_Implements_WAI )then
534 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
535
                  --  increment the PC similar to an ISR flow.
536
                  CPU_Next_State  <= WAI_Cx;
537 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
538 187 jshamlet
                else
539
                -- If Break is implemented normally, back the PC up by
540
                --  2 and return through IPF_C0 in order to execute a 5
541
                --  clock cycle delay
542
                  CPU_Next_State  <= BRK_C1;
543
                  PC_Ctrl.Offset  <= PC_REV2;
544 169 jshamlet
                end if;
545
 
546
              when SOP_JMP  =>
547 185 jshamlet
                CPU_Next_State    <= JMP_C1;
548
                Cache_Ctrl        <= CACHE_OPER1;
549 169 jshamlet
 
550
              when SOP_SMSK =>
551 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
552 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
553
 
554
              when SOP_GMSK =>
555 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
556
                ALU_Ctrl.Oper     <= ALU_GMSK;
557 169 jshamlet
 
558
              when SOP_JSR =>
559
                CPU_Next_State <= JSR_C1;
560 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
561
                DP_Ctrl.Src       <= DATA_WR_PC;
562
                DP_Ctrl.Reg       <= PC_MSB;
563 169 jshamlet
 
564
              when others => null;
565
            end case;
566
 
567
          when OP_MUL =>
568
            CPU_Next_State   <= MUL_C1;
569 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
570
            --  to the ALU writing the result to registers. As a result, this
571
            --  state needs to idle the ALU initially, and back the PC up by 1
572
            -- We can get away with only 1 extra clock by pre-fetching the
573
            --  next instruction, though.
574 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
575 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
576 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
577
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
578
            --  now, but hold off on the ALU command until the next state.
579 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
580
            ALU_Ctrl.Reg     <= SubOp;
581
 
582
          when OP_UPP =>
583
            CPU_Next_State   <= UPP_C1;
584
            Cache_Ctrl       <= CACHE_PREFETCH;
585 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
586 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
587
            ALU_Ctrl.Reg     <= SubOp;
588
 
589
          when OP_LDA =>
590
            CPU_Next_State   <= LDA_C1;
591
            Cache_Ctrl       <= CACHE_OPER1;
592
 
593
          when OP_LDI =>
594
            CPU_Next_State   <= LDI_C1;
595
            Cache_Ctrl       <= CACHE_OPER1;
596 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
597 169 jshamlet
 
598
          when OP_LDO =>
599
            CPU_Next_State   <= LDO_C1;
600
            Cache_Ctrl       <= CACHE_OPER1;
601 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
602 169 jshamlet
 
603
          when OP_LDX =>
604
            CPU_Next_State   <= LDX_C1;
605 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
606 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
607 169 jshamlet
 
608
          when OP_STA =>
609
            CPU_Next_State   <= STA_C1;
610
            Cache_Ctrl       <= CACHE_OPER1;
611
 
612
          when OP_STO =>
613
            CPU_Next_State   <= STO_C1;
614
            Cache_Ctrl       <= CACHE_OPER1;
615 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
616 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
617
            DP_Ctrl.Reg      <= ACCUM;
618
 
619
          when OP_STX =>
620
            CPU_Next_State   <= STX_C1;
621
            Cache_Ctrl       <= CACHE_PREFETCH;
622 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
623 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
624
            DP_Ctrl.Reg      <= ACCUM;
625
 
626 244 jshamlet
          when OP_STP =>
627
            PC_Ctrl.Offset   <= PC_NEXT;
628
            if( Supervisor_Mode )then
629
              if( SubOp /= PSR_I )then
630
                ALU_Ctrl.Oper  <= Opcode;
631
                ALU_Ctrl.Reg   <= SubOp;
632
              end if;
633
            else
634
              ALU_Ctrl.Oper  <= Opcode;
635
              ALU_Ctrl.Reg   <= SubOp;
636
            end if;
637
 
638 169 jshamlet
          when others =>
639 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
640 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
641
            ALU_Ctrl.Reg     <= SubOp;
642
 
643
        end case;
644
 
645 186 jshamlet
        if( Int_Req = '1' )then
646
          CPU_Next_State     <= ISR_C1;
647 187 jshamlet
        end if;
648
 
649
        if( CPU_Halt_Req = '1' )then
650
          CPU_Next_State     <= WAH_Cx;
651
        end if;
652
 
653
        -- If either of these override conditions are true, the decoder needs
654
        --  to undo everything it just setup, since even "single-cycle"
655
        --  instructions will be executed again upon return.
656
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
657
          -- In either case, we want to skip loading the cache, as the cache
658
          --  will be invalid by the time we get back.
659 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
660 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
661
          -- compensating for the pipeline registers.
662 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
663
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
664 187 jshamlet
          --  operation due to the current instruction.
665 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
666
          SP_Ctrl.Oper       <= SP_IDLE;
667 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
668
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
669 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
670 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
671
          --  executed again when normal processing resumes, so axe their
672
          --  requests for now.
673
          INT_Ctrl.Mask_Set       <= '0';
674
          INT_Ctrl.Soft_Ints(Reg) <= '0';
675 186 jshamlet
        end if;
676
 
677 169 jshamlet
-------------------------------------------------------------------------------
678
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
679
-------------------------------------------------------------------------------
680
 
681
      when BRN_C1 =>
682 187 jshamlet
        CPU_Next_State       <= IDC_C0;
683 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
684 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
685 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
686 187 jshamlet
          CPU_Next_State     <= IPF_C0;
687 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
688
          PC_Ctrl.Offset     <= Operand1;
689
        end if;
690
 
691
      when DBNZ_C1 =>
692 187 jshamlet
        CPU_Next_State       <= IDC_C0;
693 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
694 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
695
        if( Flags(PSR_Z) = '0' )then
696 187 jshamlet
          CPU_Next_State     <= IPF_C0;
697 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
698
          PC_Ctrl.Offset     <= Operand1;
699
        end if;
700
 
701
      when JMP_C1 =>
702
        CPU_Next_State       <= JMP_C2;
703
        Cache_Ctrl           <= CACHE_OPER2;
704
 
705
      when JMP_C2 =>
706 187 jshamlet
        CPU_Next_State       <= IPF_C0;
707 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
708
 
709
-------------------------------------------------------------------------------
710
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
711
-------------------------------------------------------------------------------
712
 
713
      when LDA_C1 =>
714
        CPU_Next_State       <= LDA_C2;
715
        Cache_Ctrl           <= CACHE_OPER2;
716
 
717
      when LDA_C2 =>
718
        CPU_Next_State       <= LDA_C3;
719
 
720
      when LDA_C3 =>
721
        CPU_Next_State       <= LDA_C4;
722 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
723 169 jshamlet
 
724
      when LDA_C4 =>
725
        CPU_Next_State       <= LDI_C1;
726
        Cache_Ctrl           <= CACHE_OPER1;
727 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
728 169 jshamlet
 
729
      when LDI_C1 =>
730 187 jshamlet
        CPU_Next_State       <= IDC_C0;
731 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
732 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
733 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
734
        ALU_Ctrl.Reg         <= SubOp;
735
 
736
      when LDO_C1 =>
737 181 jshamlet
        CPU_Next_State       <= LDX_C2;
738 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
739 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
740
          ALU_Ctrl.Oper      <= ALU_UPP;
741
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
742 169 jshamlet
        end if;
743
 
744
      when LDX_C1 =>
745
        CPU_Next_State       <= LDX_C2;
746 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
747
          ALU_Ctrl.Oper      <= ALU_UPP;
748
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
749 181 jshamlet
        end if;
750 169 jshamlet
 
751
      when LDX_C2 =>
752
        CPU_Next_State       <= LDX_C3;
753 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
754 181 jshamlet
 
755
      when LDX_C3 =>
756
        CPU_Next_State       <= LDX_C4;
757 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
758 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
759 169 jshamlet
 
760 181 jshamlet
      when LDX_C4 =>
761 187 jshamlet
        CPU_Next_State       <= IDC_C0;
762 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
763 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
764 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
765 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
766
 
767
-------------------------------------------------------------------------------
768
-- Data Storage - Store to memory (STA, STO, STX)
769
-------------------------------------------------------------------------------
770
      when STA_C1 =>
771
        CPU_Next_State       <= STA_C2;
772
        Cache_Ctrl           <= CACHE_OPER2;
773
        DP_Ctrl.Src          <= DATA_WR_REG;
774
        DP_Ctrl.Reg          <= SubOp;
775
 
776
      when STA_C2 =>
777
        CPU_Next_State       <= STA_C3;
778 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
779 169 jshamlet
 
780
      when STA_C3 =>
781 187 jshamlet
        CPU_Next_State       <= IPF_C2;
782 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
783 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
784 169 jshamlet
 
785
      when STO_C1 =>
786 187 jshamlet
        CPU_Next_State       <= IPF_C0;
787 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
788 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
789 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
790
          CPU_Next_State     <= STO_C2;
791
          ALU_Ctrl.Oper      <= ALU_UPP;
792
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
793 169 jshamlet
        end if;
794
 
795
      when STO_C2 =>
796 187 jshamlet
        CPU_Next_State       <= IPF_C1;
797 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
798 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
799
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
800
 
801
      when STX_C1 =>
802 187 jshamlet
        CPU_Next_State       <= IPF_C1;
803 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
804 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
805
          CPU_Next_State     <= STX_C2;
806
          ALU_Ctrl.Oper      <= ALU_UPP;
807
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
808 169 jshamlet
        end if;
809
 
810
      when STX_C2 =>
811 187 jshamlet
        CPU_Next_State       <= IPF_C2;
812 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
813 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
814
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
815
 
816
-------------------------------------------------------------------------------
817
-- Multi-Cycle Math Operations (UPP, MUL)
818
-------------------------------------------------------------------------------
819
 
820
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
821 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
822
      --  need to tell the ALU to store the results to R1:R0 here. Note that
823
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
824 169 jshamlet
      when MUL_C1 =>
825 187 jshamlet
        CPU_Next_State       <= IPF_C2;
826 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
827 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
828
 
829
      when UPP_C1 =>
830 187 jshamlet
        CPU_Next_State       <= IPF_C2;
831 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
832 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
833
        ALU_Ctrl.Reg         <= SubOp_p1;
834
 
835
-------------------------------------------------------------------------------
836
-- Basic Stack Manipulation (PSH, POP, RSP)
837
-------------------------------------------------------------------------------
838
      when PSH_C1 =>
839 187 jshamlet
        CPU_Next_State       <= IPF_C1;
840 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
841
 
842
      when POP_C1 =>
843
        CPU_Next_State       <= POP_C2;
844
 
845
      when POP_C2 =>
846
        CPU_Next_State       <= POP_C3;
847 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
848 169 jshamlet
 
849
      when POP_C3 =>
850
        CPU_Next_State       <= POP_C4;
851
        Cache_Ctrl           <= CACHE_OPER1;
852 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
853 169 jshamlet
 
854
      when POP_C4 =>
855 187 jshamlet
        CPU_Next_State       <= IDC_C0;
856 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
857 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
858 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
859
        ALU_Ctrl.Reg         <= SubOp;
860 172 jshamlet
 
861 169 jshamlet
-------------------------------------------------------------------------------
862
-- Subroutines & Interrupts (RTS, JSR)
863
-------------------------------------------------------------------------------
864 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
865 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
866 186 jshamlet
        if( Int_Req = '1' )then
867
          CPU_Next_State     <= ISR_C1;
868 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
869
          --  instruction, compensating for the pipeline registers.
870 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
871
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
872
          --  operation due to the current instruction
873
          DP_Ctrl.Src        <= DATA_RD_MEM;
874
        end if;
875 169 jshamlet
 
876 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
877 225 jshamlet
        CPU_Halt_Ack         <= '1';
878 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
879
        if( CPU_Halt_Req = '0' )then
880
          CPU_Next_State     <= IPF_C0;
881
          DP_Ctrl.Src        <= DATA_RD_MEM;
882
        end if;
883
 
884
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
885
        CPU_Next_State       <= IPF_C0;
886
 
887 169 jshamlet
      when ISR_C1 =>
888
        CPU_Next_State       <= ISR_C2;
889
        INT_Ctrl.Incr_ISR    <= '1';
890
 
891
      when ISR_C2 =>
892
        CPU_Next_State       <= ISR_C3;
893
        DP_Ctrl.Src          <= DATA_WR_FLAG;
894
 
895
      when ISR_C3 =>
896
        CPU_Next_State       <= JSR_C1;
897
        Cache_Ctrl           <= CACHE_OPER1;
898 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
899 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
900 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
901
        DP_Ctrl.Src          <= DATA_WR_PC;
902 182 jshamlet
        DP_Ctrl.Reg          <= PC_MSB;
903 169 jshamlet
        Ack_D                <= '1';
904
 
905
      when JSR_C1 =>
906
        CPU_Next_State       <= JSR_C2;
907
        Cache_Ctrl           <= CACHE_OPER2;
908
        SP_Ctrl.Oper         <= SP_PUSH;
909
        DP_Ctrl.Src          <= DATA_WR_PC;
910 182 jshamlet
        DP_Ctrl.Reg          <= PC_LSB;
911 169 jshamlet
 
912
      when JSR_C2 =>
913 187 jshamlet
        CPU_Next_State       <= IPF_C0;
914 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
915 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
916 169 jshamlet
 
917
      when RTS_C1 =>
918
        CPU_Next_State       <= RTS_C2;
919
        SP_Ctrl.Oper         <= SP_POP;
920
 
921
      when RTS_C2 =>
922
        CPU_Next_State       <= RTS_C3;
923
        -- if this is an RTI, then we need to POP the flags
924
        if( SubOp = SOP_RTI )then
925
          SP_Ctrl.Oper       <= SP_POP;
926
        end if;
927
 
928
      when RTS_C3 =>
929
        CPU_Next_State       <= RTS_C4;
930
        Cache_Ctrl           <= CACHE_OPER1;
931
 
932
      when RTS_C4 =>
933
        CPU_Next_State       <= RTS_C5;
934
        Cache_Ctrl           <= CACHE_OPER2;
935
 
936
      when RTS_C5 =>
937 187 jshamlet
        CPU_Next_State       <= IPF_C0;
938 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
939 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
940 169 jshamlet
        if( SubOp = SOP_RTI )then
941
          CPU_Next_State     <= RTI_C6;
942
          Cache_Ctrl         <= CACHE_OPER1;
943 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
944
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
945 169 jshamlet
        end if;
946
 
947
      when RTI_C6 =>
948 187 jshamlet
        CPU_Next_State       <= IPF_C1;
949 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
950 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
951
 
952
      when others =>
953
        null;
954
    end case;
955
 
956
  end process;
957
 
958
-------------------------------------------------------------------------------
959
-- Registered portion of CPU finite state machine
960
-------------------------------------------------------------------------------
961 182 jshamlet
 
962 169 jshamlet
  CPU_Regs: process( Reset, Clock )
963
    variable Offset_SX       : ADDRESS_TYPE;
964 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
965 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
966
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
967
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
968
  begin
969
    if( Reset = Reset_Level )then
970 187 jshamlet
      CPU_State              <= IPF_C0;
971 169 jshamlet
      Opcode                 <= OP_INC;
972
      SubOp                  <= ACCUM;
973
      SubOp_p1               <= ACCUM;
974
      Operand1               <= x"00";
975
      Operand2               <= x"00";
976
      Instr_Prefetch         <= '0';
977
      Prefetch               <= x"00";
978
 
979 187 jshamlet
      CPU_Halt_Req           <= '0';
980 225 jshamlet
      Halt_Ack               <= '0';
981 187 jshamlet
 
982 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
983
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
984
      Open8_Bus.Rd_En        <= '1';
985 169 jshamlet
 
986
      Program_Ctr            <= Program_Start_Addr;
987
      Stack_Ptr              <= Stack_Start_Addr;
988
 
989
      Ack_Q                  <= '0';
990
      Ack_Q1                 <= '0';
991
      Int_Ack                <= '0';
992
 
993
      Int_Req                <= '0';
994
      Pending                <= x"00";
995
      Wait_for_FSM           <= '0';
996 210 jshamlet
      Wait_for_ISR           <= '0';
997 245 jshamlet
      Set_Mask               <= '0';
998 169 jshamlet
      if( Enable_NMI )then
999
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
1000
      else
1001
        Int_Mask             <= Default_Interrupt_Mask;
1002
      end if;
1003
      ISR_Addr               <= INT_VECTOR_0;
1004
 
1005
      for i in 0 to 7 loop
1006 188 jshamlet
        Regfile(i)           <= x"00";
1007 169 jshamlet
      end loop;
1008
      Flags                  <= x"00";
1009 248 jshamlet
      if( Supervisor_Mode )then
1010 244 jshamlet
        Flags(PSR_I)         <= '1';
1011
      end if;
1012 169 jshamlet
 
1013 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
1014 188 jshamlet
 
1015 169 jshamlet
    elsif( rising_edge(Clock) )then
1016 187 jshamlet
 
1017 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
1018
      Halt_Ack               <= CPU_Halt_Ack;
1019 187 jshamlet
 
1020 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1021
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1022
      Open8_Bus.Rd_En        <= '0';
1023 169 jshamlet
 
1024
-------------------------------------------------------------------------------
1025
-- Instruction/Operand caching for pipelined memory access
1026
-------------------------------------------------------------------------------
1027
      CPU_State              <= CPU_Next_State;
1028
      case Cache_Ctrl is
1029
        when CACHE_INSTR =>
1030
          Opcode             <= Rd_Data(7 downto 3);
1031
          SubOp              <= Rd_Data(2 downto 0);
1032
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
1033
          if( Instr_Prefetch = '1' )then
1034
            Opcode           <= Prefetch(7 downto 3);
1035
            SubOp            <= Prefetch(2 downto 0);
1036
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
1037
            Instr_Prefetch   <= '0';
1038
          end if;
1039
 
1040
        when CACHE_OPER1 =>
1041
          Operand1           <= Rd_Data;
1042
 
1043
        when CACHE_OPER2 =>
1044
          Operand2           <= Rd_Data;
1045
 
1046
        when CACHE_PREFETCH =>
1047
          Prefetch           <= Rd_Data;
1048
          Instr_Prefetch     <= '1';
1049
 
1050
        when CACHE_IDLE =>
1051
          null;
1052
      end case;
1053
 
1054
-------------------------------------------------------------------------------
1055
-- Program Counter
1056
-------------------------------------------------------------------------------
1057
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1058
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1059
 
1060
      case PC_Ctrl.Oper is
1061
        when PC_INCR =>
1062
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1063
 
1064
        when PC_LOAD =>
1065 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1066 169 jshamlet
 
1067
        when others =>
1068
          null;
1069
      end case;
1070
 
1071
-------------------------------------------------------------------------------
1072
-- (Write) Data Path
1073
-------------------------------------------------------------------------------
1074
      case DP_Ctrl.Src is
1075
        when DATA_BUS_IDLE =>
1076
          null;
1077
 
1078
        when DATA_RD_MEM =>
1079 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1080 169 jshamlet
 
1081
        when DATA_WR_REG =>
1082 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1083
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1084 169 jshamlet
 
1085
        when DATA_WR_FLAG =>
1086 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1087
          Open8_Bus.Wr_Data  <= Flags;
1088 169 jshamlet
 
1089
        when DATA_WR_PC =>
1090 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1091
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1092 182 jshamlet
          if( DP_Ctrl.Reg = PC_LSB )then
1093 223 jshamlet
            Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
1094 169 jshamlet
          end if;
1095
 
1096
        when others =>
1097
          null;
1098
      end case;
1099
 
1100
-------------------------------------------------------------------------------
1101
-- Stack Pointer
1102
-------------------------------------------------------------------------------
1103
      case SP_Ctrl.Oper is
1104
        when SP_IDLE =>
1105
          null;
1106
 
1107 181 jshamlet
        when SP_CLR =>
1108 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1109
 
1110 181 jshamlet
        when SP_SET =>
1111 245 jshamlet
          if( Supervisor_Mode )then
1112
            if( Flags(PSR_I) = '1' )then
1113
              Stack_Ptr      <= Regfile(1) & Regfile(0);
1114
            end if;
1115
          else
1116
            Stack_Ptr        <= Regfile(1) & Regfile(0);
1117
          end if;
1118 181 jshamlet
 
1119 169 jshamlet
        when SP_POP  =>
1120
          Stack_Ptr          <= Stack_Ptr + 1;
1121
 
1122
        when SP_PUSH =>
1123
          Stack_Ptr          <= Stack_Ptr - 1;
1124
 
1125
        when others =>
1126
          null;
1127
 
1128
      end case;
1129
 
1130
-------------------------------------------------------------------------------
1131
-- Interrupt Controller
1132
-------------------------------------------------------------------------------
1133 245 jshamlet
 
1134
      -- If Supervisor_Mode is set, restrict the SMSK instruction such that it
1135
      --  requires the I bit to be set.
1136
      if( Supervisor_Mode )then
1137
        Set_Mask             <= INT_Ctrl.Mask_Set and Flags(PSR_I);
1138
      else
1139
        Set_Mask             <= INT_Ctrl.Mask_Set;
1140
      end if;
1141
 
1142 169 jshamlet
      -- The interrupt control mask is always sourced out of R0
1143 245 jshamlet
      if( Set_Mask = '1' )then
1144 169 jshamlet
        if( Enable_NMI )then
1145
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1146
        else
1147
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1148
        end if;
1149
      end if;
1150
 
1151
      -- Combine external and internal interrupts, and mask the OR of the two
1152
      --  with the mask. Record any incoming interrupts to the pending buffer
1153
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1154
                                Int_Mask;
1155 172 jshamlet
 
1156 169 jshamlet
      Pending                <= i_Ints or Pending;
1157
 
1158 210 jshamlet
      if( Sequential_Interrupts )then
1159
        Wait_for_ISR         <= Flags(PSR_I);
1160
      else
1161
        Wait_for_ISR         <= '0';
1162
      end if;
1163
 
1164
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1165 169 jshamlet
        if(    Pending(0) = '1' )then
1166
          ISR_Addr           <= INT_VECTOR_0;
1167
          Pending(0)         <= '0';
1168
        elsif( Pending(1) = '1' )then
1169
          ISR_Addr           <= INT_VECTOR_1;
1170
          Pending(1)         <= '0';
1171
        elsif( Pending(2) = '1' )then
1172
          ISR_Addr           <= INT_VECTOR_2;
1173
          Pending(2)         <= '0';
1174
        elsif( Pending(3) = '1' )then
1175
          ISR_Addr           <= INT_VECTOR_3;
1176
          Pending(3)         <= '0';
1177
        elsif( Pending(4) = '1' )then
1178
          ISR_Addr           <= INT_VECTOR_4;
1179
          Pending(4)         <= '0';
1180
        elsif( Pending(5) = '1' )then
1181
          ISR_Addr           <= INT_VECTOR_5;
1182
          Pending(5)         <= '0';
1183
        elsif( Pending(6) = '1' )then
1184
          ISR_Addr           <= INT_VECTOR_6;
1185
          Pending(6)         <= '0';
1186
        elsif( Pending(7) = '1' )then
1187
          ISR_Addr           <= INT_VECTOR_7;
1188
          Pending(7)         <= '0';
1189
        end if;
1190 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1191 169 jshamlet
      end if;
1192
 
1193
      -- Reset the Wait_for_FSM flag on Int_Ack
1194
      Ack_Q                  <= Ack_D;
1195
      Ack_Q1                 <= Ack_Q;
1196
      Int_Ack                <= Ack_Q1;
1197
      if( Int_Ack = '1' )then
1198
        Wait_for_FSM         <= '0';
1199
      end if;
1200
 
1201
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1202
 
1203
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1204
      --  lower half of the address.
1205
      if( INT_Ctrl.Incr_ISR = '1' )then
1206
        ISR_Addr             <= ISR_Addr + 1;
1207
      end if;
1208
 
1209
-------------------------------------------------------------------------------
1210
-- ALU (Arithmetic / Logic Unit)
1211
-------------------------------------------------------------------------------
1212
      Index                  := conv_integer(ALU_Ctrl.Reg);
1213
      Sum                    := (others => '0');
1214
      Temp                   := (others => '0');
1215
 
1216
      case ALU_Ctrl.Oper is
1217
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1218
          Sum                := ("0" & x"01") +
1219
                                ("0" & Regfile(Index));
1220 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1221
          Flags(PSR_C)       <= Sum(8);
1222 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1223 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1224
 
1225
        when ALU_UPP => -- Rn = Rn + 1
1226
          Sum                := ("0" & x"01") +
1227
                                ("0" & Regfile(Index));
1228 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1229 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1230
 
1231
        when ALU_UPP2 => -- Rn = Rn + C
1232
          Sum                := ("0" & x"00") +
1233
                                ("0" & Regfile(Index)) +
1234 185 jshamlet
                                Flags(PSR_C);
1235
          Flags(PSR_C)       <= Sum(8);
1236 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1237
 
1238
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1239
          Sum                := ("0" & Regfile(0)) +
1240
                                ("0" & Regfile(Index)) +
1241 185 jshamlet
                                Flags(PSR_C);
1242
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1243
          Flags(PSR_C)       <= Sum(8);
1244
          Flags(PSR_N)       <= Sum(7);
1245 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1246
 
1247
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1248
          Temp               := "0" & Regfile(Index);
1249 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1250
          Flags(PSR_N)       <= Temp(7);
1251 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1252
 
1253
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1254
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1255 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1256
          Flags(PSR_N)       <= Temp(7);
1257 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1258
 
1259
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1260
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1261 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1262
          Flags(PSR_N)       <= Temp(7);
1263 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1264
 
1265
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1266
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1267 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1268
          Flags(PSR_N)       <= Temp(7);
1269 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1270
 
1271
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1272 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1273
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1274
          Flags(PSR_C)       <= Temp(8);
1275
          Flags(PSR_N)       <= Temp(7);
1276 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1277
 
1278
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1279 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1280 169 jshamlet
                                Regfile(Index)(7 downto 1);
1281 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1282
          Flags(PSR_C)       <= Temp(8);
1283
          Flags(PSR_N)       <= Temp(7);
1284 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1285
 
1286
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1287
          Sum                := ("0" & Regfile(Index)) +
1288
                                ("0" & x"FF");
1289 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1290
          Flags(PSR_C)       <= Sum(8);
1291
          Flags(PSR_N)       <= Sum(7);
1292 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1293
 
1294
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1295
          Sum                := ("0" & Regfile(0)) +
1296
                                ("1" & (not Regfile(Index))) +
1297 185 jshamlet
                                Flags(PSR_C);
1298
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1299
          Flags(PSR_C)       <= Sum(8);
1300
          Flags(PSR_N)       <= Sum(7);
1301 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1302
 
1303
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1304
          Sum                := ("0" & Regfile(0)) +
1305
                                ("0" & Regfile(Index));
1306 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1307 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1308 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1309
          Flags(PSR_N)       <= Sum(7);
1310 169 jshamlet
 
1311
        when ALU_STP => -- Sets bit(n) in the Flags register
1312
          Flags(Index)       <= '1';
1313
 
1314
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1315 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1316
          Flags(PSR_N)       <= Regfile(0)(7);
1317 169 jshamlet
 
1318
        when ALU_CLP => -- Clears bit(n) in the Flags register
1319
          Flags(Index)       <= '0';
1320
 
1321
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1322
          Temp               := "0" & Regfile(0);
1323 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1324
          Flags(PSR_N)       <= Temp(7);
1325 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1326
 
1327
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1328
          Sum                := ("0" & Regfile(0)) +
1329
                                ("1" & (not Regfile(Index))) +
1330
                                '1';
1331 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1332
          Flags(PSR_C)       <= Sum(8);
1333
          Flags(PSR_N)       <= Sum(7);
1334 169 jshamlet
 
1335
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1336
          Regfile(0)         <= Mult(7 downto 0);
1337
          Regfile(1)         <= Mult(15 downto 8);
1338 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1339 169 jshamlet
 
1340
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1341 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1342
          Flags(PSR_N)       <= Operand1(7);
1343
          Regfile(Index)     <= Operand1;
1344 169 jshamlet
 
1345
        when ALU_POP => -- Rn <= Data
1346 185 jshamlet
          Regfile(Index)     <= Operand1;
1347 169 jshamlet
 
1348
        when ALU_RFLG =>
1349 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1350
          if( not RTI_Ignores_GP_Flags )then
1351
            Flags(7 downto 4)<= Operand1(7 downto 4);
1352
          end if;
1353 169 jshamlet
 
1354 185 jshamlet
        when ALU_RSP =>
1355 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1356
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1357
 
1358 185 jshamlet
        when ALU_GMSK =>
1359
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1360
          Regfile(0)         <= Int_Mask;
1361
 
1362 169 jshamlet
        when others =>
1363
          null;
1364
      end case;
1365
 
1366 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1367 188 jshamlet
 
1368 169 jshamlet
    end if;
1369
  end process;
1370
 
1371 182 jshamlet
-------------------------------------------------------------------------------
1372
-- Multiplier Logic
1373
--
1374
-- We need to infer a hardware multipler, so we create a special clocked
1375
--  process with no reset or clock enable
1376
-------------------------------------------------------------------------------
1377
 
1378
  Multiplier_proc: process( Clock )
1379
  begin
1380
    if( rising_edge(Clock) )then
1381
      Mult                   <= Regfile(0) *
1382 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1383
    end if;
1384
  end process;
1385
 
1386
end architecture;

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