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1 185 jshamlet
-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
2 169 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
24 181 jshamlet
-- VHDL Units :  o8_cpu
25 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44
--            :   specified by Stack_Xfer_Flag. If the flag is '0', RSP will
45
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 181 jshamlet
--            :  Stack_Xfer_Flag instructs the core to use the specified ALU
52
--            :   flag to alter the behavior of the RSP instruction when
53
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it is ignored.
54
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
74
--            :   after an interrupt. By default, all of the flag bits are put
75
--            :   back to their original state. If this flag is set true, only
76
--            :   the lower four bits are restored, allowing ISR code to alter
77
--            :   the GP flags persistently.
78
--            :
79 244 jshamlet
--            :  Supervisor_Mode, when set, disables the STP PSR_I instruction
80
--            :   preventing code from setting the I bit. When enabled, only
81
--            :   interrupts can set the I bit, allowing for more robust memory
82
--            :   protection by preventing errant code execution from
83
--            :   inadvertently entering an interrupt state.
84
--            :
85 248 jshamlet
--            :   This setting also sets I bit at startup so that any
86
--            :   initialization code may be run in an ISR context, initially
87
--            :   bypassing memory protection. Init code should clear the I bit
88
--            :   when done;
89 244 jshamlet
--            :
90 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
91
--            :   interrupt mask. To remain true to the original core, which
92
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
93
--            :   it can be initialized to any value. Note that Enable_NMI
94
--            :   will logically force the LSB high.
95 172 jshamlet
--            :
96 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
97
--            :   on a high or low level from higher logic.
98
--            :
99
--            : Architecture notes
100
--            :  This model deviates from the original ISA in a few important
101
--            :   ways.
102
--            :
103
--            :  First, there is only one set of registers. Interrupt service
104
--            :   routines must explicitely preserve context since the the
105
--            :   hardware doesn't. This was done to decrease size and code
106
--            :   complexity. Older code that assumes this behavior will not
107
--            :   execute correctly on this processor model.
108
--            :
109
--            :  Second, this model adds an additional pipeline stage between
110
--            :   the instruction decoder and the ALU. Unfortunately, this
111
--            :   means that the instruction stream has to be restarted after
112
--            :   any math instruction is executed, implying that any ALU
113
--            :   instruction now has a latency of 2 instead of 0. The
114
--            :   advantage is that the maximum frequency has gone up
115
--            :   significantly, as the ALU code is vastly more efficient.
116
--            :   As an aside, this now means that all math instructions,
117
--            :   including MUL (see below) and UPP have the same instruction
118
--            :   latency.
119
--            :
120
--            :  Third, the original ISA, also a soft core, had two reserved
121
--            :   instructions, USR and USR2. These have been implemented as
122
--            :   DBNZ, and MUL respectively.
123
--            :
124
--            :  DBNZ decrements the specified register and branches if the
125
--            :   result is non-zero. The instruction effectively executes a
126
--            :   DEC Rn instruction prior to branching, so the same flags will
127
--            :   be set.
128
--            :
129
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
130
--            :   latency is identical to other ALU instructions. Only the Z
131
--            :   flag is set, since there is no defined overflow or "negative
132
--            :   16-bit values"
133
--            :
134
--            :  Fourth, indexed load/store instructions now have an (optional)
135
--            :   ability to post-increment their index registers. If enabled,
136
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
137
--            :   register pair to be incremented after the storage access.
138
--            :
139
--            :  Fifth, the RSP instruction has been (optionally) altered to
140
--            :   allow the stack pointer to be sourced from R1:R0.
141
--            :
142
--            :  Sixth, the BRK instruction can optionally implement a WAI,
143
--            :   which is the same as the INT instruction without the soft
144
--            :   interrupt, as a way to put the processor to "sleep" until the
145
--            :   next external interrupt.
146
--            :
147
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
148
--            :   with priority. This model has the same 8 interrupts, but
149 172 jshamlet
--            :   allows software to mask them (with an additional option to
150 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
151
--            :
152
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
153
--            :   were repurposed to support a new interrupt mask.
154
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
155
--            :   to/from the interrupt mask register. SMSK is immediate, while
156
--            :   GMSK has the same overhead as a math instruction.
157
--
158
-- Revision History
159
-- Author          Date     Change
160
------------------ -------- ---------------------------------------------------
161
-- Seth Henry      07/19/06 Design Start
162
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
163
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
164
--                           corruption issues.
165
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
166
--                           path sections.
167
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
168
--                           single entity.
169
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
170
--                           processor to wait for an interrupt instead of the
171
--                           normal BRK behavior.
172 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
173 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
174
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
175
--                           faster logic that simply does priority encoding.
176
-- Seth Henry      08/06/13 Removed HALT functionality
177
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
178 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
179 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
180
--                           allowing true backup/restore of the stack pointer
181 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
182
--                           in order to simplify things and eliminate
183
--                           redundancies. Came across and fixed a problem with
184
--                           the STO instruction when Enable_Auto_Increment is
185
--                           NOT set.
186 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
187
--                           the assembler names. Also fixed an issue where
188
--                           the I bit wasn't being cleared after interrupts.
189
--                          Simplified the program counter logic to only use
190
--                           the offset for increments, redefining the
191
--                           original modes as fixed offset values.
192
--                          Modified the ALU section with a new ALU operation
193
--                           for GMSK. This allowed the .data field to be
194
--                           removed and Operand1 used in its place, which
195
--                           simplified the logic a great deal.
196 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
197
--                           the instruction decode state, where it acts as a
198
--                           modified form of the BRK instruction that holds
199
--                           state until CPU_Halt is deasserted. This has a
200
--                           much smaller impact on Fmax/complexity than the
201
--                           original clock enable, but imposes a mild impact
202
--                           due to the need to reset the instruction pipeline
203 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
204
--                           the flags, including the general purpose ones, or
205
--                           only the core ALU flags (Z, N, and C). Also
206
--                           brought out copies of the GP flags for external
207
--                           connection.
208 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
209
--                           while the I bit is set to avoid reentering ISRs
210
--                           This may slightly affect timing, as this will
211
--                           potentially block higher priority interrupts
212
--                           until the lower priority ISR returns or clears
213
--                           the I bit.
214
--                          Also added the I bit to the exported flags for
215
--                           use in memory protection schemes.
216 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
217 225 jshamlet
--                           reset and usec_tick logic to drive utility
218
--                           signals. Also added Halt_Ack output.
219 244 jshamlet
-- Seth Henry      05/20/20 Added two new generics to alter the way the I bit
220
--                           is handled. The Supervisor_Mode setting disables
221
--                           STP PSR_I from being executed, preventing it
222
--                           from being set outside of an ISR. The
223
--                           Default_Int_Flag setting allows the I bit to
224
--                           start set so that initialization code can run,
225
--                           but not be hijacked later to corrupt any memory
226
--                           write protection later.
227 245 jshamlet
-- Seth Henry      05/21/20 Supervisor_Mode now protects the interrupt mask
228
--                           and stack pointer as well.
229 248 jshamlet
-- Seth Henry      05/24/20 Removed the Default_Int_Flag, as it is covered by
230
--                           Supervisor_Mode. If Supervisor_Mode isn't set,
231
--                           code can simply use STP to set the bit
232 252 jshamlet
-- Seth Henry      06/09/20 Added ability to use unsigned index offsets for
233
--                           LDO/SDO. Also pipelined the address calculation
234
--                           for indexed instructions, reducing the final
235
--                           address generator to a multiplexor fed only by
236
--                           registers.
237 169 jshamlet
 
238
library ieee;
239
  use ieee.std_logic_1164.all;
240
  use ieee.std_logic_unsigned.all;
241
  use ieee.std_logic_arith.all;
242
  use ieee.std_logic_misc.all;
243
 
244
library work;
245 227 jshamlet
  use work.Open8_pkg.all;
246 169 jshamlet
 
247 183 jshamlet
entity o8_cpu is
248 169 jshamlet
  generic(
249
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
250
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
251
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
252
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
253 188 jshamlet
    Stack_Xfer_Flag          : integer      := PSR_GP4; -- GP4 modifies RSP
254 169 jshamlet
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
255
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
256
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
257 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
258 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
259 244 jshamlet
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
260 252 jshamlet
    Unsigned_Index_Offsets   : boolean      := false;   -- Offsets are signed
261 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
262 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
263
);
264 169 jshamlet
  port(
265
    Clock                    : in  std_logic;
266 224 jshamlet
    PLL_Locked               : in  std_logic;
267 169 jshamlet
    --
268 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
269
    Halt_Ack                 : out std_logic;
270
    --
271 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
272 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
273 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
274
);
275 169 jshamlet
end entity;
276
 
277 183 jshamlet
architecture behave of o8_cpu is
278 169 jshamlet
 
279 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
280
  signal Reset               : std_logic := Reset_Level;
281
 
282
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
283
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
284
  constant USEC_DLY          : std_logic_vector :=
285
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
286
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
287
  signal uSec_Tick           : std_logic;
288
 
289 169 jshamlet
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;
290
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;
291
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;
292
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;
293
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;
294
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;
295
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;
296
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;
297
 
298 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
299
  signal CPU_State           : CPU_STATES := IPF_C0;
300 169 jshamlet
 
301 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
302
  signal CPU_Halt_Ack        : std_logic := '0';
303 187 jshamlet
 
304 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
305
 
306
  signal Opcode              : OPCODE_TYPE := (others => '0');
307
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
308
 
309
  signal Prefetch            : DATA_TYPE   := x"00";
310
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
311
 
312
  signal Instr_Prefetch      : std_logic   := '0';
313
 
314
  signal PC_Ctrl             : PC_CTRL_TYPE;
315
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
316
 
317 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
318
  signal Regfile             : REGFILE_TYPE;
319
  signal Flags               : FLAG_TYPE;
320
  signal Mult                : ADDRESS_TYPE := x"0000";
321
 
322 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
323
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
324
 
325
  signal DP_Ctrl             : DATA_CTRL_TYPE;
326
 
327
  signal INT_Ctrl            : INT_CTRL_TYPE;
328
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
329
  signal Int_Req, Int_Ack    : std_logic   := '0';
330 245 jshamlet
  signal Set_Mask            : std_logic   := '0';
331 169 jshamlet
  signal Int_Mask            : DATA_TYPE   := x"00";
332
  signal ISR_Addr            : ADDRESS_TYPE := x"0000";
333
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
334
  signal Pending             : INTERRUPT_BUNDLE := x"00";
335
  signal Wait_for_FSM        : std_logic := '0';
336 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
337 169 jshamlet
 
338 252 jshamlet
  signal IDX_Offset          : ADDRESS_TYPE := x"0000";
339
 
340
  signal IDX_Reg_l           : integer := 0;
341
  signal IDX_Reg_h           : integer := 0;
342
 
343
  signal IDX_NoOffset_Calc   : ADDRESS_TYPE := x"0000";
344
  signal IDX_Offset_Calc     : ADDRESS_TYPE := x"0000";
345
 
346 169 jshamlet
begin
347
 
348 224 jshamlet
-------------------------------------------------------------------------------
349
-- Reset & uSec Tick
350
-------------------------------------------------------------------------------
351 185 jshamlet
 
352 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
353
  begin
354
    if( PLL_Locked = '0' )then
355
      Reset_q                <= Reset_Level;
356
      Reset                  <= Reset_Level;
357
    elsif( rising_edge(Clock) )then
358
      Reset_q                <= not Reset_Level;
359
      Reset                  <= Reset_q;
360
    end if;
361
  end process;
362
 
363
  uSec_Tick_proc: process( Clock, Reset )
364
  begin
365
    if( Reset = Reset_Level )then
366
      uSec_Cntr              <= USEC_DLY;
367
      uSec_Tick              <= '0';
368
    elsif( rising_edge( Clock ) )then
369
      uSec_Cntr              <= uSec_Cntr - 1;
370
      if( or_reduce(uSec_Cntr) = '0' )then
371
        uSec_Cntr            <= USEC_DLY;
372
      end if;
373
      uSec_Tick              <= nor_reduce(uSec_Cntr);
374
    end if;
375
  end process;
376
 
377
  Open8_Bus.Clock            <= Clock;
378
  Open8_Bus.Reset            <= Reset;
379
  Open8_Bus.uSec_Tick        <= uSec_Tick;
380
 
381 169 jshamlet
-------------------------------------------------------------------------------
382 182 jshamlet
-- Address bus selection/generation logic
383 169 jshamlet
-------------------------------------------------------------------------------
384
 
385 252 jshamlet
  -- The original model treated the offset to LDO/STO as a signed value
386
  --  allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't
387
  --  always helpful, so the generic allows the CPU to use unsigned math
388
  --  for the offsets. This makes the range 0 to +255 instead.
389
Unsigned_Idx_Offsets : if( Unsigned_Index_Offsets )generate
390
  IDX_Offset(15 downto 8)    <= (others => '0');
391
  IDX_Offset(7 downto 0)     <= Operand1;
392
end generate;
393
 
394
Signed_Idx_Offsets: if( not Unsigned_Index_Offsets )generate
395
  IDX_Offset(15 downto 8)    <= (others => Operand1(7));
396
  IDX_Offset(7 downto 0)     <= Operand1;
397
end generate;
398
 
399
  -- Enable_Auto_Increment uses the LSB to determine whether or not to
400
  --  do the auto-increment, so we need to lock the LSB for each operand
401
  --  if it is enabled. This forces [ODD:EVEN] pairing.
402
 
403
Auto_Incr_Set: if( Enable_Auto_Increment )generate
404
  IDX_Reg_l                  <= conv_integer(SubOp(2 downto 1) & '0');
405
  IDX_Reg_h                  <= conv_integer(SubOp(2 downto 1) & '1');
406
end generate;
407
 
408
Auto_Incr_Not_Set: if( not Enable_Auto_Increment )generate
409
  IDX_Reg_l                  <= conv_integer(SubOp);
410
  IDX_Reg_h                  <= conv_integer(SubOp_p1);
411
end generate;
412
 
413
  -- Pipeline registers for the indexed and indexed with offset addresses.
414
  Idx_Addr_Calc_proc: process( Clock, Reset )
415 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
416
  begin
417 252 jshamlet
    if( Reset = Reset_Level )then
418
      IDX_NoOffset_Calc      <= x"0000";
419
      IDX_Offset_Calc        <= x"0000";
420
    elsif( rising_edge(Clock))then
421
      IDX_NoOffset_Calc      <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l));
422
      IDX_Offset_Calc        <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) +
423
                                IDX_Offset;
424 182 jshamlet
    end if;
425 252 jshamlet
  end process;
426 182 jshamlet
 
427 252 jshamlet
  -- Address selection logic based on current CPU state. This is combinatorial,
428
  --  as adding pipeline registration would add a clock cycle to every instr,
429
  --  without really adding the Fmax to compensate.
430
  Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
431
                         IDX_Offset_Calc, ISR_Addr, Stack_Ptr, Program_Ctr )
432
  begin
433 182 jshamlet
    case( CPU_State )is
434
 
435
      when LDA_C2 | STA_C2 =>
436 223 jshamlet
        Open8_Bus.Address    <= Operand2 & Operand1;
437 182 jshamlet
 
438
      when LDX_C1 | STX_C1 =>
439 252 jshamlet
        Open8_Bus.Address    <= IDX_NoOffset_Calc;
440 182 jshamlet
 
441 252 jshamlet
      when LDO_C2 | STO_C2 =>
442
        Open8_Bus.Address    <= IDX_Offset_Calc;
443 182 jshamlet
 
444
      when ISR_C1 | ISR_C2 =>
445 223 jshamlet
        Open8_Bus.Address    <= ISR_Addr;
446 182 jshamlet
 
447
      when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
448 223 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
449 182 jshamlet
 
450
      when others =>
451 223 jshamlet
        Open8_Bus.Address    <= Program_Ctr;
452 182 jshamlet
 
453
    end case;
454
  end process;
455
 
456
-------------------------------------------------------------------------------
457
-- Combinatorial portion of CPU finite state machine
458
-- State Logic / Instruction Decoding & Execution
459
-------------------------------------------------------------------------------
460
 
461 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
462 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
463
    variable Reg             : integer range 0 to 7 := 0;
464
  begin
465 169 jshamlet
    CPU_Next_State           <= CPU_State;
466
    Cache_Ctrl               <= CACHE_IDLE;
467
    --
468 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
469
    PC_Ctrl.Offset           <= PC_IDLE;
470 182 jshamlet
    --
471 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
472
    ALU_Ctrl.Reg             <= ACCUM;
473
    --
474
    SP_Ctrl.Oper             <= SP_IDLE;
475
    --
476
    DP_Ctrl.Src              <= DATA_RD_MEM;
477
    DP_Ctrl.Reg              <= ACCUM;
478
    --
479
    INT_Ctrl.Mask_Set        <= '0';
480
    INT_Ctrl.Soft_Ints       <= x"00";
481
    INT_Ctrl.Incr_ISR        <= '0';
482
    Ack_D                    <= '0';
483 225 jshamlet
    --
484 182 jshamlet
    Reg                     := conv_integer(SubOp);
485 225 jshamlet
    --
486
    CPU_Halt_Ack             <= '0';
487 169 jshamlet
 
488
    case CPU_State is
489
-------------------------------------------------------------------------------
490
-- Initial Instruction fetch & decode
491
-------------------------------------------------------------------------------
492 187 jshamlet
      when IPF_C0 =>
493
        CPU_Next_State       <= IPF_C1;
494 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
495 169 jshamlet
 
496 187 jshamlet
      when IPF_C1 =>
497
        CPU_Next_State       <= IPF_C2;
498 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
499 169 jshamlet
 
500 187 jshamlet
      when IPF_C2 =>
501
        CPU_Next_State       <= IDC_C0;
502 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
503 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
504 169 jshamlet
 
505 187 jshamlet
      when IDC_C0 =>
506
        CPU_Next_State       <= IDC_C0;
507 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
508
 
509
        case Opcode is
510
          when OP_PSH =>
511
            CPU_Next_State   <= PSH_C1;
512
            Cache_Ctrl       <= CACHE_PREFETCH;
513 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
514 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
515
            DP_Ctrl.Reg      <= SubOp;
516
 
517
          when OP_POP =>
518
            CPU_Next_State   <= POP_C1;
519
            Cache_Ctrl       <= CACHE_PREFETCH;
520 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
521 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
522
 
523
          when OP_BR0 | OP_BR1 =>
524
            CPU_Next_State   <= BRN_C1;
525
            Cache_Ctrl       <= CACHE_OPER1;
526 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
527 169 jshamlet
 
528 185 jshamlet
 
529 169 jshamlet
          when OP_DBNZ =>
530
            CPU_Next_State   <= DBNZ_C1;
531
            Cache_Ctrl       <= CACHE_OPER1;
532 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
533 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
534
            ALU_Ctrl.Reg     <= SubOp;
535
 
536
          when OP_INT =>
537 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
538 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
539
            --  Also, unlike CPU_Halt, the INT instruction is actually being
540
            --  executed, so go ahead and increment the program counter before
541
            --  pausing so the CPU restarts on the next instruction.
542 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
543 187 jshamlet
              CPU_Next_State <= WAI_Cx;
544 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
545
            end if;
546
 
547
          when OP_STK =>
548
            case SubOp is
549
              when SOP_RSP  =>
550 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
551 181 jshamlet
                if( not Allow_Stack_Address_Move )then
552 187 jshamlet
                  -- The default behavior for this instruction is to simply
553
                  --  repoint the SP to the HDL default
554 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
555 181 jshamlet
                end if;
556 187 jshamlet
                if( Allow_Stack_Address_Move and
557
                    Flags(Stack_Xfer_Flag) = '1' )then
558
                  -- If RSP is set to allow SP moves, and the specified flag
559
                  --  is true, then signal the stack pointer logic to load
560
                  --  from R1:R0
561 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
562 181 jshamlet
                end if;
563 187 jshamlet
                if( Allow_Stack_Address_Move and
564
                    Flags(Stack_Xfer_Flag) = '0')then
565
                  -- If RSP is set to allow SP moves, and the specified flag
566
                  --  is false, then signal the ALU to copy the stack pointer
567
                  --  to R1:R0
568 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
569 181 jshamlet
                end if;
570 169 jshamlet
 
571
              when SOP_RTS | SOP_RTI =>
572 185 jshamlet
                CPU_Next_State    <= RTS_C1;
573 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
574 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
575 169 jshamlet
 
576
              when SOP_BRK  =>
577
                if( BRK_Implements_WAI )then
578 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
579
                  --  increment the PC similar to an ISR flow.
580
                  CPU_Next_State  <= WAI_Cx;
581 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
582 187 jshamlet
                else
583
                -- If Break is implemented normally, back the PC up by
584
                --  2 and return through IPF_C0 in order to execute a 5
585
                --  clock cycle delay
586
                  CPU_Next_State  <= BRK_C1;
587
                  PC_Ctrl.Offset  <= PC_REV2;
588 169 jshamlet
                end if;
589
 
590
              when SOP_JMP  =>
591 185 jshamlet
                CPU_Next_State    <= JMP_C1;
592
                Cache_Ctrl        <= CACHE_OPER1;
593 169 jshamlet
 
594
              when SOP_SMSK =>
595 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
596 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
597
 
598
              when SOP_GMSK =>
599 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
600
                ALU_Ctrl.Oper     <= ALU_GMSK;
601 169 jshamlet
 
602
              when SOP_JSR =>
603
                CPU_Next_State <= JSR_C1;
604 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
605
                DP_Ctrl.Src       <= DATA_WR_PC;
606
                DP_Ctrl.Reg       <= PC_MSB;
607 169 jshamlet
 
608
              when others => null;
609
            end case;
610
 
611
          when OP_MUL =>
612
            CPU_Next_State   <= MUL_C1;
613 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
614
            --  to the ALU writing the result to registers. As a result, this
615
            --  state needs to idle the ALU initially, and back the PC up by 1
616
            -- We can get away with only 1 extra clock by pre-fetching the
617
            --  next instruction, though.
618 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
619 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
620 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
621
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
622
            --  now, but hold off on the ALU command until the next state.
623 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
624
            ALU_Ctrl.Reg     <= SubOp;
625
 
626
          when OP_UPP =>
627
            CPU_Next_State   <= UPP_C1;
628
            Cache_Ctrl       <= CACHE_PREFETCH;
629 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
630 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
631
            ALU_Ctrl.Reg     <= SubOp;
632
 
633
          when OP_LDA =>
634
            CPU_Next_State   <= LDA_C1;
635
            Cache_Ctrl       <= CACHE_OPER1;
636
 
637
          when OP_LDI =>
638
            CPU_Next_State   <= LDI_C1;
639
            Cache_Ctrl       <= CACHE_OPER1;
640 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
641 169 jshamlet
 
642
          when OP_LDO =>
643
            CPU_Next_State   <= LDO_C1;
644
            Cache_Ctrl       <= CACHE_OPER1;
645 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
646 169 jshamlet
 
647
          when OP_LDX =>
648
            CPU_Next_State   <= LDX_C1;
649 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
650 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
651 169 jshamlet
 
652
          when OP_STA =>
653
            CPU_Next_State   <= STA_C1;
654
            Cache_Ctrl       <= CACHE_OPER1;
655
 
656
          when OP_STO =>
657
            CPU_Next_State   <= STO_C1;
658
            Cache_Ctrl       <= CACHE_OPER1;
659 252 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
660 169 jshamlet
 
661
          when OP_STX =>
662
            CPU_Next_State   <= STX_C1;
663
            Cache_Ctrl       <= CACHE_PREFETCH;
664 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
665 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
666
            DP_Ctrl.Reg      <= ACCUM;
667
 
668 244 jshamlet
          when OP_STP =>
669
            PC_Ctrl.Offset   <= PC_NEXT;
670
            if( Supervisor_Mode )then
671
              if( SubOp /= PSR_I )then
672
                ALU_Ctrl.Oper  <= Opcode;
673
                ALU_Ctrl.Reg   <= SubOp;
674
              end if;
675
            else
676
              ALU_Ctrl.Oper  <= Opcode;
677
              ALU_Ctrl.Reg   <= SubOp;
678
            end if;
679
 
680 169 jshamlet
          when others =>
681 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
682 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
683
            ALU_Ctrl.Reg     <= SubOp;
684
 
685
        end case;
686
 
687 186 jshamlet
        if( Int_Req = '1' )then
688
          CPU_Next_State     <= ISR_C1;
689 187 jshamlet
        end if;
690
 
691
        if( CPU_Halt_Req = '1' )then
692
          CPU_Next_State     <= WAH_Cx;
693
        end if;
694
 
695
        -- If either of these override conditions are true, the decoder needs
696
        --  to undo everything it just setup, since even "single-cycle"
697
        --  instructions will be executed again upon return.
698
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
699
          -- In either case, we want to skip loading the cache, as the cache
700
          --  will be invalid by the time we get back.
701 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
702 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
703
          -- compensating for the pipeline registers.
704 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
705
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
706 187 jshamlet
          --  operation due to the current instruction.
707 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
708
          SP_Ctrl.Oper       <= SP_IDLE;
709 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
710
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
711 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
712 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
713
          --  executed again when normal processing resumes, so axe their
714
          --  requests for now.
715
          INT_Ctrl.Mask_Set       <= '0';
716
          INT_Ctrl.Soft_Ints(Reg) <= '0';
717 186 jshamlet
        end if;
718
 
719 169 jshamlet
-------------------------------------------------------------------------------
720
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
721
-------------------------------------------------------------------------------
722
 
723
      when BRN_C1 =>
724 187 jshamlet
        CPU_Next_State       <= IDC_C0;
725 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
726 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
727 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
728 187 jshamlet
          CPU_Next_State     <= IPF_C0;
729 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
730
          PC_Ctrl.Offset     <= Operand1;
731
        end if;
732
 
733
      when DBNZ_C1 =>
734 187 jshamlet
        CPU_Next_State       <= IDC_C0;
735 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
736 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
737
        if( Flags(PSR_Z) = '0' )then
738 187 jshamlet
          CPU_Next_State     <= IPF_C0;
739 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
740
          PC_Ctrl.Offset     <= Operand1;
741
        end if;
742
 
743
      when JMP_C1 =>
744
        CPU_Next_State       <= JMP_C2;
745
        Cache_Ctrl           <= CACHE_OPER2;
746
 
747
      when JMP_C2 =>
748 187 jshamlet
        CPU_Next_State       <= IPF_C0;
749 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
750
 
751
-------------------------------------------------------------------------------
752
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
753
-------------------------------------------------------------------------------
754
 
755
      when LDA_C1 =>
756
        CPU_Next_State       <= LDA_C2;
757
        Cache_Ctrl           <= CACHE_OPER2;
758
 
759
      when LDA_C2 =>
760
        CPU_Next_State       <= LDA_C3;
761
 
762
      when LDA_C3 =>
763
        CPU_Next_State       <= LDA_C4;
764 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
765 169 jshamlet
 
766
      when LDA_C4 =>
767
        CPU_Next_State       <= LDI_C1;
768
        Cache_Ctrl           <= CACHE_OPER1;
769 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
770 169 jshamlet
 
771
      when LDI_C1 =>
772 187 jshamlet
        CPU_Next_State       <= IDC_C0;
773 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
774 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
775 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
776
        ALU_Ctrl.Reg         <= SubOp;
777
 
778
      when LDO_C1 =>
779 252 jshamlet
        CPU_Next_State       <= LDO_C2;
780
 
781
      when LDO_C2 =>
782 181 jshamlet
        CPU_Next_State       <= LDX_C2;
783 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
784 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
785
          ALU_Ctrl.Oper      <= ALU_UPP;
786
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
787 169 jshamlet
        end if;
788
 
789
      when LDX_C1 =>
790
        CPU_Next_State       <= LDX_C2;
791 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
792
          ALU_Ctrl.Oper      <= ALU_UPP;
793
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
794 181 jshamlet
        end if;
795 169 jshamlet
 
796
      when LDX_C2 =>
797
        CPU_Next_State       <= LDX_C3;
798 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
799 181 jshamlet
 
800
      when LDX_C3 =>
801
        CPU_Next_State       <= LDX_C4;
802 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
803 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
804 169 jshamlet
 
805 181 jshamlet
      when LDX_C4 =>
806 187 jshamlet
        CPU_Next_State       <= IDC_C0;
807 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
808 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
809 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
810 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
811
 
812
-------------------------------------------------------------------------------
813
-- Data Storage - Store to memory (STA, STO, STX)
814
-------------------------------------------------------------------------------
815
      when STA_C1 =>
816
        CPU_Next_State       <= STA_C2;
817
        Cache_Ctrl           <= CACHE_OPER2;
818
        DP_Ctrl.Src          <= DATA_WR_REG;
819
        DP_Ctrl.Reg          <= SubOp;
820
 
821
      when STA_C2 =>
822
        CPU_Next_State       <= STA_C3;
823 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
824 169 jshamlet
 
825
      when STA_C3 =>
826 187 jshamlet
        CPU_Next_State       <= IPF_C2;
827 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
828 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
829 169 jshamlet
 
830
      when STO_C1 =>
831 252 jshamlet
        CPU_Next_State       <= STO_C2;
832 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
833 252 jshamlet
        DP_Ctrl.Src          <= DATA_WR_REG;
834
        DP_Ctrl.Reg          <= ACCUM;
835
 
836
      when STO_C2 =>
837
        CPU_Next_State       <= IPF_C1;
838 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
839 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
840 252 jshamlet
          CPU_Next_State     <= STO_C3;
841 182 jshamlet
          ALU_Ctrl.Oper      <= ALU_UPP;
842
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
843 169 jshamlet
        end if;
844
 
845 252 jshamlet
      when STO_C3 =>
846
        CPU_Next_State       <= IPF_C2;
847 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
848 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
849
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
850
 
851
      when STX_C1 =>
852 187 jshamlet
        CPU_Next_State       <= IPF_C1;
853 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
854 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
855
          CPU_Next_State     <= STX_C2;
856
          ALU_Ctrl.Oper      <= ALU_UPP;
857
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
858 169 jshamlet
        end if;
859
 
860
      when STX_C2 =>
861 187 jshamlet
        CPU_Next_State       <= IPF_C2;
862 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
863 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
864
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
865
 
866
-------------------------------------------------------------------------------
867
-- Multi-Cycle Math Operations (UPP, MUL)
868
-------------------------------------------------------------------------------
869
 
870
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
871 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
872
      --  need to tell the ALU to store the results to R1:R0 here. Note that
873
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
874 169 jshamlet
      when MUL_C1 =>
875 187 jshamlet
        CPU_Next_State       <= IPF_C2;
876 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
877 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
878
 
879
      when UPP_C1 =>
880 187 jshamlet
        CPU_Next_State       <= IPF_C2;
881 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
882 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
883
        ALU_Ctrl.Reg         <= SubOp_p1;
884
 
885
-------------------------------------------------------------------------------
886
-- Basic Stack Manipulation (PSH, POP, RSP)
887
-------------------------------------------------------------------------------
888
      when PSH_C1 =>
889 187 jshamlet
        CPU_Next_State       <= IPF_C1;
890 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
891
 
892
      when POP_C1 =>
893
        CPU_Next_State       <= POP_C2;
894
 
895
      when POP_C2 =>
896
        CPU_Next_State       <= POP_C3;
897 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
898 169 jshamlet
 
899
      when POP_C3 =>
900
        CPU_Next_State       <= POP_C4;
901
        Cache_Ctrl           <= CACHE_OPER1;
902 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
903 169 jshamlet
 
904
      when POP_C4 =>
905 187 jshamlet
        CPU_Next_State       <= IDC_C0;
906 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
907 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
908 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
909
        ALU_Ctrl.Reg         <= SubOp;
910 172 jshamlet
 
911 169 jshamlet
-------------------------------------------------------------------------------
912
-- Subroutines & Interrupts (RTS, JSR)
913
-------------------------------------------------------------------------------
914 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
915 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
916 186 jshamlet
        if( Int_Req = '1' )then
917
          CPU_Next_State     <= ISR_C1;
918 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
919
          --  instruction, compensating for the pipeline registers.
920 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
921
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
922
          --  operation due to the current instruction
923
          DP_Ctrl.Src        <= DATA_RD_MEM;
924
        end if;
925 169 jshamlet
 
926 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
927 225 jshamlet
        CPU_Halt_Ack         <= '1';
928 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
929
        if( CPU_Halt_Req = '0' )then
930
          CPU_Next_State     <= IPF_C0;
931
          DP_Ctrl.Src        <= DATA_RD_MEM;
932
        end if;
933
 
934
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
935
        CPU_Next_State       <= IPF_C0;
936
 
937 169 jshamlet
      when ISR_C1 =>
938
        CPU_Next_State       <= ISR_C2;
939
        INT_Ctrl.Incr_ISR    <= '1';
940
 
941
      when ISR_C2 =>
942
        CPU_Next_State       <= ISR_C3;
943
        DP_Ctrl.Src          <= DATA_WR_FLAG;
944
 
945
      when ISR_C3 =>
946
        CPU_Next_State       <= JSR_C1;
947
        Cache_Ctrl           <= CACHE_OPER1;
948 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
949 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
950 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
951
        DP_Ctrl.Src          <= DATA_WR_PC;
952 182 jshamlet
        DP_Ctrl.Reg          <= PC_MSB;
953 169 jshamlet
        Ack_D                <= '1';
954
 
955
      when JSR_C1 =>
956
        CPU_Next_State       <= JSR_C2;
957
        Cache_Ctrl           <= CACHE_OPER2;
958
        SP_Ctrl.Oper         <= SP_PUSH;
959
        DP_Ctrl.Src          <= DATA_WR_PC;
960 182 jshamlet
        DP_Ctrl.Reg          <= PC_LSB;
961 169 jshamlet
 
962
      when JSR_C2 =>
963 187 jshamlet
        CPU_Next_State       <= IPF_C0;
964 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
965 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
966 169 jshamlet
 
967
      when RTS_C1 =>
968
        CPU_Next_State       <= RTS_C2;
969
        SP_Ctrl.Oper         <= SP_POP;
970
 
971
      when RTS_C2 =>
972
        CPU_Next_State       <= RTS_C3;
973
        -- if this is an RTI, then we need to POP the flags
974
        if( SubOp = SOP_RTI )then
975
          SP_Ctrl.Oper       <= SP_POP;
976
        end if;
977
 
978
      when RTS_C3 =>
979
        CPU_Next_State       <= RTS_C4;
980
        Cache_Ctrl           <= CACHE_OPER1;
981
 
982
      when RTS_C4 =>
983
        CPU_Next_State       <= RTS_C5;
984
        Cache_Ctrl           <= CACHE_OPER2;
985
 
986
      when RTS_C5 =>
987 187 jshamlet
        CPU_Next_State       <= IPF_C0;
988 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
989 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
990 169 jshamlet
        if( SubOp = SOP_RTI )then
991
          CPU_Next_State     <= RTI_C6;
992
          Cache_Ctrl         <= CACHE_OPER1;
993 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
994
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
995 169 jshamlet
        end if;
996
 
997
      when RTI_C6 =>
998 187 jshamlet
        CPU_Next_State       <= IPF_C1;
999 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1000 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
1001
 
1002
      when others =>
1003
        null;
1004
    end case;
1005
 
1006
  end process;
1007
 
1008
-------------------------------------------------------------------------------
1009
-- Registered portion of CPU finite state machine
1010
-------------------------------------------------------------------------------
1011 182 jshamlet
 
1012 169 jshamlet
  CPU_Regs: process( Reset, Clock )
1013
    variable Offset_SX       : ADDRESS_TYPE;
1014 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
1015 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
1016
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
1017
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
1018
  begin
1019
    if( Reset = Reset_Level )then
1020 187 jshamlet
      CPU_State              <= IPF_C0;
1021 169 jshamlet
      Opcode                 <= OP_INC;
1022
      SubOp                  <= ACCUM;
1023
      SubOp_p1               <= ACCUM;
1024
      Operand1               <= x"00";
1025
      Operand2               <= x"00";
1026
      Instr_Prefetch         <= '0';
1027
      Prefetch               <= x"00";
1028
 
1029 187 jshamlet
      CPU_Halt_Req           <= '0';
1030 225 jshamlet
      Halt_Ack               <= '0';
1031 187 jshamlet
 
1032 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1033
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1034
      Open8_Bus.Rd_En        <= '1';
1035 169 jshamlet
 
1036
      Program_Ctr            <= Program_Start_Addr;
1037
      Stack_Ptr              <= Stack_Start_Addr;
1038
 
1039
      Ack_Q                  <= '0';
1040
      Ack_Q1                 <= '0';
1041
      Int_Ack                <= '0';
1042
 
1043
      Int_Req                <= '0';
1044
      Pending                <= x"00";
1045
      Wait_for_FSM           <= '0';
1046 210 jshamlet
      Wait_for_ISR           <= '0';
1047 245 jshamlet
      Set_Mask               <= '0';
1048 169 jshamlet
      if( Enable_NMI )then
1049
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
1050
      else
1051
        Int_Mask             <= Default_Interrupt_Mask;
1052
      end if;
1053
      ISR_Addr               <= INT_VECTOR_0;
1054
 
1055
      for i in 0 to 7 loop
1056 188 jshamlet
        Regfile(i)           <= x"00";
1057 169 jshamlet
      end loop;
1058
      Flags                  <= x"00";
1059 248 jshamlet
      if( Supervisor_Mode )then
1060 244 jshamlet
        Flags(PSR_I)         <= '1';
1061
      end if;
1062 169 jshamlet
 
1063 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
1064 188 jshamlet
 
1065 169 jshamlet
    elsif( rising_edge(Clock) )then
1066 187 jshamlet
 
1067 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
1068
      Halt_Ack               <= CPU_Halt_Ack;
1069 187 jshamlet
 
1070 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1071
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1072
      Open8_Bus.Rd_En        <= '0';
1073 169 jshamlet
 
1074
-------------------------------------------------------------------------------
1075
-- Instruction/Operand caching for pipelined memory access
1076
-------------------------------------------------------------------------------
1077
      CPU_State              <= CPU_Next_State;
1078
      case Cache_Ctrl is
1079
        when CACHE_INSTR =>
1080
          Opcode             <= Rd_Data(7 downto 3);
1081
          SubOp              <= Rd_Data(2 downto 0);
1082
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
1083
          if( Instr_Prefetch = '1' )then
1084
            Opcode           <= Prefetch(7 downto 3);
1085
            SubOp            <= Prefetch(2 downto 0);
1086
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
1087
            Instr_Prefetch   <= '0';
1088
          end if;
1089
 
1090
        when CACHE_OPER1 =>
1091
          Operand1           <= Rd_Data;
1092
 
1093
        when CACHE_OPER2 =>
1094
          Operand2           <= Rd_Data;
1095
 
1096
        when CACHE_PREFETCH =>
1097
          Prefetch           <= Rd_Data;
1098
          Instr_Prefetch     <= '1';
1099
 
1100
        when CACHE_IDLE =>
1101
          null;
1102
      end case;
1103
 
1104
-------------------------------------------------------------------------------
1105
-- Program Counter
1106
-------------------------------------------------------------------------------
1107
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1108
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1109
 
1110
      case PC_Ctrl.Oper is
1111
        when PC_INCR =>
1112
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1113
 
1114
        when PC_LOAD =>
1115 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1116 169 jshamlet
 
1117
        when others =>
1118
          null;
1119
      end case;
1120
 
1121
-------------------------------------------------------------------------------
1122
-- (Write) Data Path
1123
-------------------------------------------------------------------------------
1124
      case DP_Ctrl.Src is
1125
        when DATA_BUS_IDLE =>
1126
          null;
1127
 
1128
        when DATA_RD_MEM =>
1129 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1130 169 jshamlet
 
1131
        when DATA_WR_REG =>
1132 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1133
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1134 169 jshamlet
 
1135
        when DATA_WR_FLAG =>
1136 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1137
          Open8_Bus.Wr_Data  <= Flags;
1138 169 jshamlet
 
1139
        when DATA_WR_PC =>
1140 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1141
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1142 182 jshamlet
          if( DP_Ctrl.Reg = PC_LSB )then
1143 223 jshamlet
            Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
1144 169 jshamlet
          end if;
1145
 
1146
        when others =>
1147
          null;
1148
      end case;
1149
 
1150
-------------------------------------------------------------------------------
1151
-- Stack Pointer
1152
-------------------------------------------------------------------------------
1153
      case SP_Ctrl.Oper is
1154
        when SP_IDLE =>
1155
          null;
1156
 
1157 181 jshamlet
        when SP_CLR =>
1158 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1159
 
1160 181 jshamlet
        when SP_SET =>
1161 245 jshamlet
          if( Supervisor_Mode )then
1162
            if( Flags(PSR_I) = '1' )then
1163
              Stack_Ptr      <= Regfile(1) & Regfile(0);
1164
            end if;
1165
          else
1166
            Stack_Ptr        <= Regfile(1) & Regfile(0);
1167
          end if;
1168 181 jshamlet
 
1169 169 jshamlet
        when SP_POP  =>
1170
          Stack_Ptr          <= Stack_Ptr + 1;
1171
 
1172
        when SP_PUSH =>
1173
          Stack_Ptr          <= Stack_Ptr - 1;
1174
 
1175
        when others =>
1176
          null;
1177
 
1178
      end case;
1179
 
1180
-------------------------------------------------------------------------------
1181
-- Interrupt Controller
1182
-------------------------------------------------------------------------------
1183 245 jshamlet
 
1184
      -- If Supervisor_Mode is set, restrict the SMSK instruction such that it
1185
      --  requires the I bit to be set.
1186
      if( Supervisor_Mode )then
1187
        Set_Mask             <= INT_Ctrl.Mask_Set and Flags(PSR_I);
1188
      else
1189
        Set_Mask             <= INT_Ctrl.Mask_Set;
1190
      end if;
1191
 
1192 169 jshamlet
      -- The interrupt control mask is always sourced out of R0
1193 245 jshamlet
      if( Set_Mask = '1' )then
1194 169 jshamlet
        if( Enable_NMI )then
1195
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1196
        else
1197
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1198
        end if;
1199
      end if;
1200
 
1201
      -- Combine external and internal interrupts, and mask the OR of the two
1202
      --  with the mask. Record any incoming interrupts to the pending buffer
1203
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1204
                                Int_Mask;
1205 172 jshamlet
 
1206 169 jshamlet
      Pending                <= i_Ints or Pending;
1207
 
1208 210 jshamlet
      if( Sequential_Interrupts )then
1209
        Wait_for_ISR         <= Flags(PSR_I);
1210
      else
1211
        Wait_for_ISR         <= '0';
1212
      end if;
1213
 
1214
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1215 169 jshamlet
        if(    Pending(0) = '1' )then
1216
          ISR_Addr           <= INT_VECTOR_0;
1217
          Pending(0)         <= '0';
1218
        elsif( Pending(1) = '1' )then
1219
          ISR_Addr           <= INT_VECTOR_1;
1220
          Pending(1)         <= '0';
1221
        elsif( Pending(2) = '1' )then
1222
          ISR_Addr           <= INT_VECTOR_2;
1223
          Pending(2)         <= '0';
1224
        elsif( Pending(3) = '1' )then
1225
          ISR_Addr           <= INT_VECTOR_3;
1226
          Pending(3)         <= '0';
1227
        elsif( Pending(4) = '1' )then
1228
          ISR_Addr           <= INT_VECTOR_4;
1229
          Pending(4)         <= '0';
1230
        elsif( Pending(5) = '1' )then
1231
          ISR_Addr           <= INT_VECTOR_5;
1232
          Pending(5)         <= '0';
1233
        elsif( Pending(6) = '1' )then
1234
          ISR_Addr           <= INT_VECTOR_6;
1235
          Pending(6)         <= '0';
1236
        elsif( Pending(7) = '1' )then
1237
          ISR_Addr           <= INT_VECTOR_7;
1238
          Pending(7)         <= '0';
1239
        end if;
1240 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1241 169 jshamlet
      end if;
1242
 
1243
      -- Reset the Wait_for_FSM flag on Int_Ack
1244
      Ack_Q                  <= Ack_D;
1245
      Ack_Q1                 <= Ack_Q;
1246
      Int_Ack                <= Ack_Q1;
1247
      if( Int_Ack = '1' )then
1248
        Wait_for_FSM         <= '0';
1249
      end if;
1250
 
1251
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1252
 
1253
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1254
      --  lower half of the address.
1255
      if( INT_Ctrl.Incr_ISR = '1' )then
1256
        ISR_Addr             <= ISR_Addr + 1;
1257
      end if;
1258
 
1259
-------------------------------------------------------------------------------
1260
-- ALU (Arithmetic / Logic Unit)
1261
-------------------------------------------------------------------------------
1262
      Index                  := conv_integer(ALU_Ctrl.Reg);
1263
      Sum                    := (others => '0');
1264
      Temp                   := (others => '0');
1265
 
1266
      case ALU_Ctrl.Oper is
1267
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1268
          Sum                := ("0" & x"01") +
1269
                                ("0" & Regfile(Index));
1270 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1271
          Flags(PSR_C)       <= Sum(8);
1272 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1273 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1274
 
1275
        when ALU_UPP => -- Rn = Rn + 1
1276
          Sum                := ("0" & x"01") +
1277
                                ("0" & Regfile(Index));
1278 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1279 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1280
 
1281
        when ALU_UPP2 => -- Rn = Rn + C
1282
          Sum                := ("0" & x"00") +
1283
                                ("0" & Regfile(Index)) +
1284 185 jshamlet
                                Flags(PSR_C);
1285
          Flags(PSR_C)       <= Sum(8);
1286 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1287
 
1288
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1289
          Sum                := ("0" & Regfile(0)) +
1290
                                ("0" & Regfile(Index)) +
1291 185 jshamlet
                                Flags(PSR_C);
1292
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1293
          Flags(PSR_C)       <= Sum(8);
1294
          Flags(PSR_N)       <= Sum(7);
1295 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1296
 
1297
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1298
          Temp               := "0" & Regfile(Index);
1299 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1300
          Flags(PSR_N)       <= Temp(7);
1301 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1302
 
1303
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1304
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1305 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1306
          Flags(PSR_N)       <= Temp(7);
1307 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1308
 
1309
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1310
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1311 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1312
          Flags(PSR_N)       <= Temp(7);
1313 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1314
 
1315
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1316
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1317 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1318
          Flags(PSR_N)       <= Temp(7);
1319 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1320
 
1321
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1322 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1323
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1324
          Flags(PSR_C)       <= Temp(8);
1325
          Flags(PSR_N)       <= Temp(7);
1326 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1327
 
1328
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1329 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1330 169 jshamlet
                                Regfile(Index)(7 downto 1);
1331 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1332
          Flags(PSR_C)       <= Temp(8);
1333
          Flags(PSR_N)       <= Temp(7);
1334 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1335
 
1336
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1337
          Sum                := ("0" & Regfile(Index)) +
1338
                                ("0" & x"FF");
1339 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1340
          Flags(PSR_C)       <= Sum(8);
1341
          Flags(PSR_N)       <= Sum(7);
1342 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1343
 
1344
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1345
          Sum                := ("0" & Regfile(0)) +
1346
                                ("1" & (not Regfile(Index))) +
1347 185 jshamlet
                                Flags(PSR_C);
1348
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1349
          Flags(PSR_C)       <= Sum(8);
1350
          Flags(PSR_N)       <= Sum(7);
1351 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1352
 
1353
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1354
          Sum                := ("0" & Regfile(0)) +
1355
                                ("0" & Regfile(Index));
1356 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1357 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1358 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1359
          Flags(PSR_N)       <= Sum(7);
1360 169 jshamlet
 
1361
        when ALU_STP => -- Sets bit(n) in the Flags register
1362
          Flags(Index)       <= '1';
1363
 
1364
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1365 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1366
          Flags(PSR_N)       <= Regfile(0)(7);
1367 169 jshamlet
 
1368
        when ALU_CLP => -- Clears bit(n) in the Flags register
1369
          Flags(Index)       <= '0';
1370
 
1371
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1372
          Temp               := "0" & Regfile(0);
1373 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1374
          Flags(PSR_N)       <= Temp(7);
1375 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1376
 
1377
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1378
          Sum                := ("0" & Regfile(0)) +
1379
                                ("1" & (not Regfile(Index))) +
1380
                                '1';
1381 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1382
          Flags(PSR_C)       <= Sum(8);
1383
          Flags(PSR_N)       <= Sum(7);
1384 169 jshamlet
 
1385
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1386
          Regfile(0)         <= Mult(7 downto 0);
1387
          Regfile(1)         <= Mult(15 downto 8);
1388 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1389 169 jshamlet
 
1390
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1391 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1392
          Flags(PSR_N)       <= Operand1(7);
1393
          Regfile(Index)     <= Operand1;
1394 169 jshamlet
 
1395
        when ALU_POP => -- Rn <= Data
1396 185 jshamlet
          Regfile(Index)     <= Operand1;
1397 169 jshamlet
 
1398
        when ALU_RFLG =>
1399 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1400
          if( not RTI_Ignores_GP_Flags )then
1401
            Flags(7 downto 4)<= Operand1(7 downto 4);
1402
          end if;
1403 169 jshamlet
 
1404 185 jshamlet
        when ALU_RSP =>
1405 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1406
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1407
 
1408 185 jshamlet
        when ALU_GMSK =>
1409
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1410
          Regfile(0)         <= Int_Mask;
1411
 
1412 169 jshamlet
        when others =>
1413
          null;
1414
      end case;
1415
 
1416 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1417 188 jshamlet
 
1418 169 jshamlet
    end if;
1419
  end process;
1420
 
1421 182 jshamlet
-------------------------------------------------------------------------------
1422
-- Multiplier Logic
1423
--
1424
-- We need to infer a hardware multipler, so we create a special clocked
1425
--  process with no reset or clock enable
1426
-------------------------------------------------------------------------------
1427
 
1428
  Multiplier_proc: process( Clock )
1429
  begin
1430
    if( rising_edge(Clock) )then
1431
      Mult                   <= Regfile(0) *
1432 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1433
    end if;
1434
  end process;
1435
 
1436
end architecture;

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