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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Blame information for rev 283

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Line No. Rev Author Line
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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
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-- VHDL Units :  o8_cpu
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-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44 270 jshamlet
--            :   specified by STACK_XFER_FLAG. If the flag is '0', RSP will
45 181 jshamlet
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 270 jshamlet
--            :  STACK_XFER_FLAG instructs the core to use the specified ALU
52 181 jshamlet
--            :   flag to alter the behavior of the RSP instruction when
53 256 jshamlet
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it's ignored.
54 181 jshamlet
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 260 jshamlet
--            :  Sequential_Interrupts, when set, prevents interrupt service
74
--            :   routines from  being interrupted by postponing an later
75
--            :   interrupts until the I bit is cleared (usually with an RTI,
76
--            :   but a CLP PSR_I will also work). This is potentially
77
--            :   dangerous, as it means a lower-priority ISR can "hog" the CPU
78
--            :   by failing to return. However, it can also prevent the
79
--            :   condition of an ISR interrupting itself until it causes a
80
--            :   memory fault. (For example, an interrupt source that whose
81
--            :   period is shorter than the ISR service time) Note that this
82
--            :   setting alters the way the pending logic works, so it affects
83
--            :   all interrupts, including the NMI. If this is set, special
84
--            :   care should be taken to make sure ISRs are short and always
85
--            :   execute an RTI at the end.
86
--            :
87 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
88
--            :   after an interrupt. By default, all of the flag bits are put
89
--            :   back to their original state. If this flag is set true, only
90
--            :   the lower four bits are restored, allowing ISR code to alter
91
--            :   the GP flags persistently.
92
--            :
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--            :  Supervisor_Mode, when set, disables the STP PSR_I instruction
94
--            :   preventing code from setting the I bit. When enabled, only
95
--            :   interrupts can set the I bit, allowing for more robust memory
96
--            :   protection by preventing errant code execution from
97
--            :   inadvertently entering an interrupt state.
98
--            :
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--            :   This setting also sets I bit at startup so that any
100
--            :   initialization code may be run in an ISR context, initially
101
--            :   bypassing memory protection. Init code should clear the I bit
102
--            :   when done;
103 244 jshamlet
--            :
104 255 jshamlet
--            :  Unsigned_Index_Offsets alters the way offsets are added to
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--            :   [Rn+1:Rn] during LDO/STO instructions. The original, default
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--            :   behavior treats these offsets as signed values, allowing
107
--            :   instructions to offset by -128 to +127 from [Rn+1:Rn].
108
--            :   Setting this generic to TRUE will switch to unsigned offsets,
109
--            :   switching the range to 0 to 255 instead.
110
--            :
111 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
112
--            :   interrupt mask. To remain true to the original core, which
113
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
114
--            :   it can be initialized to any value. Note that Enable_NMI
115
--            :   will logically force the LSB high.
116 172 jshamlet
--            :
117 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
118
--            :   on a high or low level from higher logic.
119
--            :
120
--            : Architecture notes
121
--            :  This model deviates from the original ISA in a few important
122
--            :   ways.
123
--            :
124
--            :  First, there is only one set of registers. Interrupt service
125
--            :   routines must explicitely preserve context since the the
126
--            :   hardware doesn't. This was done to decrease size and code
127
--            :   complexity. Older code that assumes this behavior will not
128
--            :   execute correctly on this processor model.
129
--            :
130
--            :  Second, this model adds an additional pipeline stage between
131
--            :   the instruction decoder and the ALU. Unfortunately, this
132
--            :   means that the instruction stream has to be restarted after
133
--            :   any math instruction is executed, implying that any ALU
134
--            :   instruction now has a latency of 2 instead of 0. The
135
--            :   advantage is that the maximum frequency has gone up
136
--            :   significantly, as the ALU code is vastly more efficient.
137
--            :   As an aside, this now means that all math instructions,
138
--            :   including MUL (see below) and UPP have the same instruction
139
--            :   latency.
140
--            :
141
--            :  Third, the original ISA, also a soft core, had two reserved
142
--            :   instructions, USR and USR2. These have been implemented as
143
--            :   DBNZ, and MUL respectively.
144
--            :
145
--            :  DBNZ decrements the specified register and branches if the
146
--            :   result is non-zero. The instruction effectively executes a
147
--            :   DEC Rn instruction prior to branching, so the same flags will
148
--            :   be set.
149
--            :
150
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
151
--            :   latency is identical to other ALU instructions. Only the Z
152
--            :   flag is set, since there is no defined overflow or "negative
153
--            :   16-bit values"
154
--            :
155
--            :  Fourth, indexed load/store instructions now have an (optional)
156
--            :   ability to post-increment their index registers. If enabled,
157
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
158
--            :   register pair to be incremented after the storage access.
159
--            :
160
--            :  Fifth, the RSP instruction has been (optionally) altered to
161
--            :   allow the stack pointer to be sourced from R1:R0.
162
--            :
163
--            :  Sixth, the BRK instruction can optionally implement a WAI,
164
--            :   which is the same as the INT instruction without the soft
165
--            :   interrupt, as a way to put the processor to "sleep" until the
166
--            :   next external interrupt.
167
--            :
168
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
169
--            :   with priority. This model has the same 8 interrupts, but
170 172 jshamlet
--            :   allows software to mask them (with an additional option to
171 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
172
--            :
173
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
174
--            :   were repurposed to support a new interrupt mask.
175
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
176
--            :   to/from the interrupt mask register. SMSK is immediate, while
177
--            :   GMSK has the same overhead as a math instruction.
178
--
179
-- Revision History
180
-- Author          Date     Change
181
------------------ -------- ---------------------------------------------------
182
-- Seth Henry      07/19/06 Design Start
183
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
184
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
185
--                           corruption issues.
186
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
187
--                           path sections.
188
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
189
--                           single entity.
190
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
191
--                           processor to wait for an interrupt instead of the
192
--                           normal BRK behavior.
193 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
194 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
195
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
196
--                           faster logic that simply does priority encoding.
197
-- Seth Henry      08/06/13 Removed HALT functionality
198
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
199 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
200 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
201
--                           allowing true backup/restore of the stack pointer
202 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
203
--                           in order to simplify things and eliminate
204
--                           redundancies. Came across and fixed a problem with
205
--                           the STO instruction when Enable_Auto_Increment is
206
--                           NOT set.
207 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
208
--                           the assembler names. Also fixed an issue where
209
--                           the I bit wasn't being cleared after interrupts.
210
--                          Simplified the program counter logic to only use
211
--                           the offset for increments, redefining the
212
--                           original modes as fixed offset values.
213
--                          Modified the ALU section with a new ALU operation
214
--                           for GMSK. This allowed the .data field to be
215
--                           removed and Operand1 used in its place, which
216
--                           simplified the logic a great deal.
217 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
218
--                           the instruction decode state, where it acts as a
219
--                           modified form of the BRK instruction that holds
220
--                           state until CPU_Halt is deasserted. This has a
221
--                           much smaller impact on Fmax/complexity than the
222
--                           original clock enable, but imposes a mild impact
223
--                           due to the need to reset the instruction pipeline
224 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
225
--                           the flags, including the general purpose ones, or
226
--                           only the core ALU flags (Z, N, and C). Also
227
--                           brought out copies of the GP flags for external
228
--                           connection.
229 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
230
--                           while the I bit is set to avoid reentering ISRs
231
--                           This may slightly affect timing, as this will
232
--                           potentially block higher priority interrupts
233
--                           until the lower priority ISR returns or clears
234
--                           the I bit.
235
--                          Also added the I bit to the exported flags for
236
--                           use in memory protection schemes.
237 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
238 225 jshamlet
--                           reset and usec_tick logic to drive utility
239
--                           signals. Also added Halt_Ack output.
240 244 jshamlet
-- Seth Henry      05/20/20 Added two new generics to alter the way the I bit
241
--                           is handled. The Supervisor_Mode setting disables
242
--                           STP PSR_I from being executed, preventing it
243
--                           from being set outside of an ISR. The
244
--                           Default_Int_Flag setting allows the I bit to
245
--                           start set so that initialization code can run,
246
--                           but not be hijacked later to corrupt any memory
247
--                           write protection later.
248 245 jshamlet
-- Seth Henry      05/21/20 Supervisor_Mode now protects the interrupt mask
249
--                           and stack pointer as well.
250 248 jshamlet
-- Seth Henry      05/24/20 Removed the Default_Int_Flag, as it is covered by
251
--                           Supervisor_Mode. If Supervisor_Mode isn't set,
252
--                           code can simply use STP to set the bit
253 252 jshamlet
-- Seth Henry      06/09/20 Added ability to use unsigned index offsets for
254 253 jshamlet
--                           LDO/STO. Also pipelined the address calculation
255 252 jshamlet
--                           for indexed instructions, reducing the final
256
--                           address generator to a multiplexor fed only by
257
--                           registers.
258 264 jshamlet
-- Seth Henry      07/10/20 Fixed a bug in the LDO/LDX logic where the register
259
--                           pair wasn't being incremented properly due to a
260
--                           missing UPP2 signal to the ALU.
261 269 jshamlet
-- Seth Henry      10/21/20 Modified the write data path to use separate
262
--                           enumerated states rather than reuse the .reg field
263
--                           to improve performance.
264 270 jshamlet
-- Seth Henry      10/23/20 Moved CPU internal constants to o8_cpu.vhd. Also
265
--                           removed Stack_Xfer_Flag, which specified the CPU
266
--                           flag used to alter the RSP instruction, making it
267
--                           a constant instead (PSR_GP4). This eliminated the
268
--                           need to expose an internal constant externally
269 169 jshamlet
 
270
library ieee;
271
  use ieee.std_logic_1164.all;
272
  use ieee.std_logic_unsigned.all;
273
  use ieee.std_logic_arith.all;
274
  use ieee.std_logic_misc.all;
275
 
276
library work;
277 227 jshamlet
  use work.Open8_pkg.all;
278 169 jshamlet
 
279 183 jshamlet
entity o8_cpu is
280 169 jshamlet
  generic(
281
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
282
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
283
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
284
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
285
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
286
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
287
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
288 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
289 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
290 244 jshamlet
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
291 252 jshamlet
    Unsigned_Index_Offsets   : boolean      := false;   -- Offsets are signed
292 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
293 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
294
);
295 169 jshamlet
  port(
296
    Clock                    : in  std_logic;
297 224 jshamlet
    PLL_Locked               : in  std_logic;
298 169 jshamlet
    --
299 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
300
    Halt_Ack                 : out std_logic;
301
    --
302 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
303 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
304 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
305
);
306 169 jshamlet
end entity;
307
 
308 183 jshamlet
architecture behave of o8_cpu is
309 169 jshamlet
 
310 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
311
  signal Reset               : std_logic := Reset_Level;
312
 
313
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
314
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
315
  constant USEC_DLY          : std_logic_vector :=
316
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
317
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
318
  signal uSec_Tick           : std_logic;
319
 
320 270 jshamlet
  -- CPU Instruction Set Definitions
321
  subtype OPCODE_TYPE  is std_logic_vector(4 downto 0);
322
  subtype SUBOP_TYPE   is std_logic_vector(2 downto 0);
323
 
324
  -- All opcodes should be identical to the opcode used by the assembler
325
  -- In this case, they match the original V8/ARC uRISC ISA
326
  constant OP_INC            : OPCODE_TYPE := "00000";
327
  constant OP_ADC            : OPCODE_TYPE := "00001";
328
  constant OP_TX0            : OPCODE_TYPE := "00010";
329
  constant OP_OR             : OPCODE_TYPE := "00011";
330
  constant OP_AND            : OPCODE_TYPE := "00100";
331
  constant OP_XOR            : OPCODE_TYPE := "00101";
332
  constant OP_ROL            : OPCODE_TYPE := "00110";
333
  constant OP_ROR            : OPCODE_TYPE := "00111";
334
  constant OP_DEC            : OPCODE_TYPE := "01000";
335
  constant OP_SBC            : OPCODE_TYPE := "01001";
336
  constant OP_ADD            : OPCODE_TYPE := "01010";
337
  constant OP_STP            : OPCODE_TYPE := "01011";
338
  constant OP_BTT            : OPCODE_TYPE := "01100";
339
  constant OP_CLP            : OPCODE_TYPE := "01101";
340
  constant OP_T0X            : OPCODE_TYPE := "01110";
341
  constant OP_CMP            : OPCODE_TYPE := "01111";
342
  constant OP_PSH            : OPCODE_TYPE := "10000";
343
  constant OP_POP            : OPCODE_TYPE := "10001";
344
  constant OP_BR0            : OPCODE_TYPE := "10010";
345
  constant OP_BR1            : OPCODE_TYPE := "10011";
346
  constant OP_DBNZ           : OPCODE_TYPE := "10100"; -- USR
347
  constant OP_INT            : OPCODE_TYPE := "10101";
348
  constant OP_MUL            : OPCODE_TYPE := "10110"; -- USR2
349
  constant OP_STK            : OPCODE_TYPE := "10111";
350
  constant OP_UPP            : OPCODE_TYPE := "11000";
351
  constant OP_STA            : OPCODE_TYPE := "11001";
352
  constant OP_STX            : OPCODE_TYPE := "11010";
353
  constant OP_STO            : OPCODE_TYPE := "11011";
354
  constant OP_LDI            : OPCODE_TYPE := "11100";
355
  constant OP_LDA            : OPCODE_TYPE := "11101";
356
  constant OP_LDX            : OPCODE_TYPE := "11110";
357
  constant OP_LDO            : OPCODE_TYPE := "11111";
358
 
359
  -- OP_STK uses the lower 3 bits to further refine the instruction by
360
  --  repurposing the source register field. These "sub opcodes" take
361
  --  the place of the register select for the OP_STK opcode
362
  constant SOP_RSP           : SUBOP_TYPE := "000";
363
  constant SOP_RTS           : SUBOP_TYPE := "001";
364
  constant SOP_RTI           : SUBOP_TYPE := "010";
365
  constant SOP_BRK           : SUBOP_TYPE := "011";
366
  constant SOP_JMP           : SUBOP_TYPE := "100";
367
  constant SOP_SMSK          : SUBOP_TYPE := "101";
368
  constant SOP_GMSK          : SUBOP_TYPE := "110";
369
  constant SOP_JSR           : SUBOP_TYPE := "111";
370
 
371
  -- These should match the assembler's definitions for the flags
372
  constant PSR_Z             : integer := 0;
373
  constant PSR_C             : integer := 1;
374
  constant PSR_N             : integer := 2;
375
  constant PSR_I             : integer := 3;
376
  constant PSR_GP4           : integer := 4;
377
  constant PSR_GP5           : integer := 5;
378
  constant PSR_GP6           : integer := 6;
379
  constant PSR_GP7           : integer := 7;
380
 
381
  -- Internal CPU Signals & Constants
382
 
383
  type CPU_STATES is (
384
      -- Instruction fetch & Decode
385
    IPF_C0, IPF_C1, IPF_C2, IDC_C0,
386
    -- Branching
387
    BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
388
    -- Loads
389
    LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
390
    LDO_C1, LDO_C2, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
391
    -- Stores
392
    STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STO_C3, STX_C1, STX_C2,
393
    -- 2-cycle math
394
    MUL_C1, UPP_C1,
395
    -- Stack
396
    PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
397
    -- Subroutines & Interrupts
398
    WAI_Cx, WAH_Cx, BRK_C1,
399
    ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
400
    RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6
401
     );
402
 
403
  type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
404
                       CACHE_PREFETCH );
405
 
406
  type PC_MODES is ( PC_INCR, PC_LOAD );
407
 
408
  type PC_CTRL_TYPE is record
409
    Oper                     : PC_MODES;
410
    Offset                   : DATA_TYPE;
411
  end record;
412
 
413
  -- These are fixed constant offsets to the program counter logic, which is
414
  --  always either incrementing or loading.
415
  constant PC_NEXT           : DATA_TYPE := x"03";
416
  constant PC_IDLE           : DATA_TYPE := x"02";
417
  constant PC_REV1           : DATA_TYPE := x"01";
418
  constant PC_REV2           : DATA_TYPE := x"00";
419
  constant PC_REV3           : DATA_TYPE := x"FF";
420
 
421
  type SP_MODES is ( SP_IDLE, SP_CLR, SP_SET, SP_POP, SP_PUSH );
422
 
423
  type SP_CTRL_TYPE is record
424
    Oper                     : SP_MODES;
425
  end record;
426
 
427
  -- This constant determines which CPU flag is used to switch the
428
  --  direction of the modified RSP instruction
429
  constant STACK_XFER_FLAG   : integer := PSR_GP4; -- GP4 modifies RSP
430
 
431
  type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
432
                     DATA_WR_REG, DATA_WR_FLAG,
433
                     DATA_WR_PC_L, DATA_WR_PC_H );
434
 
435
  type DATA_CTRL_TYPE is record
436
    Src                      : DP_MODES;
437
    Reg                      : SUBOP_TYPE;
438
  end record;
439
 
440
  type INT_CTRL_TYPE is record
441
    Mask_Set                 : std_logic;
442
    Soft_Ints                : INTERRUPT_BUNDLE;
443
    Incr_ISR                 : std_logic;
444
  end record;
445
 
446
  -- Most of the ALU instructions are the same as their Opcode equivalents,
447
  --  with exceptions for IDLE, UPP2, RFLG, RSP, and GMSK, which perform
448
  --  internal operations not otherwise exposed by the instruction set.
449
  constant ALU_INC           : OPCODE_TYPE := "00000"; -- x"00"
450
  constant ALU_ADC           : OPCODE_TYPE := "00001"; -- x"01"
451
  constant ALU_TX0           : OPCODE_TYPE := "00010"; -- x"02"
452
  constant ALU_OR            : OPCODE_TYPE := "00011"; -- x"03"
453
  constant ALU_AND           : OPCODE_TYPE := "00100"; -- x"04"
454
  constant ALU_XOR           : OPCODE_TYPE := "00101"; -- x"05"
455
  constant ALU_ROL           : OPCODE_TYPE := "00110"; -- x"06"
456
  constant ALU_ROR           : OPCODE_TYPE := "00111"; -- x"07"
457
  constant ALU_DEC           : OPCODE_TYPE := "01000"; -- x"08"
458
  constant ALU_SBC           : OPCODE_TYPE := "01001"; -- x"09"
459
  constant ALU_ADD           : OPCODE_TYPE := "01010"; -- x"0A"
460
  constant ALU_STP           : OPCODE_TYPE := "01011"; -- x"0B"
461
  constant ALU_BTT           : OPCODE_TYPE := "01100"; -- x"0C"
462
  constant ALU_CLP           : OPCODE_TYPE := "01101"; -- x"0D"
463
  constant ALU_T0X           : OPCODE_TYPE := "01110"; -- x"0E"
464
  constant ALU_CMP           : OPCODE_TYPE := "01111"; -- x"0F"
465
  constant ALU_POP           : OPCODE_TYPE := "10001"; -- x"11"
466
  constant ALU_MUL           : OPCODE_TYPE := "10110"; -- x"16"
467
  constant ALU_UPP           : OPCODE_TYPE := "11000"; -- x"18"
468
  constant ALU_LDI           : OPCODE_TYPE := "11100"; -- x"1C"
469
 
470
  constant ALU_IDLE          : OPCODE_TYPE := "10000"; -- x"10"
471
  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"12"
472
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"13"
473
  constant ALU_RSP           : OPCODE_TYPE := "10111"; -- x"17"
474
  constant ALU_GMSK          : OPCODE_TYPE := "11111"; -- x"1F"
475
 
476
  type ALU_CTRL_TYPE is record
477
    Oper                     : OPCODE_TYPE;
478
    Reg                      : SUBOP_TYPE;
479
  end record;
480
 
481
  constant ACCUM             : SUBOP_TYPE := "000";
482
 
483
  type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
484
 
485
  subtype FLAG_TYPE is DATA_TYPE;
486
 
487 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
488
  signal CPU_State           : CPU_STATES := IPF_C0;
489 169 jshamlet
 
490 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
491
  signal CPU_Halt_Ack        : std_logic := '0';
492 187 jshamlet
 
493 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
494
 
495
  signal Opcode              : OPCODE_TYPE := (others => '0');
496
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
497
 
498
  signal Prefetch            : DATA_TYPE   := x"00";
499
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
500
 
501
  signal Instr_Prefetch      : std_logic   := '0';
502
 
503
  signal PC_Ctrl             : PC_CTRL_TYPE;
504
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
505
 
506 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
507
  signal Regfile             : REGFILE_TYPE;
508
  signal Flags               : FLAG_TYPE;
509
  signal Mult                : ADDRESS_TYPE := x"0000";
510
 
511 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
512
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
513
 
514
  signal DP_Ctrl             : DATA_CTRL_TYPE;
515
 
516
  signal INT_Ctrl            : INT_CTRL_TYPE;
517
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
518
  signal Int_Req, Int_Ack    : std_logic   := '0';
519 245 jshamlet
  signal Set_Mask            : std_logic   := '0';
520 169 jshamlet
  signal Int_Mask            : DATA_TYPE   := x"00";
521
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
522
  signal Pending             : INTERRUPT_BUNDLE := x"00";
523
  signal Wait_for_FSM        : std_logic := '0';
524 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
525 169 jshamlet
 
526 254 jshamlet
  alias  ISR_Addr_Base       is ISR_Start_Addr(15 downto 4);
527
  signal ISR_Addr_Offset     : std_logic_vector(3 downto 0) := x"0";
528
 
529
  constant INT_VECTOR_0      : std_logic_vector(3 downto 0) := x"0";
530
  constant INT_VECTOR_1      : std_logic_vector(3 downto 0) := x"2";
531
  constant INT_VECTOR_2      : std_logic_vector(3 downto 0) := x"4";
532
  constant INT_VECTOR_3      : std_logic_vector(3 downto 0) := x"6";
533
  constant INT_VECTOR_4      : std_logic_vector(3 downto 0) := x"8";
534
  constant INT_VECTOR_5      : std_logic_vector(3 downto 0) := x"A";
535
  constant INT_VECTOR_6      : std_logic_vector(3 downto 0) := x"C";
536
  constant INT_VECTOR_7      : std_logic_vector(3 downto 0) := x"E";
537
 
538 255 jshamlet
  signal IDX_Offset_SX       : std_logic := '0';
539
 
540 252 jshamlet
  signal IDX_Offset          : ADDRESS_TYPE := x"0000";
541
 
542 255 jshamlet
  signal IDX_Sel_l           : std_logic_vector(2 downto 0) := "000";
543
  signal IDX_Sel_h           : std_logic_vector(2 downto 0) := "000";
544
 
545 252 jshamlet
  signal IDX_Reg_l           : integer := 0;
546
  signal IDX_Reg_h           : integer := 0;
547
 
548
  signal IDX_NoOffset_Calc   : ADDRESS_TYPE := x"0000";
549
  signal IDX_Offset_Calc     : ADDRESS_TYPE := x"0000";
550
 
551 169 jshamlet
begin
552
 
553 224 jshamlet
-------------------------------------------------------------------------------
554
-- Reset & uSec Tick
555
-------------------------------------------------------------------------------
556 185 jshamlet
 
557 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
558
  begin
559
    if( PLL_Locked = '0' )then
560
      Reset_q                <= Reset_Level;
561
      Reset                  <= Reset_Level;
562
    elsif( rising_edge(Clock) )then
563
      Reset_q                <= not Reset_Level;
564
      Reset                  <= Reset_q;
565
    end if;
566
  end process;
567
 
568
  uSec_Tick_proc: process( Clock, Reset )
569
  begin
570
    if( Reset = Reset_Level )then
571
      uSec_Cntr              <= USEC_DLY;
572
      uSec_Tick              <= '0';
573
    elsif( rising_edge( Clock ) )then
574
      uSec_Cntr              <= uSec_Cntr - 1;
575
      if( or_reduce(uSec_Cntr) = '0' )then
576
        uSec_Cntr            <= USEC_DLY;
577
      end if;
578
      uSec_Tick              <= nor_reduce(uSec_Cntr);
579
    end if;
580
  end process;
581
 
582
  Open8_Bus.Clock            <= Clock;
583
  Open8_Bus.Reset            <= Reset;
584
  Open8_Bus.uSec_Tick        <= uSec_Tick;
585
 
586 169 jshamlet
-------------------------------------------------------------------------------
587 182 jshamlet
-- Address bus selection/generation logic
588 169 jshamlet
-------------------------------------------------------------------------------
589
 
590 254 jshamlet
  -- Address selection logic based on current CPU state. This is combinatorial,
591
  --  as adding pipeline registration would add a clock cycle to every instr,
592
  --  without really adding the Fmax to compensate.
593
  Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
594 255 jshamlet
                         IDX_Offset_Calc, ISR_Addr_Offset, Stack_Ptr,
595
                         Program_Ctr )
596 254 jshamlet
  begin
597
    case( CPU_State )is
598
 
599
      when LDA_C2 | STA_C2 =>
600
        Open8_Bus.Address    <= Operand2 & Operand1;
601
 
602
      when LDX_C1 | STX_C1 =>
603
        Open8_Bus.Address    <= IDX_NoOffset_Calc;
604
 
605
      when LDO_C2 | STO_C2 =>
606
        Open8_Bus.Address    <= IDX_Offset_Calc;
607
 
608
      when ISR_C1 | ISR_C2 =>
609
        Open8_Bus.Address    <= ISR_Addr_Base & ISR_Addr_Offset;
610
 
611 255 jshamlet
      when PSH_C1 | POP_C1 |
612
           ISR_C3 | JSR_C1 | JSR_C2 |
613
           RTS_C1 | RTS_C2 | RTS_C3 =>
614 254 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
615
 
616
      when others =>
617
        Open8_Bus.Address    <= Program_Ctr;
618
 
619
    end case;
620
  end process;
621
 
622 252 jshamlet
  -- The original model treated the offset to LDO/STO as a signed value
623
  --  allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't
624
  --  always helpful, so the generic allows the CPU to use unsigned math
625
  --  for the offsets. This makes the range 0 to +255 instead.
626 253 jshamlet
 
627 255 jshamlet
  IDX_Offset_SX <= '0' when Unsigned_Index_Offsets else Operand1(7);
628 252 jshamlet
 
629 255 jshamlet
  IDX_Offset(15 downto 8)    <= (others => IDX_Offset_SX);
630 252 jshamlet
  IDX_Offset(7 downto 0)     <= Operand1;
631
 
632
  -- Enable_Auto_Increment uses the LSB to determine whether or not to
633
  --  do the auto-increment, so we need to lock the LSB for each operand
634
  --  if it is enabled. This forces [ODD:EVEN] pairing.
635
 
636 255 jshamlet
  IDX_Sel_l <= (SubOp(2 downto 1) & '0') when Enable_Auto_Increment else
637
               SubOp;
638 252 jshamlet
 
639 255 jshamlet
  IDX_Sel_h <= (SubOp(2 downto 1) & '1') when Enable_Auto_Increment else
640
               SubOp_p1;
641 252 jshamlet
 
642 255 jshamlet
  IDX_Reg_l <= conv_integer(IDX_Sel_l);
643
  IDX_Reg_h <= conv_integer(IDX_Sel_h);
644
 
645 252 jshamlet
  -- Pipeline registers for the indexed and indexed with offset addresses.
646
  Idx_Addr_Calc_proc: process( Clock, Reset )
647 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
648
  begin
649 252 jshamlet
    if( Reset = Reset_Level )then
650
      IDX_NoOffset_Calc      <= x"0000";
651
      IDX_Offset_Calc        <= x"0000";
652
    elsif( rising_edge(Clock))then
653
      IDX_NoOffset_Calc      <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l));
654
      IDX_Offset_Calc        <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) +
655
                                IDX_Offset;
656 182 jshamlet
    end if;
657 252 jshamlet
  end process;
658 182 jshamlet
 
659
-------------------------------------------------------------------------------
660
-- Combinatorial portion of CPU finite state machine
661
-- State Logic / Instruction Decoding & Execution
662
-------------------------------------------------------------------------------
663
 
664 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
665 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
666
    variable Reg             : integer range 0 to 7 := 0;
667
  begin
668 169 jshamlet
    CPU_Next_State           <= CPU_State;
669
    Cache_Ctrl               <= CACHE_IDLE;
670
    --
671 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
672
    PC_Ctrl.Offset           <= PC_IDLE;
673 182 jshamlet
    --
674 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
675
    ALU_Ctrl.Reg             <= ACCUM;
676
    --
677
    SP_Ctrl.Oper             <= SP_IDLE;
678
    --
679
    DP_Ctrl.Src              <= DATA_RD_MEM;
680
    DP_Ctrl.Reg              <= ACCUM;
681
    --
682
    INT_Ctrl.Mask_Set        <= '0';
683
    INT_Ctrl.Soft_Ints       <= x"00";
684
    INT_Ctrl.Incr_ISR        <= '0';
685
    Ack_D                    <= '0';
686 225 jshamlet
    --
687 182 jshamlet
    Reg                     := conv_integer(SubOp);
688 225 jshamlet
    --
689
    CPU_Halt_Ack             <= '0';
690 169 jshamlet
 
691
    case CPU_State is
692
-------------------------------------------------------------------------------
693
-- Initial Instruction fetch & decode
694
-------------------------------------------------------------------------------
695 187 jshamlet
      when IPF_C0 =>
696
        CPU_Next_State       <= IPF_C1;
697 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
698 169 jshamlet
 
699 187 jshamlet
      when IPF_C1 =>
700
        CPU_Next_State       <= IPF_C2;
701 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
702 169 jshamlet
 
703 187 jshamlet
      when IPF_C2 =>
704
        CPU_Next_State       <= IDC_C0;
705 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
706 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
707 169 jshamlet
 
708 187 jshamlet
      when IDC_C0 =>
709
        CPU_Next_State       <= IDC_C0;
710 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
711
 
712
        case Opcode is
713
          when OP_PSH =>
714
            CPU_Next_State   <= PSH_C1;
715
            Cache_Ctrl       <= CACHE_PREFETCH;
716 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
717 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
718
            DP_Ctrl.Reg      <= SubOp;
719
 
720
          when OP_POP =>
721
            CPU_Next_State   <= POP_C1;
722
            Cache_Ctrl       <= CACHE_PREFETCH;
723 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
724 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
725
 
726
          when OP_BR0 | OP_BR1 =>
727
            CPU_Next_State   <= BRN_C1;
728
            Cache_Ctrl       <= CACHE_OPER1;
729 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
730 169 jshamlet
 
731
          when OP_DBNZ =>
732
            CPU_Next_State   <= DBNZ_C1;
733
            Cache_Ctrl       <= CACHE_OPER1;
734 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
735 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
736
            ALU_Ctrl.Reg     <= SubOp;
737
 
738
          when OP_INT =>
739 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
740 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
741
            --  Also, unlike CPU_Halt, the INT instruction is actually being
742
            --  executed, so go ahead and increment the program counter before
743
            --  pausing so the CPU restarts on the next instruction.
744 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
745 187 jshamlet
              CPU_Next_State <= WAI_Cx;
746 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
747
            end if;
748
 
749
          when OP_STK =>
750
            case SubOp is
751
              when SOP_RSP  =>
752 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
753 181 jshamlet
                if( not Allow_Stack_Address_Move )then
754 187 jshamlet
                  -- The default behavior for this instruction is to simply
755
                  --  repoint the SP to the HDL default
756 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
757 181 jshamlet
                end if;
758 187 jshamlet
                if( Allow_Stack_Address_Move and
759 270 jshamlet
                    Flags(STACK_XFER_FLAG) = '1' )then
760 187 jshamlet
                  -- If RSP is set to allow SP moves, and the specified flag
761
                  --  is true, then signal the stack pointer logic to load
762
                  --  from R1:R0
763 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
764 181 jshamlet
                end if;
765 187 jshamlet
                if( Allow_Stack_Address_Move and
766 270 jshamlet
                    Flags(STACK_XFER_FLAG) = '0')then
767 187 jshamlet
                  -- If RSP is set to allow SP moves, and the specified flag
768
                  --  is false, then signal the ALU to copy the stack pointer
769
                  --  to R1:R0
770 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
771 181 jshamlet
                end if;
772 169 jshamlet
 
773
              when SOP_RTS | SOP_RTI =>
774 185 jshamlet
                CPU_Next_State    <= RTS_C1;
775 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
776 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
777 169 jshamlet
 
778
              when SOP_BRK  =>
779
                if( BRK_Implements_WAI )then
780 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
781
                  --  increment the PC similar to an ISR flow.
782
                  CPU_Next_State  <= WAI_Cx;
783 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
784 187 jshamlet
                else
785
                -- If Break is implemented normally, back the PC up by
786 260 jshamlet
                --  2 and return through IPF_C0 in order to execute a 3
787 187 jshamlet
                --  clock cycle delay
788
                  CPU_Next_State  <= BRK_C1;
789
                  PC_Ctrl.Offset  <= PC_REV2;
790 169 jshamlet
                end if;
791
 
792
              when SOP_JMP  =>
793 185 jshamlet
                CPU_Next_State    <= JMP_C1;
794
                Cache_Ctrl        <= CACHE_OPER1;
795 169 jshamlet
 
796
              when SOP_SMSK =>
797 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
798 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
799
 
800
              when SOP_GMSK =>
801 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
802
                ALU_Ctrl.Oper     <= ALU_GMSK;
803 169 jshamlet
 
804
              when SOP_JSR =>
805 269 jshamlet
                CPU_Next_State    <= JSR_C1;
806 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
807 269 jshamlet
                DP_Ctrl.Src       <= DATA_WR_PC_H;
808 169 jshamlet
 
809
              when others => null;
810
            end case;
811
 
812
          when OP_MUL =>
813
            CPU_Next_State   <= MUL_C1;
814 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
815
            --  to the ALU writing the result to registers. As a result, this
816
            --  state needs to idle the ALU initially, and back the PC up by 1
817
            -- We can get away with only 1 extra clock by pre-fetching the
818
            --  next instruction, though.
819 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
820 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
821 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
822
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
823
            --  now, but hold off on the ALU command until the next state.
824 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
825
            ALU_Ctrl.Reg     <= SubOp;
826
 
827
          when OP_UPP =>
828
            CPU_Next_State   <= UPP_C1;
829
            Cache_Ctrl       <= CACHE_PREFETCH;
830 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
831 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
832
            ALU_Ctrl.Reg     <= SubOp;
833
 
834
          when OP_LDA =>
835
            CPU_Next_State   <= LDA_C1;
836
            Cache_Ctrl       <= CACHE_OPER1;
837
 
838
          when OP_LDI =>
839
            CPU_Next_State   <= LDI_C1;
840
            Cache_Ctrl       <= CACHE_OPER1;
841 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
842 169 jshamlet
 
843
          when OP_LDO =>
844
            CPU_Next_State   <= LDO_C1;
845
            Cache_Ctrl       <= CACHE_OPER1;
846 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
847 169 jshamlet
 
848
          when OP_LDX =>
849
            CPU_Next_State   <= LDX_C1;
850 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
851 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
852 169 jshamlet
 
853
          when OP_STA =>
854
            CPU_Next_State   <= STA_C1;
855
            Cache_Ctrl       <= CACHE_OPER1;
856
 
857
          when OP_STO =>
858
            CPU_Next_State   <= STO_C1;
859
            Cache_Ctrl       <= CACHE_OPER1;
860 252 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
861 169 jshamlet
 
862
          when OP_STX =>
863
            CPU_Next_State   <= STX_C1;
864
            Cache_Ctrl       <= CACHE_PREFETCH;
865 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
866 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
867
            DP_Ctrl.Reg      <= ACCUM;
868
 
869 244 jshamlet
          when OP_STP =>
870
            PC_Ctrl.Offset   <= PC_NEXT;
871
            if( Supervisor_Mode )then
872
              if( SubOp /= PSR_I )then
873
                ALU_Ctrl.Oper  <= Opcode;
874
                ALU_Ctrl.Reg   <= SubOp;
875
              end if;
876
            else
877
              ALU_Ctrl.Oper  <= Opcode;
878
              ALU_Ctrl.Reg   <= SubOp;
879
            end if;
880
 
881 169 jshamlet
          when others =>
882 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
883 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
884
            ALU_Ctrl.Reg     <= SubOp;
885
 
886
        end case;
887
 
888 186 jshamlet
        if( Int_Req = '1' )then
889
          CPU_Next_State     <= ISR_C1;
890 187 jshamlet
        end if;
891
 
892
        if( CPU_Halt_Req = '1' )then
893
          CPU_Next_State     <= WAH_Cx;
894
        end if;
895
 
896
        -- If either of these override conditions are true, the decoder needs
897
        --  to undo everything it just setup, since even "single-cycle"
898
        --  instructions will be executed again upon return.
899
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
900
          -- In either case, we want to skip loading the cache, as the cache
901
          --  will be invalid by the time we get back.
902 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
903 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
904
          -- compensating for the pipeline registers.
905 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
906
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
907 187 jshamlet
          --  operation due to the current instruction.
908 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
909
          SP_Ctrl.Oper       <= SP_IDLE;
910 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
911
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
912 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
913 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
914
          --  executed again when normal processing resumes, so axe their
915
          --  requests for now.
916
          INT_Ctrl.Mask_Set       <= '0';
917
          INT_Ctrl.Soft_Ints(Reg) <= '0';
918 186 jshamlet
        end if;
919
 
920 169 jshamlet
-------------------------------------------------------------------------------
921 270 jshamlet
-- Program Control (BRx, BNx, DBNZ, JMP )
922 169 jshamlet
-------------------------------------------------------------------------------
923
 
924
      when BRN_C1 =>
925 187 jshamlet
        CPU_Next_State       <= IDC_C0;
926 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
927 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
928 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
929 187 jshamlet
          CPU_Next_State     <= IPF_C0;
930 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
931
          PC_Ctrl.Offset     <= Operand1;
932
        end if;
933
 
934
      when DBNZ_C1 =>
935 187 jshamlet
        CPU_Next_State       <= IDC_C0;
936 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
937 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
938
        if( Flags(PSR_Z) = '0' )then
939 187 jshamlet
          CPU_Next_State     <= IPF_C0;
940 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
941
          PC_Ctrl.Offset     <= Operand1;
942
        end if;
943
 
944
      when JMP_C1 =>
945
        CPU_Next_State       <= JMP_C2;
946
        Cache_Ctrl           <= CACHE_OPER2;
947
 
948
      when JMP_C2 =>
949 187 jshamlet
        CPU_Next_State       <= IPF_C0;
950 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
951
 
952
-------------------------------------------------------------------------------
953
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
954
-------------------------------------------------------------------------------
955
 
956
      when LDA_C1 =>
957
        CPU_Next_State       <= LDA_C2;
958
        Cache_Ctrl           <= CACHE_OPER2;
959
 
960
      when LDA_C2 =>
961
        CPU_Next_State       <= LDA_C3;
962
 
963
      when LDA_C3 =>
964
        CPU_Next_State       <= LDA_C4;
965 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
966 169 jshamlet
 
967
      when LDA_C4 =>
968
        CPU_Next_State       <= LDI_C1;
969
        Cache_Ctrl           <= CACHE_OPER1;
970 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
971 169 jshamlet
 
972
      when LDI_C1 =>
973 187 jshamlet
        CPU_Next_State       <= IDC_C0;
974 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
975 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
976 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
977
        ALU_Ctrl.Reg         <= SubOp;
978
 
979
      when LDO_C1 =>
980 252 jshamlet
        CPU_Next_State       <= LDO_C2;
981
 
982
      when LDO_C2 =>
983 181 jshamlet
        CPU_Next_State       <= LDX_C2;
984 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
985 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
986
          ALU_Ctrl.Oper      <= ALU_UPP;
987
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
988 169 jshamlet
        end if;
989
 
990
      when LDX_C1 =>
991
        CPU_Next_State       <= LDX_C2;
992 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
993
          ALU_Ctrl.Oper      <= ALU_UPP;
994
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
995 181 jshamlet
        end if;
996 169 jshamlet
 
997
      when LDX_C2 =>
998
        CPU_Next_State       <= LDX_C3;
999 263 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1000
          ALU_Ctrl.Oper      <= ALU_UPP2;
1001
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '1';
1002
        end if;
1003 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1004 181 jshamlet
 
1005
      when LDX_C3 =>
1006
        CPU_Next_State       <= LDX_C4;
1007 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
1008 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1009 169 jshamlet
 
1010 181 jshamlet
      when LDX_C4 =>
1011 187 jshamlet
        CPU_Next_State       <= IDC_C0;
1012 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
1013 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1014 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
1015 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
1016
 
1017
-------------------------------------------------------------------------------
1018
-- Data Storage - Store to memory (STA, STO, STX)
1019
-------------------------------------------------------------------------------
1020
      when STA_C1 =>
1021
        CPU_Next_State       <= STA_C2;
1022
        Cache_Ctrl           <= CACHE_OPER2;
1023
        DP_Ctrl.Src          <= DATA_WR_REG;
1024
        DP_Ctrl.Reg          <= SubOp;
1025
 
1026
      when STA_C2 =>
1027
        CPU_Next_State       <= STA_C3;
1028 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1029 169 jshamlet
 
1030
      when STA_C3 =>
1031 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1032 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
1033 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1034 169 jshamlet
 
1035
      when STO_C1 =>
1036 252 jshamlet
        CPU_Next_State       <= STO_C2;
1037 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
1038 252 jshamlet
        DP_Ctrl.Src          <= DATA_WR_REG;
1039
        DP_Ctrl.Reg          <= ACCUM;
1040
 
1041
      when STO_C2 =>
1042
        CPU_Next_State       <= IPF_C1;
1043 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1044 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1045 252 jshamlet
          CPU_Next_State     <= STO_C3;
1046 182 jshamlet
          ALU_Ctrl.Oper      <= ALU_UPP;
1047
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
1048 169 jshamlet
        end if;
1049
 
1050 252 jshamlet
      when STO_C3 =>
1051
        CPU_Next_State       <= IPF_C2;
1052 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1053 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
1054
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
1055
 
1056
      when STX_C1 =>
1057 187 jshamlet
        CPU_Next_State       <= IPF_C1;
1058 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1059 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1060
          CPU_Next_State     <= STX_C2;
1061
          ALU_Ctrl.Oper      <= ALU_UPP;
1062
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
1063 169 jshamlet
        end if;
1064
 
1065
      when STX_C2 =>
1066 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1067 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1068 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
1069
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
1070
 
1071
-------------------------------------------------------------------------------
1072
-- Multi-Cycle Math Operations (UPP, MUL)
1073
-------------------------------------------------------------------------------
1074
 
1075
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
1076 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
1077
      --  need to tell the ALU to store the results to R1:R0 here. Note that
1078
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
1079 169 jshamlet
      when MUL_C1 =>
1080 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1081 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1082 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
1083
 
1084
      when UPP_C1 =>
1085 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1086 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1087 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
1088
        ALU_Ctrl.Reg         <= SubOp_p1;
1089
 
1090
-------------------------------------------------------------------------------
1091
-- Basic Stack Manipulation (PSH, POP, RSP)
1092
-------------------------------------------------------------------------------
1093
      when PSH_C1 =>
1094 187 jshamlet
        CPU_Next_State       <= IPF_C1;
1095 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
1096
 
1097
      when POP_C1 =>
1098
        CPU_Next_State       <= POP_C2;
1099
 
1100
      when POP_C2 =>
1101
        CPU_Next_State       <= POP_C3;
1102 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1103 169 jshamlet
 
1104
      when POP_C3 =>
1105
        CPU_Next_State       <= POP_C4;
1106
        Cache_Ctrl           <= CACHE_OPER1;
1107 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1108 169 jshamlet
 
1109
      when POP_C4 =>
1110 187 jshamlet
        CPU_Next_State       <= IDC_C0;
1111 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
1112 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1113 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
1114
        ALU_Ctrl.Reg         <= SubOp;
1115 172 jshamlet
 
1116 169 jshamlet
-------------------------------------------------------------------------------
1117
-- Subroutines & Interrupts (RTS, JSR)
1118
-------------------------------------------------------------------------------
1119 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
1120 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
1121 186 jshamlet
        if( Int_Req = '1' )then
1122
          CPU_Next_State     <= ISR_C1;
1123 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
1124
          --  instruction, compensating for the pipeline registers.
1125 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
1126
          DP_Ctrl.Src        <= DATA_RD_MEM;
1127
        end if;
1128 169 jshamlet
 
1129 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
1130 225 jshamlet
        CPU_Halt_Ack         <= '1';
1131 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
1132
        if( CPU_Halt_Req = '0' )then
1133
          CPU_Next_State     <= IPF_C0;
1134
          DP_Ctrl.Src        <= DATA_RD_MEM;
1135
        end if;
1136
 
1137
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
1138
        CPU_Next_State       <= IPF_C0;
1139
 
1140 169 jshamlet
      when ISR_C1 =>
1141
        CPU_Next_State       <= ISR_C2;
1142
        INT_Ctrl.Incr_ISR    <= '1';
1143
 
1144
      when ISR_C2 =>
1145
        CPU_Next_State       <= ISR_C3;
1146
        DP_Ctrl.Src          <= DATA_WR_FLAG;
1147
 
1148
      when ISR_C3 =>
1149
        CPU_Next_State       <= JSR_C1;
1150
        Cache_Ctrl           <= CACHE_OPER1;
1151 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
1152 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
1153 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
1154 269 jshamlet
        DP_Ctrl.Src          <= DATA_WR_PC_H;
1155 169 jshamlet
        Ack_D                <= '1';
1156
 
1157
      when JSR_C1 =>
1158
        CPU_Next_State       <= JSR_C2;
1159
        Cache_Ctrl           <= CACHE_OPER2;
1160
        SP_Ctrl.Oper         <= SP_PUSH;
1161 269 jshamlet
        DP_Ctrl.Src          <= DATA_WR_PC_L;
1162 169 jshamlet
 
1163
      when JSR_C2 =>
1164 187 jshamlet
        CPU_Next_State       <= IPF_C0;
1165 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
1166 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
1167 169 jshamlet
 
1168
      when RTS_C1 =>
1169
        CPU_Next_State       <= RTS_C2;
1170
        SP_Ctrl.Oper         <= SP_POP;
1171
 
1172
      when RTS_C2 =>
1173
        CPU_Next_State       <= RTS_C3;
1174
        -- if this is an RTI, then we need to POP the flags
1175
        if( SubOp = SOP_RTI )then
1176
          SP_Ctrl.Oper       <= SP_POP;
1177
        end if;
1178
 
1179
      when RTS_C3 =>
1180
        CPU_Next_State       <= RTS_C4;
1181
        Cache_Ctrl           <= CACHE_OPER1;
1182
 
1183
      when RTS_C4 =>
1184
        CPU_Next_State       <= RTS_C5;
1185
        Cache_Ctrl           <= CACHE_OPER2;
1186
 
1187
      when RTS_C5 =>
1188 187 jshamlet
        CPU_Next_State       <= IPF_C0;
1189 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
1190 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
1191 169 jshamlet
        if( SubOp = SOP_RTI )then
1192
          CPU_Next_State     <= RTI_C6;
1193
          Cache_Ctrl         <= CACHE_OPER1;
1194 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
1195
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
1196 169 jshamlet
        end if;
1197
 
1198
      when RTI_C6 =>
1199 187 jshamlet
        CPU_Next_State       <= IPF_C1;
1200 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1201 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
1202
 
1203
      when others =>
1204
        null;
1205
    end case;
1206
 
1207
  end process;
1208
 
1209
-------------------------------------------------------------------------------
1210
-- Registered portion of CPU finite state machine
1211
-------------------------------------------------------------------------------
1212 182 jshamlet
 
1213 169 jshamlet
  CPU_Regs: process( Reset, Clock )
1214
    variable Offset_SX       : ADDRESS_TYPE;
1215 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
1216 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
1217
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
1218
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
1219
  begin
1220
    if( Reset = Reset_Level )then
1221 187 jshamlet
      CPU_State              <= IPF_C0;
1222 260 jshamlet
 
1223
      CPU_Halt_Req           <= '0';
1224
      Halt_Ack               <= '0';
1225
 
1226 169 jshamlet
      Opcode                 <= OP_INC;
1227
      SubOp                  <= ACCUM;
1228
      SubOp_p1               <= ACCUM;
1229
      Operand1               <= x"00";
1230
      Operand2               <= x"00";
1231
      Instr_Prefetch         <= '0';
1232
      Prefetch               <= x"00";
1233
 
1234 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1235
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1236
      Open8_Bus.Rd_En        <= '1';
1237 169 jshamlet
 
1238
      Program_Ctr            <= Program_Start_Addr;
1239
      Stack_Ptr              <= Stack_Start_Addr;
1240
 
1241
      Ack_Q                  <= '0';
1242
      Ack_Q1                 <= '0';
1243
      Int_Ack                <= '0';
1244
 
1245
      Int_Req                <= '0';
1246
      Pending                <= x"00";
1247
      Wait_for_FSM           <= '0';
1248 210 jshamlet
      Wait_for_ISR           <= '0';
1249 245 jshamlet
      Set_Mask               <= '0';
1250 169 jshamlet
      if( Enable_NMI )then
1251
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
1252
      else
1253
        Int_Mask             <= Default_Interrupt_Mask;
1254
      end if;
1255 254 jshamlet
      ISR_Addr_Offset        <= INT_VECTOR_0;
1256 169 jshamlet
 
1257
      for i in 0 to 7 loop
1258 188 jshamlet
        Regfile(i)           <= x"00";
1259 169 jshamlet
      end loop;
1260
      Flags                  <= x"00";
1261 248 jshamlet
      if( Supervisor_Mode )then
1262 244 jshamlet
        Flags(PSR_I)         <= '1';
1263
      end if;
1264 169 jshamlet
 
1265 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
1266 188 jshamlet
 
1267 169 jshamlet
    elsif( rising_edge(Clock) )then
1268 187 jshamlet
 
1269 260 jshamlet
      CPU_State              <= CPU_Next_State;
1270
 
1271
-- Register the halt request and acknowledge lines
1272
 
1273 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
1274
      Halt_Ack               <= CPU_Halt_Ack;
1275 187 jshamlet
 
1276 169 jshamlet
-------------------------------------------------------------------------------
1277
-- Instruction/Operand caching for pipelined memory access
1278
-------------------------------------------------------------------------------
1279 260 jshamlet
 
1280
      -- To avoid putting too much load on the (usually massive) wire-OR'd bus,
1281
      --  the CPU loads Rd_Data into one of four registers - instruction,
1282
      --  operand 1 or 2, or the instruction prefetch registers. The first is
1283
      --  used to decode an instruction when the prefetch isn't valid, while
1284
      --  the two operand registers are used to hold any additional argument
1285
      --  for multi-byte instructions. Because of the memory pipelining, some
1286
      --  longer instructions can cache the next instruction as part of their
1287
      --  execution in a prefetch register, allowing the CPU to skip loading
1288
      --  it again later. Unfortunate, because instructions aren't all the same
1289
      --  length, it is not feasible to cache their operands without adding a
1290
      --  second partial decode stage that would obviate any savings.
1291
 
1292 169 jshamlet
      case Cache_Ctrl is
1293
        when CACHE_INSTR =>
1294
          Opcode             <= Rd_Data(7 downto 3);
1295
          SubOp              <= Rd_Data(2 downto 0);
1296
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
1297
          if( Instr_Prefetch = '1' )then
1298
            Opcode           <= Prefetch(7 downto 3);
1299
            SubOp            <= Prefetch(2 downto 0);
1300
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
1301
            Instr_Prefetch   <= '0';
1302
          end if;
1303
 
1304
        when CACHE_OPER1 =>
1305
          Operand1           <= Rd_Data;
1306
 
1307
        when CACHE_OPER2 =>
1308
          Operand2           <= Rd_Data;
1309
 
1310
        when CACHE_PREFETCH =>
1311
          Prefetch           <= Rd_Data;
1312
          Instr_Prefetch     <= '1';
1313
 
1314
        when CACHE_IDLE =>
1315
          null;
1316
      end case;
1317
 
1318
-------------------------------------------------------------------------------
1319
-- Program Counter
1320
-------------------------------------------------------------------------------
1321 260 jshamlet
 
1322
      -- The program counter is a bit unusual in that it always subtracts two
1323
      --  from itself plus the signed offset. This is because of the way the
1324
      --  assembler works when computing branches. Thus, to "IDLE" the counter,
1325
      --  the offset is set to 2, while "NEXT" sets the offset to 3. Depending
1326
      --  on how an instruction interacts with memory, or is pipelined,  the
1327
      --  offset can vary from -1 to 3
1328
 
1329 169 jshamlet
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1330
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1331
 
1332
      case PC_Ctrl.Oper is
1333
        when PC_INCR =>
1334
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1335
 
1336
        when PC_LOAD =>
1337 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1338 169 jshamlet
 
1339
        when others =>
1340
          null;
1341
      end case;
1342
 
1343
-------------------------------------------------------------------------------
1344
-- (Write) Data Path
1345
-------------------------------------------------------------------------------
1346 260 jshamlet
 
1347
      -- Note that this code handles both the Rd_En and Wr_En signals. These
1348
      --  were separated to make downstream logic simpler (As opposed to the
1349
      --  more classic RD_WRn and ADDR_STROBE scheme) It is also true to the
1350
      --  original core, which also had separate read and write enable outputs
1351
 
1352
      Open8_Bus.Wr_En        <= '0';
1353
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1354
      Open8_Bus.Rd_En        <= '0';
1355
 
1356 169 jshamlet
      case DP_Ctrl.Src is
1357
        when DATA_BUS_IDLE =>
1358
          null;
1359
 
1360
        when DATA_RD_MEM =>
1361 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1362 169 jshamlet
 
1363
        when DATA_WR_REG =>
1364 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1365
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1366 169 jshamlet
 
1367
        when DATA_WR_FLAG =>
1368 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1369
          Open8_Bus.Wr_Data  <= Flags;
1370 169 jshamlet
 
1371 269 jshamlet
        when DATA_WR_PC_L =>
1372 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1373 269 jshamlet
          Open8_Bus.Wr_Data  <= Program_Ctr(7 downto 0);
1374
 
1375
        when DATA_WR_PC_H =>
1376
          Open8_Bus.Wr_En    <= '1';
1377 223 jshamlet
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1378 169 jshamlet
 
1379
        when others =>
1380
          null;
1381
      end case;
1382
 
1383
-------------------------------------------------------------------------------
1384
-- Stack Pointer
1385
-------------------------------------------------------------------------------
1386
      case SP_Ctrl.Oper is
1387
        when SP_IDLE =>
1388
          null;
1389
 
1390 181 jshamlet
        when SP_CLR =>
1391 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1392
 
1393 181 jshamlet
        when SP_SET =>
1394 245 jshamlet
          if( Supervisor_Mode )then
1395
            if( Flags(PSR_I) = '1' )then
1396
              Stack_Ptr      <= Regfile(1) & Regfile(0);
1397
            end if;
1398
          else
1399
            Stack_Ptr        <= Regfile(1) & Regfile(0);
1400
          end if;
1401 181 jshamlet
 
1402 169 jshamlet
        when SP_POP  =>
1403
          Stack_Ptr          <= Stack_Ptr + 1;
1404
 
1405
        when SP_PUSH =>
1406
          Stack_Ptr          <= Stack_Ptr - 1;
1407
 
1408
        when others =>
1409
          null;
1410
 
1411
      end case;
1412
 
1413
-------------------------------------------------------------------------------
1414
-- Interrupt Controller
1415
-------------------------------------------------------------------------------
1416 245 jshamlet
 
1417
      -- If Supervisor_Mode is set, restrict the SMSK instruction such that it
1418
      --  requires the I bit to be set.
1419
      if( Supervisor_Mode )then
1420
        Set_Mask             <= INT_Ctrl.Mask_Set and Flags(PSR_I);
1421
      else
1422
        Set_Mask             <= INT_Ctrl.Mask_Set;
1423
      end if;
1424
 
1425 169 jshamlet
      -- The interrupt control mask is always sourced out of R0
1426 245 jshamlet
      if( Set_Mask = '1' )then
1427 169 jshamlet
        if( Enable_NMI )then
1428
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1429
        else
1430
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1431
        end if;
1432
      end if;
1433
 
1434
      -- Combine external and internal interrupts, and mask the OR of the two
1435
      --  with the mask. Record any incoming interrupts to the pending buffer
1436
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1437
                                Int_Mask;
1438 172 jshamlet
 
1439 169 jshamlet
      Pending                <= i_Ints or Pending;
1440
 
1441 260 jshamlet
      -- If Sequential_Interrupts is set true, Wait_for_ISR should follow the
1442
      --  I bit, preventing a new interrupt from starting until the I bit is
1443
      --  cleared.
1444 210 jshamlet
      if( Sequential_Interrupts )then
1445
        Wait_for_ISR         <= Flags(PSR_I);
1446
      else
1447
        Wait_for_ISR         <= '0';
1448
      end if;
1449
 
1450
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1451 169 jshamlet
        if(    Pending(0) = '1' )then
1452 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_0;
1453 169 jshamlet
          Pending(0)         <= '0';
1454
        elsif( Pending(1) = '1' )then
1455 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_1;
1456 169 jshamlet
          Pending(1)         <= '0';
1457
        elsif( Pending(2) = '1' )then
1458 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_2;
1459 169 jshamlet
          Pending(2)         <= '0';
1460
        elsif( Pending(3) = '1' )then
1461 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_3;
1462 169 jshamlet
          Pending(3)         <= '0';
1463
        elsif( Pending(4) = '1' )then
1464 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_4;
1465 169 jshamlet
          Pending(4)         <= '0';
1466
        elsif( Pending(5) = '1' )then
1467 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_5;
1468 169 jshamlet
          Pending(5)         <= '0';
1469
        elsif( Pending(6) = '1' )then
1470 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_6;
1471 169 jshamlet
          Pending(6)         <= '0';
1472
        elsif( Pending(7) = '1' )then
1473 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_7;
1474 169 jshamlet
          Pending(7)         <= '0';
1475
        end if;
1476 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1477 169 jshamlet
      end if;
1478
 
1479
      -- Reset the Wait_for_FSM flag on Int_Ack
1480
      Ack_Q                  <= Ack_D;
1481
      Ack_Q1                 <= Ack_Q;
1482
      Int_Ack                <= Ack_Q1;
1483
      if( Int_Ack = '1' )then
1484
        Wait_for_FSM         <= '0';
1485
      end if;
1486
 
1487
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1488
 
1489
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1490
      --  lower half of the address.
1491
      if( INT_Ctrl.Incr_ISR = '1' )then
1492 254 jshamlet
        ISR_Addr_Offset             <= ISR_Addr_Offset + 1;
1493 169 jshamlet
      end if;
1494
 
1495
-------------------------------------------------------------------------------
1496
-- ALU (Arithmetic / Logic Unit)
1497
-------------------------------------------------------------------------------
1498 260 jshamlet
 
1499
      -- The ALU code is responsible for (and should be the only code altering)
1500
      --  the register file. Most of the "instructions" directly map to opcodes
1501
      --  but a few are for internal use only, such as operations involving the
1502 263 jshamlet
      --  stack pointer or interrupt mask.
1503 260 jshamlet
 
1504 169 jshamlet
      Index                  := conv_integer(ALU_Ctrl.Reg);
1505
      Sum                    := (others => '0');
1506
      Temp                   := (others => '0');
1507
 
1508
      case ALU_Ctrl.Oper is
1509
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1510
          Sum                := ("0" & x"01") +
1511
                                ("0" & Regfile(Index));
1512 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1513
          Flags(PSR_C)       <= Sum(8);
1514 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1515 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1516
 
1517
        when ALU_UPP => -- Rn = Rn + 1
1518
          Sum                := ("0" & x"01") +
1519
                                ("0" & Regfile(Index));
1520 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1521 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1522
 
1523
        when ALU_UPP2 => -- Rn = Rn + C
1524 263 jshamlet
          Sum                := (x"00" & Flags(PSR_C)) +
1525
                                ("0" & Regfile(Index));
1526 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1527 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1528
 
1529
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1530
          Sum                := ("0" & Regfile(0)) +
1531
                                ("0" & Regfile(Index)) +
1532 185 jshamlet
                                Flags(PSR_C);
1533
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1534
          Flags(PSR_C)       <= Sum(8);
1535
          Flags(PSR_N)       <= Sum(7);
1536 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1537
 
1538
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1539
          Temp               := "0" & Regfile(Index);
1540 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1541
          Flags(PSR_N)       <= Temp(7);
1542 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1543
 
1544
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1545
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1546 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1547
          Flags(PSR_N)       <= Temp(7);
1548 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1549
 
1550
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1551
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1552 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1553
          Flags(PSR_N)       <= Temp(7);
1554 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1555
 
1556
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1557
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1558 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1559
          Flags(PSR_N)       <= Temp(7);
1560 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1561
 
1562
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1563 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1564
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1565
          Flags(PSR_C)       <= Temp(8);
1566
          Flags(PSR_N)       <= Temp(7);
1567 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1568
 
1569
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1570 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1571 169 jshamlet
                                Regfile(Index)(7 downto 1);
1572 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1573
          Flags(PSR_C)       <= Temp(8);
1574
          Flags(PSR_N)       <= Temp(7);
1575 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1576
 
1577
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1578
          Sum                := ("0" & Regfile(Index)) +
1579
                                ("0" & x"FF");
1580 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1581
          Flags(PSR_C)       <= Sum(8);
1582
          Flags(PSR_N)       <= Sum(7);
1583 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1584
 
1585
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1586
          Sum                := ("0" & Regfile(0)) +
1587
                                ("1" & (not Regfile(Index))) +
1588 185 jshamlet
                                Flags(PSR_C);
1589
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1590
          Flags(PSR_C)       <= Sum(8);
1591
          Flags(PSR_N)       <= Sum(7);
1592 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1593
 
1594
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1595
          Sum                := ("0" & Regfile(0)) +
1596
                                ("0" & Regfile(Index));
1597 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1598 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1599 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1600
          Flags(PSR_N)       <= Sum(7);
1601 169 jshamlet
 
1602
        when ALU_STP => -- Sets bit(n) in the Flags register
1603
          Flags(Index)       <= '1';
1604
 
1605
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1606 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1607
          Flags(PSR_N)       <= Regfile(0)(7);
1608 169 jshamlet
 
1609
        when ALU_CLP => -- Clears bit(n) in the Flags register
1610
          Flags(Index)       <= '0';
1611
 
1612
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1613
          Temp               := "0" & Regfile(0);
1614 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1615
          Flags(PSR_N)       <= Temp(7);
1616 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1617
 
1618
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1619
          Sum                := ("0" & Regfile(0)) +
1620
                                ("1" & (not Regfile(Index))) +
1621
                                '1';
1622 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1623
          Flags(PSR_C)       <= Sum(8);
1624
          Flags(PSR_N)       <= Sum(7);
1625 169 jshamlet
 
1626
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1627
          Regfile(0)         <= Mult(7 downto 0);
1628
          Regfile(1)         <= Mult(15 downto 8);
1629 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1630 169 jshamlet
 
1631
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1632 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1633
          Flags(PSR_N)       <= Operand1(7);
1634
          Regfile(Index)     <= Operand1;
1635 169 jshamlet
 
1636
        when ALU_POP => -- Rn <= Data
1637 185 jshamlet
          Regfile(Index)     <= Operand1;
1638 169 jshamlet
 
1639
        when ALU_RFLG =>
1640 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1641
          if( not RTI_Ignores_GP_Flags )then
1642
            Flags(7 downto 4)<= Operand1(7 downto 4);
1643
          end if;
1644 169 jshamlet
 
1645 185 jshamlet
        when ALU_RSP =>
1646 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1647
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1648
 
1649 185 jshamlet
        when ALU_GMSK =>
1650
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1651
          Regfile(0)         <= Int_Mask;
1652
 
1653 169 jshamlet
        when others =>
1654
          null;
1655
      end case;
1656
 
1657 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1658 188 jshamlet
 
1659 169 jshamlet
    end if;
1660
  end process;
1661
 
1662 182 jshamlet
-------------------------------------------------------------------------------
1663
-- Multiplier Logic
1664
--
1665
-- We need to infer a hardware multipler, so we create a special clocked
1666
--  process with no reset or clock enable
1667
-------------------------------------------------------------------------------
1668
 
1669
  Multiplier_proc: process( Clock )
1670
  begin
1671
    if( rising_edge(Clock) )then
1672
      Mult                   <= Regfile(0) *
1673 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1674
    end if;
1675
  end process;
1676
 
1677
end architecture;

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