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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Blame information for rev 299

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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020, 2022
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--  Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 169 jshamlet
--
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-- VHDL Units :  o8_cpu
26 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
27
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
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--            :
29
-- Notes      :  Generic definitions
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--            :
31
--            :  Program_Start_Addr sets the initial value of the program
32
--            :   counter.
33
--            :
34
--            :  ISR_Start_Addr sets the location of the interrupt service
35
--            :   vector table. There are 8 service vectors, or 16 bytes, which
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--            :   must be allocated to either ROM or RAM.
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--            :
38
--            :  Stack_Start_Address sets the initial (reset) value of the
39
--            :   stack pointer. Also used for the RSP instruction if
40
--            :   Allow_Stack_Address_Move is false.
41
--            :
42
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
43 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
44
--            :   instruction changes into TSX or TXS based on the flag
45 270 jshamlet
--            :   specified by STACK_XFER_FLAG. If the flag is '0', RSP will
46 181 jshamlet
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
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--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
48
--            :   allows the processor to backup and restore stack pointers
49
--            :   in a multi-process environment. Note that no flags are
50
--            :   modified by either form of this instruction.
51 169 jshamlet
--            :
52 270 jshamlet
--            :  STACK_XFER_FLAG instructs the core to use the specified ALU
53 181 jshamlet
--            :   flag to alter the behavior of the RSP instruction when
54 256 jshamlet
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it's ignored.
55 181 jshamlet
--            :   While technically any of the status bits may be used, the
56
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
57
--            :   by ordinary ALU operations.
58
--            :
59 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
60
--            :   indexed instructions such that specifying an odd register
61
--            :   will use the next lower register pair, post-incrementing the
62
--            :   value in that pair. IOW, specifying STX R1 will instead
63
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
64
--            :
65
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
66
--            :   triggers the wait for interrupt state, but without triggering
67
--            :   a soft interrupt in lieu of its normal behavior, which is to
68
--            :   insert several dead clock cycles - essentially a long NOP
69
--            :
70
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
71
--            :   non-maskable interrupt at the highest priority. To remain
72
--            :   true to the original core, this should be set false.
73
--            :
74 260 jshamlet
--            :  Sequential_Interrupts, when set, prevents interrupt service
75
--            :   routines from  being interrupted by postponing an later
76
--            :   interrupts until the I bit is cleared (usually with an RTI,
77
--            :   but a CLP PSR_I will also work). This is potentially
78
--            :   dangerous, as it means a lower-priority ISR can "hog" the CPU
79
--            :   by failing to return. However, it can also prevent the
80
--            :   condition of an ISR interrupting itself until it causes a
81
--            :   memory fault. (For example, an interrupt source that whose
82
--            :   period is shorter than the ISR service time) Note that this
83
--            :   setting alters the way the pending logic works, so it affects
84
--            :   all interrupts, including the NMI. If this is set, special
85
--            :   care should be taken to make sure ISRs are short and always
86
--            :   execute an RTI at the end.
87
--            :
88 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
89
--            :   after an interrupt. By default, all of the flag bits are put
90
--            :   back to their original state. If this flag is set true, only
91
--            :   the lower four bits are restored, allowing ISR code to alter
92
--            :   the GP flags persistently.
93
--            :
94 244 jshamlet
--            :  Supervisor_Mode, when set, disables the STP PSR_I instruction
95
--            :   preventing code from setting the I bit. When enabled, only
96
--            :   interrupts can set the I bit, allowing for more robust memory
97
--            :   protection by preventing errant code execution from
98
--            :   inadvertently entering an interrupt state.
99
--            :
100 248 jshamlet
--            :   This setting also sets I bit at startup so that any
101
--            :   initialization code may be run in an ISR context, initially
102
--            :   bypassing memory protection. Init code should clear the I bit
103
--            :   when done;
104 244 jshamlet
--            :
105 255 jshamlet
--            :  Unsigned_Index_Offsets alters the way offsets are added to
106 260 jshamlet
--            :   [Rn+1:Rn] during LDO/STO instructions. The original, default
107 255 jshamlet
--            :   behavior treats these offsets as signed values, allowing
108
--            :   instructions to offset by -128 to +127 from [Rn+1:Rn].
109
--            :   Setting this generic to TRUE will switch to unsigned offsets,
110
--            :   switching the range to 0 to 255 instead.
111
--            :
112 290 jshamlet
--            :  Rotate_Ignores_Carry alters the ROL and ROR instructions to 
113
--            :   not rotate through, or alter, the carry bit. When enabled,
114
--            :   ROL performs Rn <= Rn<<1 and ROR performs Rn <= 1>>Rn. Note
115
--            :   that unlike the original instructions, the C bit is not
116
--            :   altered.
117
--            :
118 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
119
--            :   interrupt mask. To remain true to the original core, which
120
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
121
--            :   it can be initialized to any value. Note that Enable_NMI
122
--            :   will logically force the LSB high.
123 172 jshamlet
--            :
124 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
125
--            :   on a high or low level from higher logic.
126
--            :
127
--            : Architecture notes
128
--            :  This model deviates from the original ISA in a few important
129
--            :   ways.
130
--            :
131
--            :  First, there is only one set of registers. Interrupt service
132
--            :   routines must explicitely preserve context since the the
133
--            :   hardware doesn't. This was done to decrease size and code
134
--            :   complexity. Older code that assumes this behavior will not
135
--            :   execute correctly on this processor model.
136
--            :
137
--            :  Second, this model adds an additional pipeline stage between
138
--            :   the instruction decoder and the ALU. Unfortunately, this
139
--            :   means that the instruction stream has to be restarted after
140
--            :   any math instruction is executed, implying that any ALU
141
--            :   instruction now has a latency of 2 instead of 0. The
142
--            :   advantage is that the maximum frequency has gone up
143
--            :   significantly, as the ALU code is vastly more efficient.
144
--            :   As an aside, this now means that all math instructions,
145
--            :   including MUL (see below) and UPP have the same instruction
146
--            :   latency.
147
--            :
148
--            :  Third, the original ISA, also a soft core, had two reserved
149
--            :   instructions, USR and USR2. These have been implemented as
150
--            :   DBNZ, and MUL respectively.
151
--            :
152
--            :  DBNZ decrements the specified register and branches if the
153
--            :   result is non-zero. The instruction effectively executes a
154
--            :   DEC Rn instruction prior to branching, so the same flags will
155
--            :   be set.
156
--            :
157
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
158
--            :   latency is identical to other ALU instructions. Only the Z
159
--            :   flag is set, since there is no defined overflow or "negative
160
--            :   16-bit values"
161
--            :
162
--            :  Fourth, indexed load/store instructions now have an (optional)
163
--            :   ability to post-increment their index registers. If enabled,
164
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
165
--            :   register pair to be incremented after the storage access.
166
--            :
167
--            :  Fifth, the RSP instruction has been (optionally) altered to
168
--            :   allow the stack pointer to be sourced from R1:R0.
169
--            :
170
--            :  Sixth, the BRK instruction can optionally implement a WAI,
171
--            :   which is the same as the INT instruction without the soft
172
--            :   interrupt, as a way to put the processor to "sleep" until the
173
--            :   next external interrupt.
174
--            :
175
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
176
--            :   with priority. This model has the same 8 interrupts, but
177 172 jshamlet
--            :   allows software to mask them (with an additional option to
178 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
179
--            :
180
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
181
--            :   were repurposed to support a new interrupt mask.
182
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
183
--            :   to/from the interrupt mask register. SMSK is immediate, while
184
--            :   GMSK has the same overhead as a math instruction.
185
--
186
-- Revision History
187
-- Author          Date     Change
188
------------------ -------- ---------------------------------------------------
189
-- Seth Henry      07/19/06 Design Start
190
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
191
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
192
--                           corruption issues.
193
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
194
--                           path sections.
195
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
196
--                           single entity.
197
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
198
--                           processor to wait for an interrupt instead of the
199
--                           normal BRK behavior.
200 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
201 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
202
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
203
--                           faster logic that simply does priority encoding.
204
-- Seth Henry      08/06/13 Removed HALT functionality
205
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
206 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
207 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
208
--                           allowing true backup/restore of the stack pointer
209 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
210
--                           in order to simplify things and eliminate
211
--                           redundancies. Came across and fixed a problem with
212
--                           the STO instruction when Enable_Auto_Increment is
213
--                           NOT set.
214 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
215
--                           the assembler names. Also fixed an issue where
216
--                           the I bit wasn't being cleared after interrupts.
217
--                          Simplified the program counter logic to only use
218
--                           the offset for increments, redefining the
219
--                           original modes as fixed offset values.
220
--                          Modified the ALU section with a new ALU operation
221
--                           for GMSK. This allowed the .data field to be
222
--                           removed and Operand1 used in its place, which
223
--                           simplified the logic a great deal.
224 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
225
--                           the instruction decode state, where it acts as a
226
--                           modified form of the BRK instruction that holds
227
--                           state until CPU_Halt is deasserted. This has a
228
--                           much smaller impact on Fmax/complexity than the
229
--                           original clock enable, but imposes a mild impact
230
--                           due to the need to reset the instruction pipeline
231 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
232
--                           the flags, including the general purpose ones, or
233
--                           only the core ALU flags (Z, N, and C). Also
234
--                           brought out copies of the GP flags for external
235
--                           connection.
236 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
237
--                           while the I bit is set to avoid reentering ISRs
238
--                           This may slightly affect timing, as this will
239
--                           potentially block higher priority interrupts
240
--                           until the lower priority ISR returns or clears
241
--                           the I bit.
242
--                          Also added the I bit to the exported flags for
243
--                           use in memory protection schemes.
244 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
245 225 jshamlet
--                           reset and usec_tick logic to drive utility
246
--                           signals. Also added Halt_Ack output.
247 244 jshamlet
-- Seth Henry      05/20/20 Added two new generics to alter the way the I bit
248
--                           is handled. The Supervisor_Mode setting disables
249
--                           STP PSR_I from being executed, preventing it
250
--                           from being set outside of an ISR. The
251
--                           Default_Int_Flag setting allows the I bit to
252
--                           start set so that initialization code can run,
253
--                           but not be hijacked later to corrupt any memory
254
--                           write protection later.
255 245 jshamlet
-- Seth Henry      05/21/20 Supervisor_Mode now protects the interrupt mask
256
--                           and stack pointer as well.
257 248 jshamlet
-- Seth Henry      05/24/20 Removed the Default_Int_Flag, as it is covered by
258
--                           Supervisor_Mode. If Supervisor_Mode isn't set,
259
--                           code can simply use STP to set the bit
260 252 jshamlet
-- Seth Henry      06/09/20 Added ability to use unsigned index offsets for
261 253 jshamlet
--                           LDO/STO. Also pipelined the address calculation
262 252 jshamlet
--                           for indexed instructions, reducing the final
263
--                           address generator to a multiplexor fed only by
264
--                           registers.
265 264 jshamlet
-- Seth Henry      07/10/20 Fixed a bug in the LDO/LDX logic where the register
266
--                           pair wasn't being incremented properly due to a
267
--                           missing UPP2 signal to the ALU.
268 269 jshamlet
-- Seth Henry      10/21/20 Modified the write data path to use separate
269
--                           enumerated states rather than reuse the .reg field
270
--                           to improve performance.
271 270 jshamlet
-- Seth Henry      10/23/20 Moved CPU internal constants to o8_cpu.vhd. Also
272
--                           removed Stack_Xfer_Flag, which specified the CPU
273
--                           flag used to alter the RSP instruction, making it
274
--                           a constant instead (PSR_GP4). This eliminated the
275
--                           need to expose an internal constant externally
276 290 jshamlet
-- Seth Henry      05/01/21 Added the Rotate_Ignores_Carry generic, which
277
--                           alters the ROR and ROL instructions to behave more
278
--                           like expected by not rotating through the C flag
279 298 jshamlet
-- Seth Henry      07/12/22 Fixed a long-standing bug in the SBC instruction
280
--                           where the 2's complement inversion wasn't adding
281
--                           the additional 1, causing off by 1 errors
282 169 jshamlet
 
283
library ieee;
284
  use ieee.std_logic_1164.all;
285
  use ieee.std_logic_unsigned.all;
286
  use ieee.std_logic_arith.all;
287
  use ieee.std_logic_misc.all;
288
 
289
library work;
290 227 jshamlet
  use work.Open8_pkg.all;
291 169 jshamlet
 
292 183 jshamlet
entity o8_cpu is
293 169 jshamlet
  generic(
294
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
295
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
296
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
297
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
298
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
299
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
300
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
301 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
302 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
303 244 jshamlet
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
304 252 jshamlet
    Unsigned_Index_Offsets   : boolean      := false;   -- Offsets are signed
305 290 jshamlet
    Rotate_Ignores_Carry     : boolean      := false;   -- Rotate thru Carry
306 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
307 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
308
);
309 169 jshamlet
  port(
310
    Clock                    : in  std_logic;
311 224 jshamlet
    PLL_Locked               : in  std_logic;
312 169 jshamlet
    --
313 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
314
    Halt_Ack                 : out std_logic;
315
    --
316 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
317 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
318 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
319
);
320 169 jshamlet
end entity;
321
 
322 183 jshamlet
architecture behave of o8_cpu is
323 169 jshamlet
 
324 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
325
  signal Reset               : std_logic := Reset_Level;
326
 
327
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
328
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
329
  constant USEC_DLY          : std_logic_vector :=
330
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
331
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
332
  signal uSec_Tick           : std_logic;
333
 
334 270 jshamlet
  -- CPU Instruction Set Definitions
335
  subtype OPCODE_TYPE  is std_logic_vector(4 downto 0);
336
  subtype SUBOP_TYPE   is std_logic_vector(2 downto 0);
337
 
338
  -- All opcodes should be identical to the opcode used by the assembler
339
  -- In this case, they match the original V8/ARC uRISC ISA
340
  constant OP_INC            : OPCODE_TYPE := "00000";
341
  constant OP_ADC            : OPCODE_TYPE := "00001";
342
  constant OP_TX0            : OPCODE_TYPE := "00010";
343
  constant OP_OR             : OPCODE_TYPE := "00011";
344
  constant OP_AND            : OPCODE_TYPE := "00100";
345
  constant OP_XOR            : OPCODE_TYPE := "00101";
346
  constant OP_ROL            : OPCODE_TYPE := "00110";
347
  constant OP_ROR            : OPCODE_TYPE := "00111";
348
  constant OP_DEC            : OPCODE_TYPE := "01000";
349
  constant OP_SBC            : OPCODE_TYPE := "01001";
350
  constant OP_ADD            : OPCODE_TYPE := "01010";
351
  constant OP_STP            : OPCODE_TYPE := "01011";
352
  constant OP_BTT            : OPCODE_TYPE := "01100";
353
  constant OP_CLP            : OPCODE_TYPE := "01101";
354
  constant OP_T0X            : OPCODE_TYPE := "01110";
355
  constant OP_CMP            : OPCODE_TYPE := "01111";
356
  constant OP_PSH            : OPCODE_TYPE := "10000";
357
  constant OP_POP            : OPCODE_TYPE := "10001";
358
  constant OP_BR0            : OPCODE_TYPE := "10010";
359
  constant OP_BR1            : OPCODE_TYPE := "10011";
360
  constant OP_DBNZ           : OPCODE_TYPE := "10100"; -- USR
361
  constant OP_INT            : OPCODE_TYPE := "10101";
362
  constant OP_MUL            : OPCODE_TYPE := "10110"; -- USR2
363
  constant OP_STK            : OPCODE_TYPE := "10111";
364
  constant OP_UPP            : OPCODE_TYPE := "11000";
365
  constant OP_STA            : OPCODE_TYPE := "11001";
366
  constant OP_STX            : OPCODE_TYPE := "11010";
367
  constant OP_STO            : OPCODE_TYPE := "11011";
368
  constant OP_LDI            : OPCODE_TYPE := "11100";
369
  constant OP_LDA            : OPCODE_TYPE := "11101";
370
  constant OP_LDX            : OPCODE_TYPE := "11110";
371
  constant OP_LDO            : OPCODE_TYPE := "11111";
372
 
373
  -- OP_STK uses the lower 3 bits to further refine the instruction by
374
  --  repurposing the source register field. These "sub opcodes" take
375
  --  the place of the register select for the OP_STK opcode
376
  constant SOP_RSP           : SUBOP_TYPE := "000";
377
  constant SOP_RTS           : SUBOP_TYPE := "001";
378
  constant SOP_RTI           : SUBOP_TYPE := "010";
379
  constant SOP_BRK           : SUBOP_TYPE := "011";
380
  constant SOP_JMP           : SUBOP_TYPE := "100";
381
  constant SOP_SMSK          : SUBOP_TYPE := "101";
382
  constant SOP_GMSK          : SUBOP_TYPE := "110";
383
  constant SOP_JSR           : SUBOP_TYPE := "111";
384
 
385
  -- These should match the assembler's definitions for the flags
386
  constant PSR_Z             : integer := 0;
387
  constant PSR_C             : integer := 1;
388
  constant PSR_N             : integer := 2;
389
  constant PSR_I             : integer := 3;
390
  constant PSR_GP4           : integer := 4;
391
  constant PSR_GP5           : integer := 5;
392
  constant PSR_GP6           : integer := 6;
393
  constant PSR_GP7           : integer := 7;
394
 
395
  -- Internal CPU Signals & Constants
396
 
397
  type CPU_STATES is (
398
      -- Instruction fetch & Decode
399
    IPF_C0, IPF_C1, IPF_C2, IDC_C0,
400
    -- Branching
401
    BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
402
    -- Loads
403
    LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
404
    LDO_C1, LDO_C2, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
405
    -- Stores
406
    STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STO_C3, STX_C1, STX_C2,
407
    -- 2-cycle math
408
    MUL_C1, UPP_C1,
409
    -- Stack
410
    PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
411
    -- Subroutines & Interrupts
412
    WAI_Cx, WAH_Cx, BRK_C1,
413
    ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
414
    RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6
415
     );
416
 
417
  type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
418
                       CACHE_PREFETCH );
419
 
420
  type PC_MODES is ( PC_INCR, PC_LOAD );
421
 
422
  type PC_CTRL_TYPE is record
423
    Oper                     : PC_MODES;
424
    Offset                   : DATA_TYPE;
425
  end record;
426
 
427
  -- These are fixed constant offsets to the program counter logic, which is
428
  --  always either incrementing or loading.
429
  constant PC_NEXT           : DATA_TYPE := x"03";
430
  constant PC_IDLE           : DATA_TYPE := x"02";
431
  constant PC_REV1           : DATA_TYPE := x"01";
432
  constant PC_REV2           : DATA_TYPE := x"00";
433
  constant PC_REV3           : DATA_TYPE := x"FF";
434
 
435
  type SP_MODES is ( SP_IDLE, SP_CLR, SP_SET, SP_POP, SP_PUSH );
436
 
437
  type SP_CTRL_TYPE is record
438
    Oper                     : SP_MODES;
439
  end record;
440
 
441
  -- This constant determines which CPU flag is used to switch the
442
  --  direction of the modified RSP instruction
443
  constant STACK_XFER_FLAG   : integer := PSR_GP4; -- GP4 modifies RSP
444
 
445
  type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
446
                     DATA_WR_REG, DATA_WR_FLAG,
447
                     DATA_WR_PC_L, DATA_WR_PC_H );
448
 
449
  type DATA_CTRL_TYPE is record
450
    Src                      : DP_MODES;
451
    Reg                      : SUBOP_TYPE;
452
  end record;
453
 
454
  type INT_CTRL_TYPE is record
455
    Mask_Set                 : std_logic;
456
    Soft_Ints                : INTERRUPT_BUNDLE;
457
    Incr_ISR                 : std_logic;
458
  end record;
459
 
460
  -- Most of the ALU instructions are the same as their Opcode equivalents,
461
  --  with exceptions for IDLE, UPP2, RFLG, RSP, and GMSK, which perform
462
  --  internal operations not otherwise exposed by the instruction set.
463
  constant ALU_INC           : OPCODE_TYPE := "00000"; -- x"00"
464
  constant ALU_ADC           : OPCODE_TYPE := "00001"; -- x"01"
465
  constant ALU_TX0           : OPCODE_TYPE := "00010"; -- x"02"
466
  constant ALU_OR            : OPCODE_TYPE := "00011"; -- x"03"
467
  constant ALU_AND           : OPCODE_TYPE := "00100"; -- x"04"
468
  constant ALU_XOR           : OPCODE_TYPE := "00101"; -- x"05"
469
  constant ALU_ROL           : OPCODE_TYPE := "00110"; -- x"06"
470
  constant ALU_ROR           : OPCODE_TYPE := "00111"; -- x"07"
471
  constant ALU_DEC           : OPCODE_TYPE := "01000"; -- x"08"
472
  constant ALU_SBC           : OPCODE_TYPE := "01001"; -- x"09"
473
  constant ALU_ADD           : OPCODE_TYPE := "01010"; -- x"0A"
474
  constant ALU_STP           : OPCODE_TYPE := "01011"; -- x"0B"
475
  constant ALU_BTT           : OPCODE_TYPE := "01100"; -- x"0C"
476
  constant ALU_CLP           : OPCODE_TYPE := "01101"; -- x"0D"
477
  constant ALU_T0X           : OPCODE_TYPE := "01110"; -- x"0E"
478
  constant ALU_CMP           : OPCODE_TYPE := "01111"; -- x"0F"
479
  constant ALU_POP           : OPCODE_TYPE := "10001"; -- x"11"
480
  constant ALU_MUL           : OPCODE_TYPE := "10110"; -- x"16"
481
  constant ALU_UPP           : OPCODE_TYPE := "11000"; -- x"18"
482
  constant ALU_LDI           : OPCODE_TYPE := "11100"; -- x"1C"
483
 
484
  constant ALU_IDLE          : OPCODE_TYPE := "10000"; -- x"10"
485
  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"12"
486
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"13"
487
  constant ALU_RSP           : OPCODE_TYPE := "10111"; -- x"17"
488
  constant ALU_GMSK          : OPCODE_TYPE := "11111"; -- x"1F"
489
 
490
  type ALU_CTRL_TYPE is record
491
    Oper                     : OPCODE_TYPE;
492
    Reg                      : SUBOP_TYPE;
493
  end record;
494
 
495
  constant ACCUM             : SUBOP_TYPE := "000";
496
 
497
  type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
498
 
499
  subtype FLAG_TYPE is DATA_TYPE;
500
 
501 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
502
  signal CPU_State           : CPU_STATES := IPF_C0;
503 169 jshamlet
 
504 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
505
  signal CPU_Halt_Ack        : std_logic := '0';
506 187 jshamlet
 
507 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
508
 
509
  signal Opcode              : OPCODE_TYPE := (others => '0');
510
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
511
 
512
  signal Prefetch            : DATA_TYPE   := x"00";
513
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
514
 
515
  signal Instr_Prefetch      : std_logic   := '0';
516
 
517
  signal PC_Ctrl             : PC_CTRL_TYPE;
518
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
519
 
520 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
521
  signal Regfile             : REGFILE_TYPE;
522
  signal Flags               : FLAG_TYPE;
523
  signal Mult                : ADDRESS_TYPE := x"0000";
524
 
525 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
526
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
527
 
528
  signal DP_Ctrl             : DATA_CTRL_TYPE;
529
 
530
  signal INT_Ctrl            : INT_CTRL_TYPE;
531
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
532
  signal Int_Req, Int_Ack    : std_logic   := '0';
533 245 jshamlet
  signal Set_Mask            : std_logic   := '0';
534 169 jshamlet
  signal Int_Mask            : DATA_TYPE   := x"00";
535
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
536
  signal Pending             : INTERRUPT_BUNDLE := x"00";
537
  signal Wait_for_FSM        : std_logic := '0';
538 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
539 169 jshamlet
 
540 254 jshamlet
  alias  ISR_Addr_Base       is ISR_Start_Addr(15 downto 4);
541
  signal ISR_Addr_Offset     : std_logic_vector(3 downto 0) := x"0";
542
 
543
  constant INT_VECTOR_0      : std_logic_vector(3 downto 0) := x"0";
544
  constant INT_VECTOR_1      : std_logic_vector(3 downto 0) := x"2";
545
  constant INT_VECTOR_2      : std_logic_vector(3 downto 0) := x"4";
546
  constant INT_VECTOR_3      : std_logic_vector(3 downto 0) := x"6";
547
  constant INT_VECTOR_4      : std_logic_vector(3 downto 0) := x"8";
548
  constant INT_VECTOR_5      : std_logic_vector(3 downto 0) := x"A";
549
  constant INT_VECTOR_6      : std_logic_vector(3 downto 0) := x"C";
550
  constant INT_VECTOR_7      : std_logic_vector(3 downto 0) := x"E";
551
 
552 255 jshamlet
  signal IDX_Offset_SX       : std_logic := '0';
553
 
554 252 jshamlet
  signal IDX_Offset          : ADDRESS_TYPE := x"0000";
555
 
556 255 jshamlet
  signal IDX_Sel_l           : std_logic_vector(2 downto 0) := "000";
557
  signal IDX_Sel_h           : std_logic_vector(2 downto 0) := "000";
558
 
559 252 jshamlet
  signal IDX_Reg_l           : integer := 0;
560
  signal IDX_Reg_h           : integer := 0;
561
 
562
  signal IDX_NoOffset_Calc   : ADDRESS_TYPE := x"0000";
563
  signal IDX_Offset_Calc     : ADDRESS_TYPE := x"0000";
564
 
565 169 jshamlet
begin
566
 
567 224 jshamlet
-------------------------------------------------------------------------------
568
-- Reset & uSec Tick
569
-------------------------------------------------------------------------------
570 185 jshamlet
 
571 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
572
  begin
573
    if( PLL_Locked = '0' )then
574
      Reset_q                <= Reset_Level;
575
      Reset                  <= Reset_Level;
576
    elsif( rising_edge(Clock) )then
577
      Reset_q                <= not Reset_Level;
578
      Reset                  <= Reset_q;
579
    end if;
580
  end process;
581
 
582
  uSec_Tick_proc: process( Clock, Reset )
583
  begin
584
    if( Reset = Reset_Level )then
585
      uSec_Cntr              <= USEC_DLY;
586
      uSec_Tick              <= '0';
587
    elsif( rising_edge( Clock ) )then
588
      uSec_Cntr              <= uSec_Cntr - 1;
589
      if( or_reduce(uSec_Cntr) = '0' )then
590
        uSec_Cntr            <= USEC_DLY;
591
      end if;
592
      uSec_Tick              <= nor_reduce(uSec_Cntr);
593
    end if;
594
  end process;
595
 
596
  Open8_Bus.Clock            <= Clock;
597
  Open8_Bus.Reset            <= Reset;
598
  Open8_Bus.uSec_Tick        <= uSec_Tick;
599
 
600 169 jshamlet
-------------------------------------------------------------------------------
601 182 jshamlet
-- Address bus selection/generation logic
602 169 jshamlet
-------------------------------------------------------------------------------
603
 
604 254 jshamlet
  -- Address selection logic based on current CPU state. This is combinatorial,
605
  --  as adding pipeline registration would add a clock cycle to every instr,
606
  --  without really adding the Fmax to compensate.
607
  Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
608 255 jshamlet
                         IDX_Offset_Calc, ISR_Addr_Offset, Stack_Ptr,
609
                         Program_Ctr )
610 254 jshamlet
  begin
611
    case( CPU_State )is
612
 
613
      when LDA_C2 | STA_C2 =>
614
        Open8_Bus.Address    <= Operand2 & Operand1;
615
 
616
      when LDX_C1 | STX_C1 =>
617
        Open8_Bus.Address    <= IDX_NoOffset_Calc;
618
 
619
      when LDO_C2 | STO_C2 =>
620
        Open8_Bus.Address    <= IDX_Offset_Calc;
621
 
622
      when ISR_C1 | ISR_C2 =>
623
        Open8_Bus.Address    <= ISR_Addr_Base & ISR_Addr_Offset;
624
 
625 255 jshamlet
      when PSH_C1 | POP_C1 |
626
           ISR_C3 | JSR_C1 | JSR_C2 |
627
           RTS_C1 | RTS_C2 | RTS_C3 =>
628 254 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
629
 
630
      when others =>
631
        Open8_Bus.Address    <= Program_Ctr;
632
 
633
    end case;
634
  end process;
635
 
636 252 jshamlet
  -- The original model treated the offset to LDO/STO as a signed value
637
  --  allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't
638
  --  always helpful, so the generic allows the CPU to use unsigned math
639
  --  for the offsets. This makes the range 0 to +255 instead.
640 253 jshamlet
 
641 255 jshamlet
  IDX_Offset_SX <= '0' when Unsigned_Index_Offsets else Operand1(7);
642 252 jshamlet
 
643 255 jshamlet
  IDX_Offset(15 downto 8)    <= (others => IDX_Offset_SX);
644 252 jshamlet
  IDX_Offset(7 downto 0)     <= Operand1;
645
 
646
  -- Enable_Auto_Increment uses the LSB to determine whether or not to
647
  --  do the auto-increment, so we need to lock the LSB for each operand
648
  --  if it is enabled. This forces [ODD:EVEN] pairing.
649
 
650 255 jshamlet
  IDX_Sel_l <= (SubOp(2 downto 1) & '0') when Enable_Auto_Increment else
651
               SubOp;
652 252 jshamlet
 
653 255 jshamlet
  IDX_Sel_h <= (SubOp(2 downto 1) & '1') when Enable_Auto_Increment else
654
               SubOp_p1;
655 252 jshamlet
 
656 255 jshamlet
  IDX_Reg_l <= conv_integer(IDX_Sel_l);
657
  IDX_Reg_h <= conv_integer(IDX_Sel_h);
658
 
659 252 jshamlet
  -- Pipeline registers for the indexed and indexed with offset addresses.
660
  Idx_Addr_Calc_proc: process( Clock, Reset )
661 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
662
  begin
663 252 jshamlet
    if( Reset = Reset_Level )then
664
      IDX_NoOffset_Calc      <= x"0000";
665
      IDX_Offset_Calc        <= x"0000";
666
    elsif( rising_edge(Clock))then
667
      IDX_NoOffset_Calc      <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l));
668
      IDX_Offset_Calc        <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) +
669
                                IDX_Offset;
670 182 jshamlet
    end if;
671 252 jshamlet
  end process;
672 182 jshamlet
 
673
-------------------------------------------------------------------------------
674
-- Combinatorial portion of CPU finite state machine
675
-- State Logic / Instruction Decoding & Execution
676
-------------------------------------------------------------------------------
677
 
678 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
679 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
680
    variable Reg             : integer range 0 to 7 := 0;
681
  begin
682 169 jshamlet
    CPU_Next_State           <= CPU_State;
683
    Cache_Ctrl               <= CACHE_IDLE;
684
    --
685 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
686
    PC_Ctrl.Offset           <= PC_IDLE;
687 182 jshamlet
    --
688 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
689
    ALU_Ctrl.Reg             <= ACCUM;
690
    --
691
    SP_Ctrl.Oper             <= SP_IDLE;
692
    --
693
    DP_Ctrl.Src              <= DATA_RD_MEM;
694
    DP_Ctrl.Reg              <= ACCUM;
695
    --
696
    INT_Ctrl.Mask_Set        <= '0';
697
    INT_Ctrl.Soft_Ints       <= x"00";
698
    INT_Ctrl.Incr_ISR        <= '0';
699
    Ack_D                    <= '0';
700 225 jshamlet
    --
701 182 jshamlet
    Reg                     := conv_integer(SubOp);
702 225 jshamlet
    --
703
    CPU_Halt_Ack             <= '0';
704 169 jshamlet
 
705
    case CPU_State is
706
-------------------------------------------------------------------------------
707
-- Initial Instruction fetch & decode
708
-------------------------------------------------------------------------------
709 187 jshamlet
      when IPF_C0 =>
710
        CPU_Next_State       <= IPF_C1;
711 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
712 169 jshamlet
 
713 187 jshamlet
      when IPF_C1 =>
714
        CPU_Next_State       <= IPF_C2;
715 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
716 169 jshamlet
 
717 187 jshamlet
      when IPF_C2 =>
718
        CPU_Next_State       <= IDC_C0;
719 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
720 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
721 169 jshamlet
 
722 187 jshamlet
      when IDC_C0 =>
723
        CPU_Next_State       <= IDC_C0;
724 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
725
 
726
        case Opcode is
727
          when OP_PSH =>
728
            CPU_Next_State   <= PSH_C1;
729
            Cache_Ctrl       <= CACHE_PREFETCH;
730 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
731 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
732
            DP_Ctrl.Reg      <= SubOp;
733
 
734
          when OP_POP =>
735
            CPU_Next_State   <= POP_C1;
736
            Cache_Ctrl       <= CACHE_PREFETCH;
737 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
738 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
739
 
740
          when OP_BR0 | OP_BR1 =>
741
            CPU_Next_State   <= BRN_C1;
742
            Cache_Ctrl       <= CACHE_OPER1;
743 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
744 169 jshamlet
 
745
          when OP_DBNZ =>
746
            CPU_Next_State   <= DBNZ_C1;
747
            Cache_Ctrl       <= CACHE_OPER1;
748 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
749 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
750
            ALU_Ctrl.Reg     <= SubOp;
751
 
752
          when OP_INT =>
753 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
754 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
755
            --  Also, unlike CPU_Halt, the INT instruction is actually being
756
            --  executed, so go ahead and increment the program counter before
757
            --  pausing so the CPU restarts on the next instruction.
758 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
759 187 jshamlet
              CPU_Next_State <= WAI_Cx;
760 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
761
            end if;
762
 
763
          when OP_STK =>
764
            case SubOp is
765
              when SOP_RSP  =>
766 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
767 181 jshamlet
                if( not Allow_Stack_Address_Move )then
768 187 jshamlet
                  -- The default behavior for this instruction is to simply
769
                  --  repoint the SP to the HDL default
770 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
771 181 jshamlet
                end if;
772 187 jshamlet
                if( Allow_Stack_Address_Move and
773 270 jshamlet
                    Flags(STACK_XFER_FLAG) = '1' )then
774 187 jshamlet
                  -- If RSP is set to allow SP moves, and the specified flag
775
                  --  is true, then signal the stack pointer logic to load
776
                  --  from R1:R0
777 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
778 181 jshamlet
                end if;
779 187 jshamlet
                if( Allow_Stack_Address_Move and
780 270 jshamlet
                    Flags(STACK_XFER_FLAG) = '0')then
781 187 jshamlet
                  -- If RSP is set to allow SP moves, and the specified flag
782
                  --  is false, then signal the ALU to copy the stack pointer
783
                  --  to R1:R0
784 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
785 181 jshamlet
                end if;
786 169 jshamlet
 
787
              when SOP_RTS | SOP_RTI =>
788 185 jshamlet
                CPU_Next_State    <= RTS_C1;
789 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
790 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
791 169 jshamlet
 
792
              when SOP_BRK  =>
793
                if( BRK_Implements_WAI )then
794 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
795
                  --  increment the PC similar to an ISR flow.
796
                  CPU_Next_State  <= WAI_Cx;
797 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
798 187 jshamlet
                else
799
                -- If Break is implemented normally, back the PC up by
800 260 jshamlet
                --  2 and return through IPF_C0 in order to execute a 3
801 187 jshamlet
                --  clock cycle delay
802
                  CPU_Next_State  <= BRK_C1;
803
                  PC_Ctrl.Offset  <= PC_REV2;
804 169 jshamlet
                end if;
805
 
806
              when SOP_JMP  =>
807 185 jshamlet
                CPU_Next_State    <= JMP_C1;
808
                Cache_Ctrl        <= CACHE_OPER1;
809 169 jshamlet
 
810
              when SOP_SMSK =>
811 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
812 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
813
 
814
              when SOP_GMSK =>
815 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
816
                ALU_Ctrl.Oper     <= ALU_GMSK;
817 169 jshamlet
 
818
              when SOP_JSR =>
819 269 jshamlet
                CPU_Next_State    <= JSR_C1;
820 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
821 269 jshamlet
                DP_Ctrl.Src       <= DATA_WR_PC_H;
822 169 jshamlet
 
823
              when others => null;
824
            end case;
825
 
826
          when OP_MUL =>
827
            CPU_Next_State   <= MUL_C1;
828 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
829
            --  to the ALU writing the result to registers. As a result, this
830
            --  state needs to idle the ALU initially, and back the PC up by 1
831
            -- We can get away with only 1 extra clock by pre-fetching the
832
            --  next instruction, though.
833 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
834 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
835 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
836
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
837
            --  now, but hold off on the ALU command until the next state.
838 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
839
            ALU_Ctrl.Reg     <= SubOp;
840
 
841
          when OP_UPP =>
842
            CPU_Next_State   <= UPP_C1;
843
            Cache_Ctrl       <= CACHE_PREFETCH;
844 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
845 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
846
            ALU_Ctrl.Reg     <= SubOp;
847
 
848
          when OP_LDA =>
849
            CPU_Next_State   <= LDA_C1;
850
            Cache_Ctrl       <= CACHE_OPER1;
851
 
852
          when OP_LDI =>
853
            CPU_Next_State   <= LDI_C1;
854
            Cache_Ctrl       <= CACHE_OPER1;
855 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
856 169 jshamlet
 
857
          when OP_LDO =>
858
            CPU_Next_State   <= LDO_C1;
859
            Cache_Ctrl       <= CACHE_OPER1;
860 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
861 169 jshamlet
 
862
          when OP_LDX =>
863
            CPU_Next_State   <= LDX_C1;
864 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
865 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
866 169 jshamlet
 
867
          when OP_STA =>
868
            CPU_Next_State   <= STA_C1;
869
            Cache_Ctrl       <= CACHE_OPER1;
870
 
871
          when OP_STO =>
872
            CPU_Next_State   <= STO_C1;
873
            Cache_Ctrl       <= CACHE_OPER1;
874 252 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
875 169 jshamlet
 
876
          when OP_STX =>
877
            CPU_Next_State   <= STX_C1;
878
            Cache_Ctrl       <= CACHE_PREFETCH;
879 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
880 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
881
            DP_Ctrl.Reg      <= ACCUM;
882
 
883 244 jshamlet
          when OP_STP =>
884
            PC_Ctrl.Offset   <= PC_NEXT;
885
            if( Supervisor_Mode )then
886
              if( SubOp /= PSR_I )then
887
                ALU_Ctrl.Oper  <= Opcode;
888
                ALU_Ctrl.Reg   <= SubOp;
889
              end if;
890
            else
891
              ALU_Ctrl.Oper  <= Opcode;
892
              ALU_Ctrl.Reg   <= SubOp;
893
            end if;
894
 
895 169 jshamlet
          when others =>
896 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
897 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
898
            ALU_Ctrl.Reg     <= SubOp;
899
 
900
        end case;
901
 
902 186 jshamlet
        if( Int_Req = '1' )then
903
          CPU_Next_State     <= ISR_C1;
904 187 jshamlet
        end if;
905
 
906
        if( CPU_Halt_Req = '1' )then
907
          CPU_Next_State     <= WAH_Cx;
908
        end if;
909
 
910
        -- If either of these override conditions are true, the decoder needs
911
        --  to undo everything it just setup, since even "single-cycle"
912
        --  instructions will be executed again upon return.
913
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
914
          -- In either case, we want to skip loading the cache, as the cache
915
          --  will be invalid by the time we get back.
916 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
917 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
918
          -- compensating for the pipeline registers.
919 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
920
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
921 187 jshamlet
          --  operation due to the current instruction.
922 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
923
          SP_Ctrl.Oper       <= SP_IDLE;
924 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
925
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
926 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
927 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
928
          --  executed again when normal processing resumes, so axe their
929
          --  requests for now.
930
          INT_Ctrl.Mask_Set       <= '0';
931
          INT_Ctrl.Soft_Ints(Reg) <= '0';
932 186 jshamlet
        end if;
933
 
934 169 jshamlet
-------------------------------------------------------------------------------
935 270 jshamlet
-- Program Control (BRx, BNx, DBNZ, JMP )
936 169 jshamlet
-------------------------------------------------------------------------------
937
 
938
      when BRN_C1 =>
939 187 jshamlet
        CPU_Next_State       <= IDC_C0;
940 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
941 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
942 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
943 187 jshamlet
          CPU_Next_State     <= IPF_C0;
944 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
945
          PC_Ctrl.Offset     <= Operand1;
946
        end if;
947
 
948
      when DBNZ_C1 =>
949 187 jshamlet
        CPU_Next_State       <= IDC_C0;
950 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
951 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
952
        if( Flags(PSR_Z) = '0' )then
953 187 jshamlet
          CPU_Next_State     <= IPF_C0;
954 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
955
          PC_Ctrl.Offset     <= Operand1;
956
        end if;
957
 
958
      when JMP_C1 =>
959
        CPU_Next_State       <= JMP_C2;
960
        Cache_Ctrl           <= CACHE_OPER2;
961
 
962
      when JMP_C2 =>
963 187 jshamlet
        CPU_Next_State       <= IPF_C0;
964 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
965
 
966
-------------------------------------------------------------------------------
967
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
968
-------------------------------------------------------------------------------
969
 
970
      when LDA_C1 =>
971
        CPU_Next_State       <= LDA_C2;
972
        Cache_Ctrl           <= CACHE_OPER2;
973
 
974
      when LDA_C2 =>
975
        CPU_Next_State       <= LDA_C3;
976
 
977
      when LDA_C3 =>
978
        CPU_Next_State       <= LDA_C4;
979 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
980 169 jshamlet
 
981
      when LDA_C4 =>
982
        CPU_Next_State       <= LDI_C1;
983
        Cache_Ctrl           <= CACHE_OPER1;
984 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
985 169 jshamlet
 
986
      when LDI_C1 =>
987 187 jshamlet
        CPU_Next_State       <= IDC_C0;
988 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
989 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
990 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
991
        ALU_Ctrl.Reg         <= SubOp;
992
 
993
      when LDO_C1 =>
994 252 jshamlet
        CPU_Next_State       <= LDO_C2;
995
 
996
      when LDO_C2 =>
997 181 jshamlet
        CPU_Next_State       <= LDX_C2;
998 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
999 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1000
          ALU_Ctrl.Oper      <= ALU_UPP;
1001
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
1002 169 jshamlet
        end if;
1003
 
1004
      when LDX_C1 =>
1005
        CPU_Next_State       <= LDX_C2;
1006 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1007
          ALU_Ctrl.Oper      <= ALU_UPP;
1008
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
1009 181 jshamlet
        end if;
1010 169 jshamlet
 
1011
      when LDX_C2 =>
1012
        CPU_Next_State       <= LDX_C3;
1013 263 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1014
          ALU_Ctrl.Oper      <= ALU_UPP2;
1015
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '1';
1016
        end if;
1017 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1018 181 jshamlet
 
1019
      when LDX_C3 =>
1020
        CPU_Next_State       <= LDX_C4;
1021 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
1022 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1023 169 jshamlet
 
1024 181 jshamlet
      when LDX_C4 =>
1025 187 jshamlet
        CPU_Next_State       <= IDC_C0;
1026 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
1027 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1028 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
1029 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
1030
 
1031
-------------------------------------------------------------------------------
1032
-- Data Storage - Store to memory (STA, STO, STX)
1033
-------------------------------------------------------------------------------
1034
      when STA_C1 =>
1035
        CPU_Next_State       <= STA_C2;
1036
        Cache_Ctrl           <= CACHE_OPER2;
1037
        DP_Ctrl.Src          <= DATA_WR_REG;
1038
        DP_Ctrl.Reg          <= SubOp;
1039
 
1040
      when STA_C2 =>
1041
        CPU_Next_State       <= STA_C3;
1042 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1043 169 jshamlet
 
1044
      when STA_C3 =>
1045 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1046 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
1047 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1048 169 jshamlet
 
1049
      when STO_C1 =>
1050 252 jshamlet
        CPU_Next_State       <= STO_C2;
1051 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
1052 252 jshamlet
        DP_Ctrl.Src          <= DATA_WR_REG;
1053
        DP_Ctrl.Reg          <= ACCUM;
1054
 
1055
      when STO_C2 =>
1056
        CPU_Next_State       <= IPF_C1;
1057 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1058 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1059 252 jshamlet
          CPU_Next_State     <= STO_C3;
1060 182 jshamlet
          ALU_Ctrl.Oper      <= ALU_UPP;
1061
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
1062 169 jshamlet
        end if;
1063
 
1064 252 jshamlet
      when STO_C3 =>
1065
        CPU_Next_State       <= IPF_C2;
1066 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1067 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
1068
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
1069
 
1070
      when STX_C1 =>
1071 187 jshamlet
        CPU_Next_State       <= IPF_C1;
1072 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1073 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
1074
          CPU_Next_State     <= STX_C2;
1075
          ALU_Ctrl.Oper      <= ALU_UPP;
1076
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
1077 169 jshamlet
        end if;
1078
 
1079
      when STX_C2 =>
1080 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1081 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1082 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
1083
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
1084
 
1085
-------------------------------------------------------------------------------
1086
-- Multi-Cycle Math Operations (UPP, MUL)
1087
-------------------------------------------------------------------------------
1088
 
1089
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
1090 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
1091
      --  need to tell the ALU to store the results to R1:R0 here. Note that
1092
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
1093 169 jshamlet
      when MUL_C1 =>
1094 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1095 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1096 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
1097
 
1098
      when UPP_C1 =>
1099 187 jshamlet
        CPU_Next_State       <= IPF_C2;
1100 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1101 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
1102
        ALU_Ctrl.Reg         <= SubOp_p1;
1103
 
1104
-------------------------------------------------------------------------------
1105
-- Basic Stack Manipulation (PSH, POP, RSP)
1106
-------------------------------------------------------------------------------
1107
      when PSH_C1 =>
1108 187 jshamlet
        CPU_Next_State       <= IPF_C1;
1109 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
1110
 
1111
      when POP_C1 =>
1112
        CPU_Next_State       <= POP_C2;
1113
 
1114
      when POP_C2 =>
1115
        CPU_Next_State       <= POP_C3;
1116 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1117 169 jshamlet
 
1118
      when POP_C3 =>
1119
        CPU_Next_State       <= POP_C4;
1120
        Cache_Ctrl           <= CACHE_OPER1;
1121 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1122 169 jshamlet
 
1123
      when POP_C4 =>
1124 187 jshamlet
        CPU_Next_State       <= IDC_C0;
1125 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
1126 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1127 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
1128
        ALU_Ctrl.Reg         <= SubOp;
1129 172 jshamlet
 
1130 169 jshamlet
-------------------------------------------------------------------------------
1131
-- Subroutines & Interrupts (RTS, JSR)
1132
-------------------------------------------------------------------------------
1133 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
1134 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
1135 186 jshamlet
        if( Int_Req = '1' )then
1136
          CPU_Next_State     <= ISR_C1;
1137 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
1138
          --  instruction, compensating for the pipeline registers.
1139 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
1140
          DP_Ctrl.Src        <= DATA_RD_MEM;
1141
        end if;
1142 169 jshamlet
 
1143 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
1144 225 jshamlet
        CPU_Halt_Ack         <= '1';
1145 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
1146
        if( CPU_Halt_Req = '0' )then
1147
          CPU_Next_State     <= IPF_C0;
1148
          DP_Ctrl.Src        <= DATA_RD_MEM;
1149
        end if;
1150
 
1151
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
1152
        CPU_Next_State       <= IPF_C0;
1153
 
1154 169 jshamlet
      when ISR_C1 =>
1155
        CPU_Next_State       <= ISR_C2;
1156
        INT_Ctrl.Incr_ISR    <= '1';
1157
 
1158
      when ISR_C2 =>
1159
        CPU_Next_State       <= ISR_C3;
1160
        DP_Ctrl.Src          <= DATA_WR_FLAG;
1161
 
1162
      when ISR_C3 =>
1163
        CPU_Next_State       <= JSR_C1;
1164
        Cache_Ctrl           <= CACHE_OPER1;
1165 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
1166 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
1167 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
1168 269 jshamlet
        DP_Ctrl.Src          <= DATA_WR_PC_H;
1169 169 jshamlet
        Ack_D                <= '1';
1170
 
1171
      when JSR_C1 =>
1172
        CPU_Next_State       <= JSR_C2;
1173
        Cache_Ctrl           <= CACHE_OPER2;
1174
        SP_Ctrl.Oper         <= SP_PUSH;
1175 269 jshamlet
        DP_Ctrl.Src          <= DATA_WR_PC_L;
1176 169 jshamlet
 
1177
      when JSR_C2 =>
1178 187 jshamlet
        CPU_Next_State       <= IPF_C0;
1179 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
1180 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
1181 169 jshamlet
 
1182
      when RTS_C1 =>
1183
        CPU_Next_State       <= RTS_C2;
1184
        SP_Ctrl.Oper         <= SP_POP;
1185
 
1186
      when RTS_C2 =>
1187
        CPU_Next_State       <= RTS_C3;
1188
        -- if this is an RTI, then we need to POP the flags
1189
        if( SubOp = SOP_RTI )then
1190
          SP_Ctrl.Oper       <= SP_POP;
1191
        end if;
1192
 
1193
      when RTS_C3 =>
1194
        CPU_Next_State       <= RTS_C4;
1195
        Cache_Ctrl           <= CACHE_OPER1;
1196
 
1197
      when RTS_C4 =>
1198
        CPU_Next_State       <= RTS_C5;
1199
        Cache_Ctrl           <= CACHE_OPER2;
1200
 
1201
      when RTS_C5 =>
1202 187 jshamlet
        CPU_Next_State       <= IPF_C0;
1203 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
1204 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
1205 169 jshamlet
        if( SubOp = SOP_RTI )then
1206
          CPU_Next_State     <= RTI_C6;
1207
          Cache_Ctrl         <= CACHE_OPER1;
1208 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
1209
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
1210 169 jshamlet
        end if;
1211
 
1212
      when RTI_C6 =>
1213 187 jshamlet
        CPU_Next_State       <= IPF_C1;
1214 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1215 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
1216
 
1217
      when others =>
1218
        null;
1219
    end case;
1220
 
1221
  end process;
1222
 
1223
-------------------------------------------------------------------------------
1224
-- Registered portion of CPU finite state machine
1225
-------------------------------------------------------------------------------
1226 182 jshamlet
 
1227 169 jshamlet
  CPU_Regs: process( Reset, Clock )
1228
    variable Offset_SX       : ADDRESS_TYPE;
1229 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
1230 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
1231
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
1232
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
1233
  begin
1234
    if( Reset = Reset_Level )then
1235 187 jshamlet
      CPU_State              <= IPF_C0;
1236 260 jshamlet
 
1237
      CPU_Halt_Req           <= '0';
1238
      Halt_Ack               <= '0';
1239
 
1240 169 jshamlet
      Opcode                 <= OP_INC;
1241
      SubOp                  <= ACCUM;
1242
      SubOp_p1               <= ACCUM;
1243
      Operand1               <= x"00";
1244
      Operand2               <= x"00";
1245
      Instr_Prefetch         <= '0';
1246
      Prefetch               <= x"00";
1247
 
1248 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1249
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1250
      Open8_Bus.Rd_En        <= '1';
1251 169 jshamlet
 
1252
      Program_Ctr            <= Program_Start_Addr;
1253
      Stack_Ptr              <= Stack_Start_Addr;
1254
 
1255
      Ack_Q                  <= '0';
1256
      Ack_Q1                 <= '0';
1257
      Int_Ack                <= '0';
1258
 
1259
      Int_Req                <= '0';
1260
      Pending                <= x"00";
1261
      Wait_for_FSM           <= '0';
1262 210 jshamlet
      Wait_for_ISR           <= '0';
1263 245 jshamlet
      Set_Mask               <= '0';
1264 169 jshamlet
      if( Enable_NMI )then
1265
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
1266
      else
1267
        Int_Mask             <= Default_Interrupt_Mask;
1268
      end if;
1269 254 jshamlet
      ISR_Addr_Offset        <= INT_VECTOR_0;
1270 169 jshamlet
 
1271
      for i in 0 to 7 loop
1272 188 jshamlet
        Regfile(i)           <= x"00";
1273 169 jshamlet
      end loop;
1274
      Flags                  <= x"00";
1275 248 jshamlet
      if( Supervisor_Mode )then
1276 244 jshamlet
        Flags(PSR_I)         <= '1';
1277
      end if;
1278 169 jshamlet
 
1279 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
1280 188 jshamlet
 
1281 169 jshamlet
    elsif( rising_edge(Clock) )then
1282 187 jshamlet
 
1283 260 jshamlet
      CPU_State              <= CPU_Next_State;
1284
 
1285
-- Register the halt request and acknowledge lines
1286
 
1287 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
1288
      Halt_Ack               <= CPU_Halt_Ack;
1289 187 jshamlet
 
1290 169 jshamlet
-------------------------------------------------------------------------------
1291
-- Instruction/Operand caching for pipelined memory access
1292
-------------------------------------------------------------------------------
1293 260 jshamlet
 
1294
      -- To avoid putting too much load on the (usually massive) wire-OR'd bus,
1295
      --  the CPU loads Rd_Data into one of four registers - instruction,
1296
      --  operand 1 or 2, or the instruction prefetch registers. The first is
1297
      --  used to decode an instruction when the prefetch isn't valid, while
1298
      --  the two operand registers are used to hold any additional argument
1299
      --  for multi-byte instructions. Because of the memory pipelining, some
1300
      --  longer instructions can cache the next instruction as part of their
1301
      --  execution in a prefetch register, allowing the CPU to skip loading
1302
      --  it again later. Unfortunate, because instructions aren't all the same
1303
      --  length, it is not feasible to cache their operands without adding a
1304
      --  second partial decode stage that would obviate any savings.
1305
 
1306 169 jshamlet
      case Cache_Ctrl is
1307
        when CACHE_INSTR =>
1308
          Opcode             <= Rd_Data(7 downto 3);
1309
          SubOp              <= Rd_Data(2 downto 0);
1310
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
1311
          if( Instr_Prefetch = '1' )then
1312
            Opcode           <= Prefetch(7 downto 3);
1313
            SubOp            <= Prefetch(2 downto 0);
1314
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
1315
            Instr_Prefetch   <= '0';
1316
          end if;
1317
 
1318
        when CACHE_OPER1 =>
1319
          Operand1           <= Rd_Data;
1320
 
1321
        when CACHE_OPER2 =>
1322
          Operand2           <= Rd_Data;
1323
 
1324
        when CACHE_PREFETCH =>
1325
          Prefetch           <= Rd_Data;
1326
          Instr_Prefetch     <= '1';
1327
 
1328
        when CACHE_IDLE =>
1329
          null;
1330
      end case;
1331
 
1332
-------------------------------------------------------------------------------
1333
-- Program Counter
1334
-------------------------------------------------------------------------------
1335 260 jshamlet
 
1336
      -- The program counter is a bit unusual in that it always subtracts two
1337
      --  from itself plus the signed offset. This is because of the way the
1338
      --  assembler works when computing branches. Thus, to "IDLE" the counter,
1339
      --  the offset is set to 2, while "NEXT" sets the offset to 3. Depending
1340
      --  on how an instruction interacts with memory, or is pipelined,  the
1341
      --  offset can vary from -1 to 3
1342
 
1343 169 jshamlet
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1344
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1345
 
1346
      case PC_Ctrl.Oper is
1347
        when PC_INCR =>
1348
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1349
 
1350
        when PC_LOAD =>
1351 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1352 169 jshamlet
 
1353
        when others =>
1354
          null;
1355
      end case;
1356
 
1357
-------------------------------------------------------------------------------
1358
-- (Write) Data Path
1359
-------------------------------------------------------------------------------
1360 260 jshamlet
 
1361
      -- Note that this code handles both the Rd_En and Wr_En signals. These
1362
      --  were separated to make downstream logic simpler (As opposed to the
1363
      --  more classic RD_WRn and ADDR_STROBE scheme) It is also true to the
1364
      --  original core, which also had separate read and write enable outputs
1365
 
1366
      Open8_Bus.Wr_En        <= '0';
1367
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1368
      Open8_Bus.Rd_En        <= '0';
1369
 
1370 169 jshamlet
      case DP_Ctrl.Src is
1371
        when DATA_BUS_IDLE =>
1372
          null;
1373
 
1374
        when DATA_RD_MEM =>
1375 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1376 169 jshamlet
 
1377
        when DATA_WR_REG =>
1378 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1379
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1380 169 jshamlet
 
1381
        when DATA_WR_FLAG =>
1382 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1383
          Open8_Bus.Wr_Data  <= Flags;
1384 169 jshamlet
 
1385 269 jshamlet
        when DATA_WR_PC_L =>
1386 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1387 269 jshamlet
          Open8_Bus.Wr_Data  <= Program_Ctr(7 downto 0);
1388
 
1389
        when DATA_WR_PC_H =>
1390
          Open8_Bus.Wr_En    <= '1';
1391 223 jshamlet
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1392 169 jshamlet
 
1393
        when others =>
1394
          null;
1395
      end case;
1396
 
1397
-------------------------------------------------------------------------------
1398
-- Stack Pointer
1399
-------------------------------------------------------------------------------
1400
      case SP_Ctrl.Oper is
1401
        when SP_IDLE =>
1402
          null;
1403
 
1404 181 jshamlet
        when SP_CLR =>
1405 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1406
 
1407 181 jshamlet
        when SP_SET =>
1408 245 jshamlet
          if( Supervisor_Mode )then
1409
            if( Flags(PSR_I) = '1' )then
1410
              Stack_Ptr      <= Regfile(1) & Regfile(0);
1411
            end if;
1412
          else
1413
            Stack_Ptr        <= Regfile(1) & Regfile(0);
1414
          end if;
1415 181 jshamlet
 
1416 169 jshamlet
        when SP_POP  =>
1417
          Stack_Ptr          <= Stack_Ptr + 1;
1418
 
1419
        when SP_PUSH =>
1420
          Stack_Ptr          <= Stack_Ptr - 1;
1421
 
1422
        when others =>
1423
          null;
1424
 
1425
      end case;
1426
 
1427
-------------------------------------------------------------------------------
1428
-- Interrupt Controller
1429
-------------------------------------------------------------------------------
1430 245 jshamlet
 
1431
      -- If Supervisor_Mode is set, restrict the SMSK instruction such that it
1432
      --  requires the I bit to be set.
1433
      if( Supervisor_Mode )then
1434
        Set_Mask             <= INT_Ctrl.Mask_Set and Flags(PSR_I);
1435
      else
1436
        Set_Mask             <= INT_Ctrl.Mask_Set;
1437
      end if;
1438
 
1439 169 jshamlet
      -- The interrupt control mask is always sourced out of R0
1440 245 jshamlet
      if( Set_Mask = '1' )then
1441 169 jshamlet
        if( Enable_NMI )then
1442
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1443
        else
1444
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1445
        end if;
1446
      end if;
1447
 
1448
      -- Combine external and internal interrupts, and mask the OR of the two
1449
      --  with the mask. Record any incoming interrupts to the pending buffer
1450
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1451
                                Int_Mask;
1452 172 jshamlet
 
1453 169 jshamlet
      Pending                <= i_Ints or Pending;
1454
 
1455 260 jshamlet
      -- If Sequential_Interrupts is set true, Wait_for_ISR should follow the
1456
      --  I bit, preventing a new interrupt from starting until the I bit is
1457
      --  cleared.
1458 210 jshamlet
      if( Sequential_Interrupts )then
1459
        Wait_for_ISR         <= Flags(PSR_I);
1460
      else
1461
        Wait_for_ISR         <= '0';
1462
      end if;
1463
 
1464
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1465 169 jshamlet
        if(    Pending(0) = '1' )then
1466 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_0;
1467 169 jshamlet
          Pending(0)         <= '0';
1468
        elsif( Pending(1) = '1' )then
1469 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_1;
1470 169 jshamlet
          Pending(1)         <= '0';
1471
        elsif( Pending(2) = '1' )then
1472 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_2;
1473 169 jshamlet
          Pending(2)         <= '0';
1474
        elsif( Pending(3) = '1' )then
1475 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_3;
1476 169 jshamlet
          Pending(3)         <= '0';
1477
        elsif( Pending(4) = '1' )then
1478 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_4;
1479 169 jshamlet
          Pending(4)         <= '0';
1480
        elsif( Pending(5) = '1' )then
1481 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_5;
1482 169 jshamlet
          Pending(5)         <= '0';
1483
        elsif( Pending(6) = '1' )then
1484 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_6;
1485 169 jshamlet
          Pending(6)         <= '0';
1486
        elsif( Pending(7) = '1' )then
1487 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_7;
1488 169 jshamlet
          Pending(7)         <= '0';
1489
        end if;
1490 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1491 169 jshamlet
      end if;
1492
 
1493
      -- Reset the Wait_for_FSM flag on Int_Ack
1494
      Ack_Q                  <= Ack_D;
1495
      Ack_Q1                 <= Ack_Q;
1496
      Int_Ack                <= Ack_Q1;
1497
      if( Int_Ack = '1' )then
1498
        Wait_for_FSM         <= '0';
1499
      end if;
1500
 
1501
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1502
 
1503
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1504
      --  lower half of the address.
1505
      if( INT_Ctrl.Incr_ISR = '1' )then
1506 254 jshamlet
        ISR_Addr_Offset             <= ISR_Addr_Offset + 1;
1507 169 jshamlet
      end if;
1508
 
1509
-------------------------------------------------------------------------------
1510
-- ALU (Arithmetic / Logic Unit)
1511
-------------------------------------------------------------------------------
1512 260 jshamlet
 
1513
      -- The ALU code is responsible for (and should be the only code altering)
1514
      --  the register file. Most of the "instructions" directly map to opcodes
1515
      --  but a few are for internal use only, such as operations involving the
1516 263 jshamlet
      --  stack pointer or interrupt mask.
1517 260 jshamlet
 
1518 169 jshamlet
      Index                  := conv_integer(ALU_Ctrl.Reg);
1519
      Sum                    := (others => '0');
1520
      Temp                   := (others => '0');
1521
 
1522
      case ALU_Ctrl.Oper is
1523
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1524
          Sum                := ("0" & x"01") +
1525
                                ("0" & Regfile(Index));
1526 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1527
          Flags(PSR_C)       <= Sum(8);
1528 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1529 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1530
 
1531
        when ALU_UPP => -- Rn = Rn + 1
1532
          Sum                := ("0" & x"01") +
1533
                                ("0" & Regfile(Index));
1534 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1535 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1536
 
1537
        when ALU_UPP2 => -- Rn = Rn + C
1538 263 jshamlet
          Sum                := (x"00" & Flags(PSR_C)) +
1539
                                ("0" & Regfile(Index));
1540 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1541 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1542
 
1543
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1544
          Sum                := ("0" & Regfile(0)) +
1545
                                ("0" & Regfile(Index)) +
1546 185 jshamlet
                                Flags(PSR_C);
1547
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1548
          Flags(PSR_C)       <= Sum(8);
1549
          Flags(PSR_N)       <= Sum(7);
1550 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1551
 
1552
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1553
          Temp               := "0" & Regfile(Index);
1554 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1555
          Flags(PSR_N)       <= Temp(7);
1556 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1557
 
1558
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1559
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1560 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1561
          Flags(PSR_N)       <= Temp(7);
1562 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1563
 
1564
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1565
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1566 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1567
          Flags(PSR_N)       <= Temp(7);
1568 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1569
 
1570
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1571
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1572 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1573
          Flags(PSR_N)       <= Temp(7);
1574 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1575
 
1576 290 jshamlet
        when ALU_ROL => -- Varies based on config
1577
          if( Rotate_Ignores_Carry )then
1578
            -- Rn = Rn<<1 : Flags N,Z
1579
            Temp(7 downto 0) := Regfile(Index)(6 downto 0) & Regfile(Index)(7);
1580
          else
1581
            -- Rn = Rn<<1,C : Flags N,C,Z
1582
            Temp             := Regfile(Index) & Flags(PSR_C);
1583
            Flags(PSR_C)     <= Temp(8);
1584
          end if;
1585 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1586
          Flags(PSR_N)       <= Temp(7);
1587 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1588
 
1589 290 jshamlet
        when ALU_ROR => -- Varies based on config
1590
          if( Rotate_Ignores_Carry )then
1591
            -- Rn = Rn>>1 : Flags N,Z
1592
            Temp(7 downto 0) := Regfile(Index)(0) & Regfile(Index)(7 downto 1);
1593
          else
1594
            -- Rn = C,Rn>>1 : Flags N,C,Z
1595
            Temp             := Regfile(Index)(0) & Flags(PSR_C) &
1596 169 jshamlet
                                Regfile(Index)(7 downto 1);
1597 290 jshamlet
            Flags(PSR_C)     <= Temp(8);
1598
          end if;
1599 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1600
          Flags(PSR_N)       <= Temp(7);
1601 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1602
 
1603
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1604
          Sum                := ("0" & Regfile(Index)) +
1605
                                ("0" & x"FF");
1606 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1607
          Flags(PSR_C)       <= Sum(8);
1608
          Flags(PSR_N)       <= Sum(7);
1609 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1610
 
1611
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1612 298 jshamlet
          Sum                := ("0" & Regfile(0)) -
1613
                                ("0" & Regfile(Index)) -
1614 185 jshamlet
                                Flags(PSR_C);
1615
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1616
          Flags(PSR_C)       <= Sum(8);
1617
          Flags(PSR_N)       <= Sum(7);
1618 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1619
 
1620
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1621
          Sum                := ("0" & Regfile(0)) +
1622
                                ("0" & Regfile(Index));
1623 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1624 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1625 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1626
          Flags(PSR_N)       <= Sum(7);
1627 169 jshamlet
 
1628
        when ALU_STP => -- Sets bit(n) in the Flags register
1629
          Flags(Index)       <= '1';
1630
 
1631
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1632 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1633
          Flags(PSR_N)       <= Regfile(0)(7);
1634 169 jshamlet
 
1635
        when ALU_CLP => -- Clears bit(n) in the Flags register
1636
          Flags(Index)       <= '0';
1637
 
1638
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1639
          Temp               := "0" & Regfile(0);
1640 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1641
          Flags(PSR_N)       <= Temp(7);
1642 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1643
 
1644
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1645
          Sum                := ("0" & Regfile(0)) +
1646
                                ("1" & (not Regfile(Index))) +
1647
                                '1';
1648 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1649
          Flags(PSR_C)       <= Sum(8);
1650
          Flags(PSR_N)       <= Sum(7);
1651 169 jshamlet
 
1652
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1653
          Regfile(0)         <= Mult(7 downto 0);
1654
          Regfile(1)         <= Mult(15 downto 8);
1655 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1656 169 jshamlet
 
1657
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1658 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1659
          Flags(PSR_N)       <= Operand1(7);
1660
          Regfile(Index)     <= Operand1;
1661 169 jshamlet
 
1662
        when ALU_POP => -- Rn <= Data
1663 185 jshamlet
          Regfile(Index)     <= Operand1;
1664 169 jshamlet
 
1665
        when ALU_RFLG =>
1666 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1667
          if( not RTI_Ignores_GP_Flags )then
1668
            Flags(7 downto 4)<= Operand1(7 downto 4);
1669
          end if;
1670 169 jshamlet
 
1671 185 jshamlet
        when ALU_RSP =>
1672 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1673
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1674
 
1675 185 jshamlet
        when ALU_GMSK =>
1676
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1677
          Regfile(0)         <= Int_Mask;
1678
 
1679 169 jshamlet
        when others =>
1680
          null;
1681
      end case;
1682
 
1683 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1684 188 jshamlet
 
1685 169 jshamlet
    end if;
1686
  end process;
1687
 
1688 182 jshamlet
-------------------------------------------------------------------------------
1689
-- Multiplier Logic
1690
--
1691
-- We need to infer a hardware multipler, so we create a special clocked
1692
--  process with no reset or clock enable
1693
-------------------------------------------------------------------------------
1694
 
1695
  Multiplier_proc: process( Clock )
1696
  begin
1697
    if( rising_edge(Clock) )then
1698
      Mult                   <= Regfile(0) *
1699 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1700
    end if;
1701
  end process;
1702
 
1703
end architecture;

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