OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_de0_nano_adc_if.vhd] - Blame information for rev 332

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 315 jshamlet
-- Copyright (c)2023 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL units : o8_de0_nano_adc_if
25
-- Description: Stitches together all of the components needed to supply data
26
--               from the DE0 nano's on-board ADC. Provides an interrupt output
27
--               when the 8th (last) input is written to the buffer.
28
--
29
-- Register Map:
30
-- Offset  Bitfield Description                        Read/Write
31
--   0x00  AAAAAAAA AFE 0, Channel 0, Lower Byte          RO
32
--   0x01  AAAAAAAA AFE 0, Channel 0, Upper Byte          RO
33
--   0x02  AAAAAAAA AFE 0, Channel 1, Lower Byte          RO
34
--   0x03  AAAAAAAA AFE 0, Channel 1, Upper Byte          RO
35
--   0x04  AAAAAAAA AFE 0, Channel 2, Lower Byte          RO
36
--   0x05  AAAAAAAA AFE 0, Channel 2, Upper Byte          RO
37
--   0x06  AAAAAAAA AFE 0, Channel 3, Lower Byte          RO
38
--   0x07  AAAAAAAA AFE 0, Channel 3, Upper Byte          RO
39
--   0x08  AAAAAAAA AFE 0, Channel 4, Lower Byte          RO
40
--   0x09  AAAAAAAA AFE 0, Channel 4, Upper Byte          RO
41
--   0x0A  AAAAAAAA AFE 0, Channel 5, Lower Byte          RO
42
--   0x0B  AAAAAAAA AFE 0, Channel 5, Upper Byte          RO
43
--   0x0C  AAAAAAAA AFE 0, Channel 6, Lower Byte          RO
44
--   0x0D  AAAAAAAA AFE 0, Channel 6, Upper Byte          RO
45
--   0x0E  AAAAAAAA AFE 0, Channel 7, Lower Byte          RO
46
--   0x0F  AAAAAAAA AFE 0, Channel 7, Upper Byte          RO
47
--
48
-- Revision History
49
-- Author          Date     Change
50
------------------ -------- ---------------------------------------------------
51
-- Seth Henry      05/18/23 Initial Upload
52
 
53
library ieee;
54
use ieee.std_logic_1164.all;
55
use ieee.std_logic_unsigned.all;
56
 
57
library work;
58
  use work.open8_pkg.all;
59
  use work.open8_cfg.all;
60
 
61
entity o8_de0_nano_adc_if is
62
generic(
63
  Address                    : ADDRESS_TYPE
64
);
65
port(
66
  -- Bus IF Interface
67
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
68
  Rd_Data                    : out DATA_TYPE;
69
  Interrupt                  : out std_logic;
70
  -- ADC IF
71
  ADC_SDO                    : in  std_logic;
72
  ADC_SDI                    : out std_logic;
73
  ADC_SCLK                   : out std_logic;
74
  ADC_CSn                    : out std_logic
75
);
76
end entity;
77
 
78
architecture behave of o8_de0_nano_adc_if is
79
 
80
  -- Bus Interface Signals
81
 
82
  alias Clock                is Open8_Bus.Clock;
83
  alias Reset                is Open8_Bus.Reset;
84
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
85
 
86
  signal RAW_Channel         : std_logic_vector(2 downto 0)  := (others => '0');
87
  signal RAW_Data            : std_logic_vector(15 downto 0) := (others => '0');
88
  signal RAW_Valid           : std_logic := '0';
89
 
90
  signal AVG_Busy            : std_logic := '0';
91
 
92
  signal AVG_Channel         : std_logic_vector(2 downto 0)  := (others => '0');
93
  signal AVG_Data            : std_logic_vector(15 downto 0) := (others => '0');
94
  signal AVG_Valid           : std_logic := '0';
95
 
96
  alias  Buf_Wr_Ptr          is AVG_Channel;
97
  alias  Buf_Wr_Data         is AVG_Data;
98
  alias  Buf_Wr_Valid        is AVG_Valid;
99
 
100
  alias  Buf_Rd_Ptr          is Open8_Bus.Address(3 downto 0);
101
  signal Buf_Rd_Data         : std_logic_vector(7 downto 0) := (others => '0');
102
 
103
  constant LAST_ADDR         : std_logic_vector(2 downto 0)  := (others => '1');
104
  signal Last_Sample         : std_logic := '0';
105
 
106
  constant User_Addr         : std_logic_vector(15 downto 4) :=
107
                               Address(15 downto 4);
108
  alias Comp_Addr            is Open8_Bus.Address(15 downto 4);
109
 
110
  signal Addr_Match          : std_logic := '0';
111
  signal Rd_En               : std_logic := '0';
112
 
113
begin
114
 
115
-------------------------------------------------------------------------------
116
-- ADC0 - Interface
117
-------------------------------------------------------------------------------
118
 
119
  U_ADC0 : entity work.adc12s022
120
  generic map(
121
    Clock_Frequency          => Clock_Frequency,
122
    Reset_Level              => Reset_Level
123
  )
124
  port map(
125
    Clock                    => Clock,
126
    Reset                    => Reset,
127
    --
128
    RAW_Channel              => RAW_Channel,
129
    RAW_Data                 => RAW_Data,
130
    RAW_Valid                => RAW_Valid,
131
    --
132
    Busy_In                  => AVG_Busy,
133
    --
134
    SDO                      => ADC_SDO,
135
    SDI                      => ADC_SDI,
136
    SCLK                     => ADC_SCLK,
137
    CSn                      => ADC_CSn
138
  );
139
 
140
  U_AVG0 : entity work.mavg_8ch_16b_64d
141
  generic map(
142
    Reset_Level              => Reset_Level
143
  )
144
  port map(
145
    Clock                    => Clock,
146
    Reset                    => Reset,
147
    --
148
    RAW_Channel              => RAW_Channel,
149
    RAW_Data                 => RAW_Data,
150
    RAW_Valid                => RAW_Valid,
151
    --
152
    Busy_Out                 => AVG_Busy,
153
    --
154
    AVG_Channel              => AVG_Channel,
155
    AVG_Out                  => AVG_Data,
156
    AVG_Valid                => AVG_Valid,
157
    --
158
    Busy_In                  => '0'
159
  );
160
 
161
-------------------------------------------------------------------------------
162
-- Buffer Storage
163
-------------------------------------------------------------------------------
164
 
165
  U_DBUF : entity work.adc_buffer
166
  port map(
167
    clock                    => Clock,
168
    data                     => Buf_Wr_Data,
169
    rdaddress                => Buf_Rd_Ptr,
170
    wraddress                => Buf_Wr_Ptr,
171
    wren                     => Buf_Wr_Valid,
172
    q                        => Buf_Rd_Data
173
  );
174
 
175
  U_DMON : entity work.adc_monitor
176
  port map(
177
    address                  => Buf_Wr_Ptr,
178
    clock                    => Clock,
179
    data                     => Buf_Wr_Data,
180
    wren                     => Buf_Wr_Valid,
181
    q                        => open
182
  );
183
 
184
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
185
                                '0';
186
 
187
  Last_Sample                <= Buf_Wr_Valid when Buf_Wr_Ptr = LAST_ADDR else '0';
188
 
189
  RAM_proc: process( Reset, Clock )
190
  begin
191
    if( Reset = Reset_Level )then
192
      Interrupt              <= '0';
193
      Rd_En                  <= '0';
194
      Rd_Data                <= OPEN8_NULLBUS;
195
    elsif( rising_edge(Clock) )then
196
      Interrupt              <= Last_Sample;
197
      Rd_En                  <= Addr_Match;
198
      Rd_Data                <= OPEN8_NULLBUS;
199
      if( Rd_En = '1' )then
200
        Rd_Data              <= Buf_Rd_Data;
201
      end if;
202
    end if;
203
  end process;
204
 
205
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.