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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_elapsed_usec.vhd] - Blame information for rev 245

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1 231 jshamlet
-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_elapsed_usec
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-- Description:  Provides an 24-bit microsecond resolution counter for
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--            :   measuring events
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--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x00  AAAAAAAA Req Interval Byte 0                   (RW)
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--   0x01  AAAAAAAA Req Interval Byte 1                   (RW)
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--   0x02  AAAAAAAA Req Interval Byte 2                   (RW)
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--   0x03  BA------ Control/Status Register               (RW)
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--                   A: Reset (1)                         (WR)
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--                   B: Start (1) / Stop (0)
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--
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-- Notes      :  Writing to 0x0 - 0x02 will latch the current value
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--            :  Writing a 1 to bit A of 0x03 will cause an
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--                immediate timer reset. This bit is a one-shot.
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/20/20 Design Start
45 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
46 231 jshamlet
 
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library ieee;
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use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_elapsed_usec is
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generic(
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
62 244 jshamlet
  Write_Qual                 : in  std_logic := '1';
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  Rd_Data                    : out DATA_TYPE
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);
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end entity;
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architecture behave of o8_elapsed_usec is
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  alias Clock                is Open8_Bus.Clock;
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  alias Reset                is Open8_Bus.Reset;
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  alias uSec_Tick            is Open8_Bus.uSec_Tick;
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  constant User_Addr         : std_logic_vector(15 downto 2) :=
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                                Address(15 downto 2);
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
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  signal Addr_Match          : std_logic := '0';
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78 244 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
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  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
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  signal Wr_En_d             : std_logic := '0';
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  signal Wr_En_q             : std_logic := '0';
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  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
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  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal Rd_En_d             : std_logic := '0';
85 231 jshamlet
  signal Rd_En_q             : std_logic := '0';
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  signal Shadow_Time         : std_logic_vector(23 downto 0) := x"000000";
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  alias  Shadow_Time_B0      is Shadow_Time( 7 downto  0);
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  alias  Shadow_Time_B1      is Shadow_Time(15 downto  8);
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  alias  Shadow_Time_B2      is Shadow_Time(23 downto 16);
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  signal Update_Shadow       : std_logic := '0';
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  signal Timer_Reset         : std_logic := '0';
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  signal Timer_En_Req        : std_logic := '0';
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  signal Timer_Enable        : std_logic := '0';
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  signal Timer_Cnt           : std_logic_vector(23 downto 0) := x"000000";
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
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  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Reg_Sel_q              <= "00";
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      Wr_En_q                <= '0';
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      Wr_Data_q              <= x"00";
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      Rd_En_q                <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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      Update_Shadow          <= '0';
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      Timer_Reset            <= '0';
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      Timer_En_Req           <= '0';
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    elsif( rising_edge( Clock ) )then
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      Reg_Sel_q              <= Reg_Sel_d;
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      Wr_En_q                <= Wr_En_d;
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      Wr_Data_q              <= Wr_Data_d;
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      Update_Shadow          <= '0';
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      Timer_Reset            <= '0';
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      if( Wr_En_q = '1' and Write_Qual = '1' )then
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        case( Reg_Sel_q )is
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          when "00" =>
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            Update_Shadow    <= '1';
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          when "01" =>
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            Update_Shadow    <= '1';
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          when "10" =>
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            Update_Shadow    <= '1';
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          when "11" =>
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            Timer_Reset      <= Wr_Data_q(6);
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            Timer_En_Req     <= Wr_Data_q(7);
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          when others => null;
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        end case;
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      end if;
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      Rd_Data                <= OPEN8_NULLBUS;
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      Rd_En_q                <= Rd_En_d;
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      if( Rd_En_q = '1' )then
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        case( Reg_Sel_q )is
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          when "00" =>
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            Rd_Data          <= Shadow_Time_B0;
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          when "01" =>
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            Rd_Data          <= Shadow_Time_B1;
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          when "10" =>
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            Rd_Data          <= Shadow_Time_B2;
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          when "11" =>
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            Rd_Data          <= Timer_En_Req & "0000000";
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          when others => null;
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        end case;
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      end if;
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    end if;
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  end process;
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  Timer_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Shadow_Time            <= x"000000";
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      Timer_Cnt              <= x"000000";
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    elsif( rising_edge(Clock) )then
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      if( Timer_Reset = '1' )then
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        Timer_Cnt              <= x"000000";
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      elsif( Timer_Enable = '1' )then
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        Timer_Cnt            <= Timer_Cnt + uSec_Tick;
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      end if;
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      if( uSec_Tick = '1' )then
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        Timer_Enable         <= Timer_En_Req;
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      end if;
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      if( Update_Shadow = '1' )then
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        Shadow_Time          <= Timer_Cnt;
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      end if;
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    end if;
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  end process;
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end architecture;

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