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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Blame information for rev 216

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1 212 jshamlet
-- Copyright (c)2011, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_epoch_timer
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-- Description:  Provides a 24-bit, 4uS resolution elapsed timer with
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--            :   alarm and interrupt for the Open8 CPU.
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--
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-- Notes      :  Requires an externally provided uSec tick input - one clock
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--            :   per microsecond.
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--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x0   AAAAAAAA B0 of Buffered Setpoint (W) or Current Setpoint(R)
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--   0x1   AAAAAAAA B1 of Buffered Setpoint (W) or Current Setpoint(R)
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--   0x2   AAAAAAAA B2 of Buffered Setpoint (W) or Current Setpoint(R)
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--   0x3   BA------ Status of buffer/alarm (1 = pending, 0 = current)
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--                  A = Pending status (R)
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--                  B = Alarm status (R)
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--                  Note that any write will update the internal set point
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--                  and clear the alarm
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--   0x4   AAAAAAAA B0 of Current Epoch Time(RO)
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--   0x5   AAAAAAAA B1 of Current Epoch Time(RO)
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--   0x6   AAAAAAAA B2 of Current Epoch Time(RO)
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--                  Note that any write to 0x04,0x05, or 0x06 will copy the
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--                  current epoch time to a readable output buffer
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--   0x7   -------- Epoch Time Latch/Clear Control Register
47 213 jshamlet
--                  Any write to 0x7 will clear/reset the all timer regs
48 212 jshamlet
--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      07/28/11 Design Start
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-- Seth Henry      12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
54 213 jshamlet
-- Seth Henry      04/10/20 Overhauled the register interface of the timer to
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--                           make the interface more sensible to software.
56 212 jshamlet
 
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library ieee;
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use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_epoch_timer is
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generic(
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  Reset_Level           : std_logic;
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  Address               : ADDRESS_TYPE
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);
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port(
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  Clock                 : in  std_logic;
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  Reset                 : in  std_logic;
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  uSec_Tick             : in  std_logic;
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  --
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  Bus_Address           : in  ADDRESS_TYPE;
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  Wr_Enable             : in  std_logic;
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  Wr_Data               : in  DATA_TYPE;
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  Rd_Enable             : in  std_logic;
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  Rd_Data               : out DATA_TYPE;
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  Interrupt             : out std_logic
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);
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end entity;
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architecture behave of o8_epoch_timer is
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  constant User_Addr         : std_logic_vector(15 downto 3)
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                               := Address(15 downto 3);
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  alias  Comp_Addr           is Bus_Address(15 downto 3);
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  signal Addr_Match          : std_logic := '0';
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  alias  Reg_Addr            is Bus_Address(2 downto 0);
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  signal Reg_Addr_q          : std_logic_vector(2 downto 0) := (others => '0');
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  signal Wr_En               : std_logic := '0';
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  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal Rd_En               : std_logic := '0';
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  signal setpt_buffer        : std_logic_vector(23 downto 0) := (others => '0');
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  alias  setpt_buffer_b0     is setpt_buffer(7 downto 0);
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  alias  setpt_buffer_b1     is setpt_buffer(15 downto 8);
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  alias  setpt_buffer_b2     is setpt_buffer(23 downto 16);
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  signal epoch_buffer        : std_logic_vector(23 downto 0) := (others => '0');
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  alias  epoch_buffer_b0     is epoch_buffer(7 downto 0);
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  alias  epoch_buffer_b1     is epoch_buffer(15 downto 8);
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  alias  epoch_buffer_b2     is epoch_buffer(23 downto 16);
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  signal buffer_pending      : std_logic := '0';
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  signal buffer_update       : std_logic := '0';
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  signal timer_clear         : std_logic := '0';
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  signal epoch_tmr           : std_logic_vector(25 downto 0) := (others => '0');
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  alias  epoch_tmrcmp        is epoch_tmr(25 downto 2);
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  signal epoch_setpt         : std_logic_vector(25 downto 0) := (others => '0');
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  alias  epoch_setpt_b0      is epoch_setpt(7 downto 0);
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  alias  epoch_setpt_b1      is epoch_setpt(15 downto 8);
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  alias  epoch_setpt_b2      is epoch_setpt(23 downto 16);
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  alias  epoch_setpt_u       is epoch_setpt(25 downto 2);
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  alias  epoch_setpt_l       is epoch_setpt(1 downto 0);
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  signal epoch_alarm         : std_logic := '0';
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  signal epoch_alarm_q       : std_logic := '0';
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Wr_Data_q              <= (others => '0');
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      Reg_Addr_q             <= (others => '0');
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      Wr_En                  <= '0';
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      Rd_En                  <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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      setpt_buffer           <= (others => '0');
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      epoch_buffer           <= (others => '0');
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      buffer_pending         <= '0';
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      buffer_update          <= '0';
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      timer_clear            <= '0';
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    elsif( rising_edge( Clock ) )then
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      Reg_Addr_q             <= Reg_Addr;
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      Wr_En                  <= Addr_Match and Wr_Enable;
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      Wr_Data_q              <= Wr_Data;
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      buffer_update          <= '0';
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      timer_clear            <= '0';
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      if( Wr_En = '1' )then
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        case( Reg_Addr_q )is
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          when "000" =>
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            setpt_buffer_b0  <= Wr_Data_q;
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            buffer_pending   <= '1';
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          when "001" =>
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            setpt_buffer_b1  <= Wr_Data_q;
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            buffer_pending   <= '1';
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          when "010" =>
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            setpt_buffer_b2  <= Wr_Data_q;
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            buffer_pending   <= '1';
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          when "011" =>
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            buffer_update    <= '1';
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            buffer_pending   <= '0';
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          when "100" | "101" | "110" =>
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            epoch_buffer     <= epoch_tmrcmp;
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          when "111" =>
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            timer_clear      <= '1';
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          when others => null;
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        end case;
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      end if;
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      Rd_Data                <= OPEN8_NULLBUS;
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      Rd_En                  <= Addr_Match and Rd_Enable;
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      if( Rd_En = '1' )then
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        case( Reg_Addr_q )is
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          when "000" =>
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            Rd_Data          <= epoch_setpt_b0;
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          when "001" =>
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            Rd_Data          <= epoch_setpt_b1;
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          when "010" =>
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            Rd_Data          <= epoch_setpt_b2;
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          when "011" =>
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            Rd_Data          <= epoch_alarm & buffer_pending & "000000";
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          when "100" =>
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            Rd_Data          <= epoch_buffer_b0(7 downto 0);
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          when "101" =>
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            Rd_Data          <= epoch_buffer_b1(15 downto 8);
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          when "110" =>
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            Rd_Data          <= epoch_buffer_b2(23 downto 16);
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          when others => null;
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        end case;
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      end if;
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    end if;
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  end process;
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  timer_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      epoch_setpt            <= (others => '0');
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      epoch_tmr              <= (others => '0');
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      epoch_alarm            <= '0';
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      epoch_alarm_q          <= '0';
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      Interrupt              <= '0';
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    elsif( rising_edge(Clock) )then
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      epoch_tmr              <= epoch_tmr + uSec_Tick;
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      -- Set and hold on alarm condition
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      if( epoch_tmr > epoch_setpt and epoch_setpt > 0 )then
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        epoch_alarm          <= '1';
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      end if;
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      if( buffer_update = '1' )then
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        epoch_setpt_u        <= setpt_buffer;
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                  -- Force the lower bits of the setpoint to "11" so that the offset is
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              --  reduced to 1uS (reproducing the original behavior). Software should
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                    --  always subtract 4uS (-1) from the desired time to compensate
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        epoch_setpt_l        <= (others => or_reduce(setpt_buffer));
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        epoch_alarm          <= '0';
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      end if;
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      if( timer_clear = '1' )then
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        epoch_setpt          <= (others => '0');
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        epoch_tmr            <= (others => '0');
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        epoch_alarm          <= '0';
230 209 jshamlet
      end if;
231 212 jshamlet
 
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      epoch_alarm_q          <= epoch_alarm;
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      -- Fire on rising edge of epoch_alarm
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      Interrupt              <= epoch_alarm and not epoch_alarm_q;
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236
    end if;
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  end process;
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end architecture;

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