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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer_ii.vhd] - Blame information for rev 300

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1 222 jshamlet
-- Copyright (c)2011, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_epoch_timer_ii
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-- Description:  Provides a 32-bit, 1uS resolution elapsed timer with
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--            :   alarm and interrupt for the Open8 CPU.
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--
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-- Notes      :  Requires an externally provided uSec tick input - one clock
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--            :   per microsecond.
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--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x0   AAAAAAAA B0 of Buffered Setpoint (W) or Current Setpoint(R)
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--   0x1   AAAAAAAA B1 of Buffered Setpoint (W) or Current Setpoint(R)
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--   0x2   AAAAAAAA B2 of Buffered Setpoint (W) or Current Setpoint(R)
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--   0x3   AAAAAAAA B3 of Buffered Setpoint (W) or Current Setpoint(R)
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--   0x4   AAAAAAAA B0 of Buffered Current Epoch Time(RO)
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--   0x5   AAAAAAAA B1 of Buffered Current Epoch Time(RO)
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--   0x6   AAAAAAAA B2 of Buffered Current Epoch Time(RO)
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--   0x7   AAAAAAAA B3 of Buffered Current Epoch Time(RO)
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--                  Note that any write to 0x04,0x05, 0x06, or 0x07 will copy
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--                   the current epoch time to a readable output buffer
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--   0x8   -------- (not used - returns 0x00)
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--   0x9   -------- (not used - returns 0x00)
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--   0xA   -------- (not used - returns 0x00)
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--   0xB   -------- (not used - returns 0x00)
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--   0xC   -------- (not used - returns 0x00)
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--   0xD   -------- (not used - returns 0x00)
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--   0xE   -------- Epoch Time Latch/Clear Control Register
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--                  Any write to 0xE will clear/reset the all timer regs
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--   0xF   BA------ Status of buffer/alarm (1 = pending, 0 = current)
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--                  A = Pending status (R)
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--                  B = Buffer status (R)
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--                  Note that any write will update the internal set point
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--                  and clear the alarm
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/15/20 Created from o8_epoch_timer due to requirement
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--                           change.
62 279 jshamlet
-- Seth Henry      04/16/20 Modified to make use of Open8 bus record
63 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
64 273 jshamlet
-- Seth Henry      11/01/20 Updated comments regarding buffered current time
65 222 jshamlet
 
66
library ieee;
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use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_epoch_timer_ii is
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generic(
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  Write_Qual                 : in  std_logic := '1';
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  Rd_Data                    : out DATA_TYPE;
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  Interrupt                  : out std_logic
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);
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end entity;
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architecture behave of o8_epoch_timer_ii is
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89 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
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  alias Reset                is Open8_Bus.Reset;
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  alias uSec_Tick            is Open8_Bus.uSec_Tick;
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  constant User_Addr         : std_logic_vector(15 downto 4)
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                               := Address(15 downto 4);
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 4);
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  signal Addr_Match          : std_logic := '0';
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  alias  Reg_Sel_d           is Open8_Bus.Address(3 downto 0);
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  signal Reg_Sel_q           : std_logic_vector(3 downto 0) := "0000";
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  signal Wr_En_d             : std_logic := '0';
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  signal Wr_En_q             : std_logic := '0';
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  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
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  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal Rd_En_d             : std_logic := '0';
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  signal Rd_En_q             : std_logic := '0';
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  signal setpt_buffer        : std_logic_vector(31 downto 0) :=
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                                (others => '0');
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  alias  setpt_buffer_b0     is setpt_buffer( 7 downto  0);
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  alias  setpt_buffer_b1     is setpt_buffer(15 downto  8);
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  alias  setpt_buffer_b2     is setpt_buffer(23 downto 16);
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  alias  setpt_buffer_b3     is setpt_buffer(31 downto 24);
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  signal buffer_pending      : std_logic := '0';
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  signal buffer_update       : std_logic := '0';
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  signal epoch_buffer        : std_logic_vector(31 downto 0) :=
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                                (others => '0');
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  alias  epoch_buffer_b0     is epoch_buffer( 7 downto  0);
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  alias  epoch_buffer_b1     is epoch_buffer(15 downto  8);
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  alias  epoch_buffer_b2     is epoch_buffer(23 downto 16);
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  alias  epoch_buffer_b3     is epoch_buffer(31 downto 24);
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  signal capture_epoch       : std_logic := '0';
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  signal timer_clear         : std_logic := '0';
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  signal epoch_tmr           : std_logic_vector(31 downto 0) :=
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                                (others => '0');
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  alias  epoch_tmrcmp        is epoch_tmr(31 downto 2);
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  signal epoch_setpt         : std_logic_vector(31 downto 0) :=
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                                (others => '0');
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  alias  epoch_setpt_b0      is epoch_setpt( 7 downto  0);
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  alias  epoch_setpt_b1      is epoch_setpt(15 downto  8);
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  alias  epoch_setpt_b2      is epoch_setpt(23 downto 16);
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  alias  epoch_setpt_b3      is epoch_setpt(31 downto 24);
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  signal epoch_alarm         : std_logic := '0';
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  signal epoch_alarm_q       : std_logic := '0';
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
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  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Reg_Sel_q              <= "0000";
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      Wr_En_q                <= '0';
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      Wr_Data_q              <= x"00";
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      Rd_En_q                <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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      setpt_buffer           <= (others => '0');
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      buffer_pending         <= '0';
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      buffer_update          <= '0';
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      capture_epoch          <= '0';
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      timer_clear            <= '0';
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    elsif( rising_edge( Clock ) )then
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168 244 jshamlet
      Reg_Sel_q              <= Reg_Sel_d;
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      Wr_En_q                <= Wr_En_d;
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      Wr_Data_q              <= Wr_Data_d;
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      buffer_update          <= '0';
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      timer_clear            <= '0';
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      capture_epoch          <= '0';
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177 244 jshamlet
      if( Wr_En_q = '1' and Write_Qual = '1' )then
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        case( Reg_Sel_q )is
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          when x"0" =>
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            setpt_buffer_b0  <= Wr_Data_q;
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            buffer_pending   <= '1';
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          when x"1" =>
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            setpt_buffer_b1  <= Wr_Data_q;
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            buffer_pending   <= '1';
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          when x"2" =>
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            setpt_buffer_b2  <= Wr_Data_q;
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            buffer_pending   <= '1';
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          when x"3" =>
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            setpt_buffer_b3  <= Wr_Data_q;
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            buffer_pending   <= '1';
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          when x"4" | x"5" | x"6" | x"7" =>
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            capture_epoch    <= '1';
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          when x"E" =>
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            timer_clear      <= '1';
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          when x"F" =>
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            buffer_update    <= '1';
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            buffer_pending   <= '0';
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          when others => null;
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        end case;
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      end if;
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209
      Rd_Data                <= OPEN8_NULLBUS;
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      Rd_En_q                <= Rd_En_d;
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      if( Rd_En_q = '1' )then
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        case( Reg_Sel_q )is
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          when x"0" =>
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            Rd_Data          <= epoch_setpt_b0;
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          when x"1" =>
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            Rd_Data          <= epoch_setpt_b1;
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          when x"2" =>
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            Rd_Data          <= epoch_setpt_b2;
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          when x"3" =>
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            Rd_Data          <= epoch_setpt_b3;
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          when x"4" =>
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            Rd_Data          <= epoch_buffer_b0;
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          when x"5" =>
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            Rd_Data          <= epoch_buffer_b1;
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          when x"6" =>
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            Rd_Data          <= epoch_buffer_b2;
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          when x"7" =>
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            Rd_Data          <= epoch_buffer_b3;
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          when x"F" =>
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            Rd_Data          <= epoch_alarm & buffer_pending & "000000";
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          when others => null;
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        end case;
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      end if;
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    end if;
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  end process;
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237
  timer_proc: process( Clock, Reset )
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  begin
239
    if( Reset = Reset_Level )then
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      epoch_setpt            <= (others => '0');
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      epoch_buffer           <= (others => '0');
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      epoch_tmr              <= (others => '0');
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      epoch_alarm            <= '0';
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      epoch_alarm_q          <= '0';
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      Interrupt              <= '0';
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247
    elsif( rising_edge(Clock) )then
248
 
249
      epoch_tmr              <= epoch_tmr + uSec_Tick;
250
 
251
      if( epoch_tmr > epoch_setpt )then
252
        epoch_alarm          <= or_reduce(epoch_setpt);
253
      end if;
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255
      if( buffer_update = '1' )then
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        epoch_setpt          <= setpt_buffer;
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        epoch_alarm          <= '0';
258
      end if;
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260
      if( timer_clear = '1' )then
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        epoch_setpt          <= (others => '0');
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        epoch_tmr            <= (others => '0');
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        epoch_alarm          <= '0';
264
      end if;
265
 
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      epoch_alarm_q          <= epoch_alarm;
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      Interrupt              <= epoch_alarm and not epoch_alarm_q;
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269
      if( capture_epoch = '1' )then
270
        epoch_buffer         <= epoch_tmr;
271
      end if;
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273
    end if;
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  end process;
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end architecture;

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