OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpin.vhd] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 213 jshamlet
-- Copyright (c)2011, 2019 Jeremy Seth Henry
2 167 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 167 jshamlet
--
24
-- VHDL Units :  o8_gpin
25
-- Description:  Provides a single 8-bit input register
26 189 jshamlet
--
27
-- Note: Cut the path between GPIN and GPIN_q1 for timing analysis
28
--
29
-- Revision History
30
-- Author          Date     Change
31
------------------ -------- ---------------------------------------------------
32
-- Seth Henry      07/28/11 Design Start
33
-- Seth Henry      12/19/19 Renamed to "o8_gpin" to fit "theme"
34
-- Seth Henry      12/20/19 Added metastability registers
35 213 jshamlet
-- Seth Henry      04/10/20 Code Cleanup
36 167 jshamlet
 
37
library ieee;
38
use ieee.std_logic_1164.all;
39
 
40
library work;
41
  use work.open8_pkg.all;
42
 
43
entity o8_gpin is
44
generic(
45 213 jshamlet
  Reset_Level                : std_logic;
46
  Address                    : ADDRESS_TYPE
47 167 jshamlet
);
48
port(
49 213 jshamlet
  Clock                      : in  std_logic;
50
  Reset                      : in  std_logic;
51 167 jshamlet
  --
52 213 jshamlet
  Bus_Address                : in  ADDRESS_TYPE;
53
  Rd_Enable                  : in  std_logic;
54
  Rd_Data                    : out DATA_TYPE;
55 167 jshamlet
  --
56 213 jshamlet
  GPIN                       : in  DATA_TYPE
57 167 jshamlet
);
58
end entity;
59
 
60
architecture behave of o8_gpin is
61
 
62 213 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
63
  alias  Comp_Addr           is Bus_Address(15 downto 0);
64
  signal Addr_Match          : std_logic;
65
  signal Rd_En               : std_logic;
66 191 jshamlet
 
67 213 jshamlet
  signal GPIN_q1             : DATA_TYPE;
68
  signal GPIN_q2             : DATA_TYPE;
69
  signal User_In             : DATA_TYPE;
70 167 jshamlet
 
71
begin
72
 
73 213 jshamlet
  Addr_Match                 <= Rd_Enable when Comp_Addr = User_Addr else '0';
74 167 jshamlet
 
75
  io_reg: process( Clock, Reset )
76
  begin
77
    if( Reset = Reset_Level )then
78 213 jshamlet
      Rd_En                  <= '0';
79
      Rd_Data                <= OPEN8_NULLBUS;
80
      GPIN_q1                <= x"00";
81
      GPIN_q2                <= x"00";
82
      User_In                <= x"00";
83 167 jshamlet
    elsif( rising_edge( Clock ) )then
84 213 jshamlet
      GPIN_q1                <= GPIN;
85
      GPIN_q2                <= GPIN_q1;
86
      User_In                <= GPIN_q2;
87 167 jshamlet
 
88 213 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
89
      Rd_En                  <= Addr_Match;
90 167 jshamlet
      if( Rd_En = '1' )then
91 213 jshamlet
        Rd_Data              <= User_In;
92 167 jshamlet
      end if;
93
    end if;
94
  end process;
95
 
96
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.