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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_gpio.vhd] - Blame information for rev 186

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1 167 jshamlet
-- Copyright (c)2013 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_gpio
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-- Description:  Provides a single 8-bit GPIO register
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_gpio is
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generic(
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  Default_Out           : DATA_TYPE := x"00";
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  Default_En            : DATA_TYPE := x"00";
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  Reset_Level           : std_logic := '1';
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  Input_Only            : boolean := false;
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  Address               : ADDRESS_TYPE
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);
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port(
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  Clock                 : in  std_logic;
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  Reset                 : in  std_logic;
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  --
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  Bus_Address           : in  ADDRESS_TYPE;
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  Wr_Enable             : in  std_logic;
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  Wr_Data               : in  DATA_TYPE;
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  Rd_Enable             : in  std_logic;
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  Rd_Data               : out DATA_TYPE;
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  --
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  GPIO                  : inout DATA_TYPE
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);
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end entity;
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architecture behave of o8_gpio is
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  constant User_Addr    : std_logic_vector(15 downto 2)
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                          := Address(15 downto 2);
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  alias  Comp_Addr      is Bus_Address(15 downto 2);
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  alias  Reg_Addr       is Bus_Address(1 downto 0);
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  signal Reg_Sel        : std_logic_vector(1 downto 0);
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  signal Addr_Match     : std_logic;
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  signal Wr_En          : std_logic;
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  signal Wr_Data_q      : DATA_TYPE;
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  signal Rd_En          : std_logic;
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  signal User_Out       : DATA_TYPE;
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  signal User_En        : DATA_TYPE;
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  signal User_In        : DATA_TYPE;
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begin
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  Addr_Match            <= '1' when Comp_Addr = User_Addr else '0';
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Reg_Sel           <= "00";
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      Rd_En             <= '0';
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      Rd_Data           <= x"00";
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      if( not Input_Only )then
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        Wr_En           <= '0';
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        Wr_Data_q       <= x"00";
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        User_Out        <= Default_Out;
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        User_En         <= Default_En;
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      end if;
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    elsif( rising_edge( Clock ) )then
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      Reg_Sel           <= Reg_Addr;
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      if( not Input_Only )then
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        Wr_En           <= Addr_Match and Wr_Enable;
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        Wr_Data_q       <= Wr_Data;
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        if( Wr_En = '1' )then
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          case( Reg_Sel )is
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            when "00" =>
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              User_Out  <= Wr_Data_q;
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            when "01" =>
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              User_En   <= Wr_Data_q;
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            when others => null;
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          end case;
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        end if;
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      end if;
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      User_In           <= GPIO;
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      Rd_Data           <= (others => '0');
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      Rd_En             <= Addr_Match and Rd_Enable;
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      if( Rd_En = '1' )then
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        if( Input_Only )then
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          Rd_Data       <= User_In;
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        else
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          case( Reg_Sel )is
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            when "00" =>
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              Rd_Data     <= User_Out;
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            when "01" =>
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              Rd_Data     <= User_En;
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            when "10" =>
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              Rd_Data     <= User_In;
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            when others => null;
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          end case;
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        end if;
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      end if;
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    end if;
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  end process;
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Input_Only_is_True: if( Input_Only )generate
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  GPIO                  <= (others => 'Z');
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end generate;
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Input_Only_is_False: if( not Input_Only )generate
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  Output_Ctl_proc: process( User_Out, User_En )
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  begin
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    for i in 0 to 7 loop
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      GPIO(i)           <= 'Z';
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      if( User_En(i) = '1' )then
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        GPIO(i)         <= User_Out(i);
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      end if;
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    end loop;
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  end process;
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end generate;
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end architecture;

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