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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_4b.vhd] - Blame information for rev 221

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1 194 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24 175 jshamlet
-- VHDL Entity: o8_hd44780_4b
25
-- Description: Provides low-level access to a "standard" character LCD using
26
--               the ST/HD44780(U) control ASIC wired in reduced (4-bit) mode.
27
--              All low-level timing of the control signals are handled by this
28
--               module, allowing client firmware to use a simple register
29
--               interface to program the LCD panel.
30
--              Init routine initializes the display and displays a single
31
--               character to demonstrate correct function, then listens for
32
--               user data on its external interface.
33 213 jshamlet
--
34
-- Register Map
35
-- Address  Function
36
-- Offset  Bitfield Description                        Read/Write
37
-- 0x0     AAAAAAAA LCD Register Write                 (Write-only)
38
-- 0x1     AAAAAAAA LCD Data Write                     (Write-only)
39
-- 0x2     AAAAAAAA LCD Contrast                       (Read-Write)
40
-- 0x3     AAAAAAAA LCD Backlight                      (Read-Write)
41
--
42
--------------------------------------------------------------------------------
43
-- LCD Controller
44
--------------------------------------------------------------------------------
45
--
46
-- LCD Instruction Set
47
-- Instruction             RS  RW  D7  D6  D5  D4  D3  D2  D1  D0  Time
48
------------------------------------------------------------------------
49
-- Clear Display         | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
50
-- Return Home           | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
51
-- Entry Mode            | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S |   37uS
52
-- Display Pwr           | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B |   37uS
53
-- Cursor/Display Shift  | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x |   37uS
54
-- Function Set          | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x |   37uS
55
-- Set CGRAM Address     | 0 | 0 | 0 | 1 | A | A | A | A | A | A |   37uS
56
-- Set DDRAM Address     | 0 | 0 | 1 | A | A | A | A | A | A | A |   37uS
57 175 jshamlet
 
58 213 jshamlet
-- Notes:
59
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
60
-- S  = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
61
-- D  = Display On/Off (1 = on, 0 = off)
62
-- C  = Cursor On/Off  (1 = on, 0 = off)
63
-- B  = Cursor Blink   (1 = block cursor, 0 = underline cursor)
64
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
65
-- F  = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
66
-- N  = Number of Lines (0 = 1 lines, 1 = 2 lines)
67
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
68
-- A  = Address (see data sheet for usage)
69
--
70
-- Revision History
71
-- Author          Date     Change
72
------------------ -------- ---------------------------------------------------
73
-- Seth Henry      01/22/13 Design Start
74
-- Seth Henry      04/10/20 Code & comment cleanup
75
 
76 175 jshamlet
library ieee;
77
use ieee.std_logic_1164.all;
78
use ieee.std_logic_unsigned.all;
79
use ieee.std_logic_arith.all;
80
 
81
library work;
82
use work.open8_pkg.all;
83
 
84
entity o8_hd44780_4b is
85
generic(
86 217 jshamlet
  Use_Contrast               : boolean;
87
  Default_Contrast           : std_logic_vector(7 downto 0);
88
  Use_Backlight              : boolean;
89
  Default_Brightness         : std_logic_vector(7 downto 0);
90
  Address                    : ADDRESS_TYPE;
91
  Reset_Level                : std_logic;
92
  Sys_Freq                   : real
93 175 jshamlet
);
94
port(
95 217 jshamlet
  Clock                      : in  std_logic;
96
  Reset                      : in  std_logic;
97 175 jshamlet
  --
98 217 jshamlet
  uSec_Tick                  : in  std_logic;
99 175 jshamlet
  --
100 217 jshamlet
  Bus_Address                : in  ADDRESS_TYPE;
101
  Wr_Enable                  : in  std_logic;
102
  Wr_Data                    : in  DATA_TYPE;
103
  Rd_Enable                  : in  std_logic;
104
  Rd_Data                    : out DATA_TYPE;
105
  Interrupt                  : out std_logic;
106 175 jshamlet
  --
107 217 jshamlet
  LCD_E                      : out std_logic;
108
  LCD_RW                     : out std_logic;
109
  LCD_RS                     : out std_logic;
110
  LCD_D                      : out std_logic_vector(7 downto 4);
111
  LCD_CN                     : out std_logic;
112
  LCD_BL                     : out std_logic
113 175 jshamlet
);
114
end entity;
115
 
116
architecture behave of o8_hd44780_4b is
117
 
118 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 2)
119
                               := Address(15 downto 2);
120
  alias  Comp_Addr           is Bus_Address(15 downto 2);
121
  signal Addr_Match          : std_logic := '0';
122 175 jshamlet
 
123 217 jshamlet
  alias  Reg_Addr             is Bus_Address(1 downto 0);
124
  signal Reg_Addr_q          : std_logic_vector(1 downto 0) := (others => '0');
125 175 jshamlet
 
126 217 jshamlet
  signal Wr_En               : std_logic := '0';
127
  signal Wr_Data_q           : DATA_TYPE := x"00";
128
  signal Rd_En               : std_logic := '0';
129 175 jshamlet
 
130 217 jshamlet
  signal Reg_Valid           : std_logic := '0';
131
  signal Reg_Sel             : std_logic := '0';
132
  signal Reg_Data            : std_logic_vector(7 downto 0) := x"00";
133 175 jshamlet
 
134 217 jshamlet
  signal Tx_Ready            : std_logic := '0';
135 175 jshamlet
 
136 217 jshamlet
  constant LCD_CONFIG1       : std_logic_vector(7 downto 4) := x"3";  -- Init to 4-bit mode
137
  constant LCD_CONFIG2       : std_logic_vector(7 downto 0) := x"28"; -- Set 4-bit, 2-line mode
138
  constant LCD_CONFIG3       : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
139
  constant LCD_CONFIG4       : std_logic_vector(7 downto 0) := x"01"; -- Clear display
140
  constant LCD_CONFIG5       : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
141
  constant LCD_CONFIG6       : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
142
  constant LCD_CONFIG7       : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
143 175 jshamlet
 
144 217 jshamlet
  signal init_count          : std_logic_vector(2 downto 0) := (others => '0');
145 175 jshamlet
 
146 217 jshamlet
  constant INIT_40MS         : integer := 40000;
147
  constant INIT_BITS         : integer := ceil_log2(INIT_40MS);
148
  constant INIT_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
149
                               conv_std_logic_vector(INIT_40MS,INIT_BITS);
150 175 jshamlet
 
151
-- For "long" instructions, such as clear display and return home, we need to wait for more
152
--  than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
153 217 jshamlet
  constant CLDSP_2MS         : integer := 2000;
154
  constant CLDSP_DELAY       : std_logic_vector(INIT_BITS-1 downto 0) :=
155
                               conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
156 175 jshamlet
 
157
 -- For some reason, we are required to wait 80uS before checking the busy flag, despite
158
 --  most instructions completing in 37uS. No clue as to why, but it works
159 217 jshamlet
  constant BUSY_50US         : integer := 50;
160
  constant BUSY_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
161
                               conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
162 175 jshamlet
 
163 217 jshamlet
  signal busy_timer          : std_logic_vector(INIT_BITS-1 downto 0);
164 175 jshamlet
 
165 217 jshamlet
  constant SNH_600NS         : integer := integer(Sys_Freq * 0.000000600);
166
  constant SNH_BITS          : integer := ceil_log2(SNH_600NS);
167
  constant SNH_DELAY         : std_logic_vector(SNH_BITS-1 downto 0) :=
168
                               conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
169 175 jshamlet
 
170 217 jshamlet
  signal io_timer            : std_logic_vector(SNH_BITS - 1 downto 0) :=
171
                               (others => '0');
172 175 jshamlet
 
173
  type IO_STATES is (INIT, PWR_WAIT, INIT_S1, INIT_H1,
174
                     INIT_WAIT, FN_JUMP, IDLE,
175 213 jshamlet
                                                   WR_PREP, WR_SETUP_UB, WR_HOLD_UB, WR_SETUP_LB, WR_HOLD_LB,
176 175 jshamlet
                     BUSY_PREP, BUSY_WAIT,
177
                     ISSUE_INT );
178
 
179 217 jshamlet
  signal io_state            : IO_STATES := INIT;
180 175 jshamlet
 
181 217 jshamlet
  signal LCD_Data            : DATA_TYPE := x"00";
182
  signal LCD_Addr            : std_logic := '0';
183 175 jshamlet
 
184
--------------------------------------------------------------------------------
185 213 jshamlet
-- Backlight & Contrast signals
186 175 jshamlet
--------------------------------------------------------------------------------
187
 
188 217 jshamlet
  signal LCD_Contrast        : DATA_TYPE := x"00";
189
  signal LCD_Bright          : DATA_TYPE := x"00";
190 175 jshamlet
 
191
begin
192
 
193
--------------------------------------------------------------------------------
194
-- Open8 Register interface
195
--------------------------------------------------------------------------------
196
 
197 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
198 175 jshamlet
 
199
  io_reg: process( Clock, Reset )
200
  begin
201
    if( Reset = Reset_Level )then
202 217 jshamlet
      Reg_Addr_q             <= (others => '0');
203
      Wr_Data_q              <= (others => '0');
204
      Wr_En                  <= '0';
205
      Rd_En                  <= '0';
206
      Rd_Data                <= OPEN8_NULLBUS;
207 175 jshamlet
 
208 217 jshamlet
      Reg_Valid              <= '0';
209
      Reg_Sel                <= '0';
210
      Reg_Data               <= x"00";
211 175 jshamlet
 
212 217 jshamlet
      LCD_Contrast           <= Default_Contrast;
213
      LCD_Bright             <= Default_Brightness;
214 175 jshamlet
    elsif( rising_edge( Clock ) )then
215 217 jshamlet
      Reg_Addr_q             <= Reg_Addr;
216 175 jshamlet
 
217 217 jshamlet
      Wr_Data_q              <= Wr_Data;
218
      Wr_En                  <= Addr_Match and Wr_Enable;
219 175 jshamlet
 
220 217 jshamlet
      Reg_Valid              <= '0';
221 175 jshamlet
 
222
      if( Wr_En = '1' )then
223
        case( Reg_Addr_q )is
224
          when "00" | "01" =>
225 217 jshamlet
            Reg_Valid        <= '1';
226
            Reg_Sel          <= Reg_Addr_q(0);
227
            Reg_Data         <= Wr_Data_q;
228 175 jshamlet
          when "10" =>
229 217 jshamlet
            LCD_Contrast     <= Wr_Data_q;
230 175 jshamlet
          when "11" =>
231 217 jshamlet
            LCD_Bright       <= Wr_Data_q;
232 175 jshamlet
          when others => null;
233
        end case;
234
      end if;
235
 
236 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
237
      Rd_En                  <= Addr_Match and Rd_Enable;
238 175 jshamlet
      if( Rd_En = '1' )then
239
        case( Reg_Addr_q )is
240
          when "00" | "01" =>
241 217 jshamlet
            Rd_Data(7)       <= Tx_Ready;
242 175 jshamlet
          when "10" =>
243 217 jshamlet
            Rd_Data          <= LCD_Contrast;
244 175 jshamlet
          when "11" =>
245 217 jshamlet
            Rd_Data          <= LCD_Bright;
246 175 jshamlet
          when others => null;
247
        end case;
248
      end if;
249
    end if;
250
  end process;
251
 
252
--------------------------------------------------------------------------------
253
-- LCD and Register logic
254
--------------------------------------------------------------------------------
255
 
256 217 jshamlet
  LCD_RW                     <= '0'; -- Permanently wire the RW line low
257 175 jshamlet
 
258
  LCD_IO: process( Clock, Reset )
259
  begin
260
    if( Reset = Reset_Level )then
261 217 jshamlet
      io_state               <= INIT;
262
      init_count             <= (others => '0');
263
      io_timer               <= (others => '0');
264
      busy_timer             <= (others => '0');
265
      LCD_Data               <= (others => '0');
266
      LCD_Addr               <= '0';
267
      LCD_E                  <= '0';
268
      LCD_RS                 <= '0';
269
      LCD_D                  <= (others => '0');
270
      Tx_Ready               <= '0';
271
      Interrupt              <= '0';
272 175 jshamlet
    elsif( rising_edge(Clock) )then
273 217 jshamlet
      LCD_E                  <= '0';
274
      LCD_RS                 <= '0';
275
      LCD_D                  <= (others => '0');
276
      Tx_Ready               <= '0';
277
      Interrupt              <= '0';
278
      io_timer               <= io_timer - 1;
279
      busy_timer             <= busy_timer - uSec_Tick;
280 175 jshamlet
      case( io_state )is
281
 
282
        when INIT =>
283 217 jshamlet
          busy_timer         <= INIT_DELAY;
284
          init_count         <= (others => '1');
285
          io_state           <= PWR_WAIT;
286 175 jshamlet
 
287
        -- We wait for at least 40mS before continuing initalization.
288
        when PWR_WAIT =>
289
          if( busy_timer = 0 )then
290 217 jshamlet
            io_timer         <= SNH_DELAY;
291
            io_state         <= INIT_S1;
292 175 jshamlet
          end if;
293
 
294
        -- We write out the first init byte as if we were using an 8-bit
295
        --  data bus, with a single cycle. This is an exception, and the
296
        --  rest of the commands are sent using 2-cycle transfers.
297
        when INIT_S1 =>
298 217 jshamlet
          LCD_D              <= LCD_CONFIG1;
299
          LCD_E              <= '1';
300 175 jshamlet
          if( io_timer = 0 )then
301 217 jshamlet
            io_timer         <= SNH_DELAY;
302
            io_state         <= INIT_H1;
303 175 jshamlet
          end if;
304
 
305
        when INIT_H1 =>
306 217 jshamlet
          LCD_D              <= LCD_CONFIG1;
307 175 jshamlet
          if( io_timer = 0 )then
308 217 jshamlet
            busy_timer       <= BUSY_DELAY;
309
            io_state         <= INIT_WAIT;
310 175 jshamlet
          end if;
311
 
312
        when INIT_WAIT =>
313
          if( busy_timer = 0 )then
314 217 jshamlet
            io_state         <= FN_JUMP;
315 175 jshamlet
          end if;
316
 
317
        when FN_JUMP =>
318 217 jshamlet
          io_state           <= WR_PREP;
319 175 jshamlet
          case( init_count )is
320
            when "000" =>
321 217 jshamlet
              io_state       <= IDLE;
322 175 jshamlet
            when "001" =>
323 217 jshamlet
              LCD_Addr       <= '0';
324
              LCD_Data       <= LCD_CONFIG7; -- Reset the Cursor
325 175 jshamlet
            when "010" =>
326 217 jshamlet
              LCD_Addr       <= '1';         -- Print a "*", and
327
              LCD_Data       <= LCD_CONFIG6; --  set RS to 1
328 175 jshamlet
            when "011" =>
329 217 jshamlet
              LCD_Data       <= LCD_CONFIG5; -- Entry mode
330 175 jshamlet
            when "100" =>
331 217 jshamlet
              LCD_Data       <= LCD_CONFIG4; -- Clear Display
332 175 jshamlet
            when "101" =>
333 217 jshamlet
              LCD_Data       <= LCD_CONFIG3; -- Display control
334 175 jshamlet
            when "110" | "111" =>
335 217 jshamlet
              LCD_Addr       <= '0';
336
              LCD_Data       <= LCD_CONFIG2; -- Function set
337 175 jshamlet
            when others => null;
338
          end case;
339
 
340
        when IDLE =>
341 217 jshamlet
          Tx_Ready           <= '1';
342 175 jshamlet
          if( Reg_Valid = '1' )then
343 217 jshamlet
            LCD_Addr         <= Reg_Sel;
344
            LCD_Data         <= Reg_Data;
345
            io_state         <= WR_PREP;
346 175 jshamlet
          end if;
347
 
348
        when WR_PREP =>
349 217 jshamlet
          io_timer           <= SNH_DELAY;
350
          io_state           <= WR_SETUP_UB;
351 175 jshamlet
 
352
        when WR_SETUP_UB =>
353 217 jshamlet
          LCD_RS             <= LCD_Addr;
354
          LCD_D              <= LCD_Data(7 downto 4);
355
          LCD_E              <= '1';
356 175 jshamlet
          if( io_timer = 0 )then
357 217 jshamlet
            io_timer         <= SNH_DELAY;
358
            io_state         <= WR_HOLD_UB;
359 175 jshamlet
          end if;
360
 
361
        when WR_HOLD_UB =>
362 217 jshamlet
          LCD_RS             <= LCD_Addr;
363
          LCD_D              <= LCD_Data(7 downto 4);
364 175 jshamlet
          if( io_timer = 0 )then
365 217 jshamlet
            LCD_E            <= '0';
366
            io_timer         <= SNH_DELAY;
367
            io_state         <= WR_SETUP_LB;
368 175 jshamlet
          end if;
369
 
370
        when WR_SETUP_LB =>
371 217 jshamlet
          LCD_RS             <= LCD_Addr;
372
          LCD_D              <= LCD_Data(3 downto 0);
373
          LCD_E              <= '1';
374 175 jshamlet
          if( io_timer = 0 )then
375 217 jshamlet
            io_timer         <= SNH_DELAY;
376
            io_state         <= WR_HOLD_LB;
377 175 jshamlet
          end if;
378
 
379
        when WR_HOLD_LB =>
380 217 jshamlet
          LCD_RS             <= LCD_Addr;
381
          LCD_D              <= LCD_Data(3 downto 0);
382 175 jshamlet
          if( io_timer = 0 )then
383 217 jshamlet
            io_state         <= BUSY_WAIT;
384 175 jshamlet
          end if;
385
 
386
        when BUSY_PREP =>
387 217 jshamlet
          busy_timer         <= BUSY_DELAY;
388 175 jshamlet
          if( LCD_Addr = '0' and LCD_Data < 4 )then
389 217 jshamlet
            busy_timer       <= CLDSP_DELAY;
390 175 jshamlet
          end if;
391 217 jshamlet
          io_state           <= BUSY_WAIT;
392 175 jshamlet
 
393
        when BUSY_WAIT =>
394
          if( busy_timer = 0 )then
395 217 jshamlet
            io_state         <= ISSUE_INT;
396 175 jshamlet
            if( init_count > 0 )then
397 217 jshamlet
              init_count     <= init_count - 1;
398
              io_state       <= FN_JUMP;
399 175 jshamlet
            end if;
400
          end if;
401
 
402
        when ISSUE_INT =>
403 217 jshamlet
          Interrupt          <= '1';
404
          io_state           <= IDLE;
405 175 jshamlet
 
406
        when others => null;
407
 
408
      end case;
409
 
410
    end if;
411
  end process;
412
 
413
--------------------------------------------------------------------------------
414
-- Contrast control logic (optional)
415
--------------------------------------------------------------------------------
416
 
417
Contrast_Disabled: if( not Use_Contrast )generate
418
  LCD_CN                <= '0';
419
end generate;
420
 
421
Contrast_Enabled: if( Use_Contrast )generate
422
 
423 217 jshamlet
  U_CN : entity work.vdsm8
424
  generic map(
425
    Reset_Level              => Reset_Level
426
  )
427
  port map(
428
    Clock                    => Clock,
429
    Reset                    => Reset,
430
    DACin                    => LCD_Contrast,
431
    DACout                   => LCD_CN
432
  );
433 175 jshamlet
 
434
end generate;
435
 
436
--------------------------------------------------------------------------------
437
-- Backlight control logic (optional)
438
--------------------------------------------------------------------------------
439
 
440
Backlight_Disabled: if( not Use_Backlight )generate
441
  LCD_BL                <= '0';
442
end generate;
443
 
444
Backlight_Enabled: if( Use_Backlight )generate
445
 
446 217 jshamlet
  U_BL : entity work.vdsm8
447
  generic map(
448
    Reset_Level              => Reset_Level
449
  )
450
  port map(
451
    Clock                    => Clock,
452
    Reset                    => Reset,
453
    DACin                    => LCD_Bright,
454
    DACout                   => LCD_BL
455
  );
456 175 jshamlet
 
457
end generate;
458
 
459
end architecture;

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