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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_4b.vhd] - Blame information for rev 287

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1 194 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24 175 jshamlet
-- VHDL Entity: o8_hd44780_4b
25
-- Description: Provides low-level access to a "standard" character LCD using
26
--               the ST/HD44780(U) control ASIC wired in reduced (4-bit) mode.
27
--              All low-level timing of the control signals are handled by this
28
--               module, allowing client firmware to use a simple register
29
--               interface to program the LCD panel.
30
--              Init routine initializes the display and displays a single
31
--               character to demonstrate correct function, then listens for
32
--               user data on its external interface.
33 213 jshamlet
--
34
-- Register Map
35
-- Address  Function
36
-- Offset  Bitfield Description                        Read/Write
37 262 jshamlet
-- 0x0     AAAAAAAA LCD Register Write                 (Read-Write*)
38
-- 0x1     AAAAAAAA LCD Data Write                     (Read-Write*)
39 213 jshamlet
-- 0x2     AAAAAAAA LCD Contrast                       (Read-Write)
40
-- 0x3     AAAAAAAA LCD Backlight                      (Read-Write)
41
--
42 262 jshamlet
-- Note: Reading 0x0 or 0x1 will report whether the panel is ready or not in the
43
--        MSB (bit 7). 0x00 = NOT READY / 0x80 = READY
44
--
45 213 jshamlet
--------------------------------------------------------------------------------
46
-- LCD Controller
47
--------------------------------------------------------------------------------
48
--
49
-- LCD Instruction Set
50
-- Instruction             RS  RW  D7  D6  D5  D4  D3  D2  D1  D0  Time
51
------------------------------------------------------------------------
52
-- Clear Display         | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
53
-- Return Home           | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
54
-- Entry Mode            | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S |   37uS
55
-- Display Pwr           | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B |   37uS
56
-- Cursor/Display Shift  | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x |   37uS
57
-- Function Set          | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x |   37uS
58
-- Set CGRAM Address     | 0 | 0 | 0 | 1 | A | A | A | A | A | A |   37uS
59
-- Set DDRAM Address     | 0 | 0 | 1 | A | A | A | A | A | A | A |   37uS
60 175 jshamlet
 
61 213 jshamlet
-- Notes:
62
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
63
-- S  = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
64
-- D  = Display On/Off (1 = on, 0 = off)
65
-- C  = Cursor On/Off  (1 = on, 0 = off)
66
-- B  = Cursor Blink   (1 = block cursor, 0 = underline cursor)
67
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
68
-- F  = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
69
-- N  = Number of Lines (0 = 1 lines, 1 = 2 lines)
70
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
71
-- A  = Address (see data sheet for usage)
72
--
73
-- Revision History
74
-- Author          Date     Change
75
------------------ -------- ---------------------------------------------------
76
-- Seth Henry      01/22/13 Design Start
77
-- Seth Henry      04/10/20 Code & comment cleanup
78 224 jshamlet
-- Seth Henry      04/16/20 Modified to use Open8 bus record
79 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
80 213 jshamlet
 
81 175 jshamlet
library ieee;
82
use ieee.std_logic_1164.all;
83
use ieee.std_logic_unsigned.all;
84
use ieee.std_logic_arith.all;
85
 
86
library work;
87
use work.open8_pkg.all;
88
 
89
entity o8_hd44780_4b is
90
generic(
91 217 jshamlet
  Use_Contrast               : boolean;
92
  Default_Contrast           : std_logic_vector(7 downto 0);
93
  Use_Backlight              : boolean;
94
  Default_Brightness         : std_logic_vector(7 downto 0);
95 224 jshamlet
  Clock_Frequency            : real;
96
  Address                    : ADDRESS_TYPE
97 175 jshamlet
);
98
port(
99 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
100 244 jshamlet
  Write_Qual                 : in  std_logic := '1';
101 217 jshamlet
  Rd_Data                    : out DATA_TYPE;
102
  Interrupt                  : out std_logic;
103 175 jshamlet
  --
104 217 jshamlet
  LCD_E                      : out std_logic;
105
  LCD_RW                     : out std_logic;
106
  LCD_RS                     : out std_logic;
107
  LCD_D                      : out std_logic_vector(7 downto 4);
108
  LCD_CN                     : out std_logic;
109
  LCD_BL                     : out std_logic
110 175 jshamlet
);
111
end entity;
112
 
113
architecture behave of o8_hd44780_4b is
114
 
115 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
116
  alias Reset                is Open8_Bus.Reset;
117
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
118
 
119 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 2)
120
                               := Address(15 downto 2);
121 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
122 244 jshamlet
  signal Addr_Match          : std_logic;
123 175 jshamlet
 
124 244 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
125
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
126
  signal Wr_En_d             : std_logic := '0';
127
  signal Wr_En_q             : std_logic := '0';
128
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
129 217 jshamlet
  signal Wr_Data_q           : DATA_TYPE := x"00";
130 244 jshamlet
  signal Rd_En_d             : std_logic := '0';
131
  signal Rd_En_q             : std_logic := '0';
132 175 jshamlet
 
133 217 jshamlet
  signal Reg_Valid           : std_logic := '0';
134
  signal Reg_Sel             : std_logic := '0';
135
  signal Reg_Data            : std_logic_vector(7 downto 0) := x"00";
136 175 jshamlet
 
137 217 jshamlet
  signal Tx_Ready            : std_logic := '0';
138 175 jshamlet
 
139 217 jshamlet
  constant LCD_CONFIG1       : std_logic_vector(7 downto 4) := x"3";  -- Init to 4-bit mode
140
  constant LCD_CONFIG2       : std_logic_vector(7 downto 0) := x"28"; -- Set 4-bit, 2-line mode
141
  constant LCD_CONFIG3       : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
142
  constant LCD_CONFIG4       : std_logic_vector(7 downto 0) := x"01"; -- Clear display
143
  constant LCD_CONFIG5       : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
144
  constant LCD_CONFIG6       : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
145
  constant LCD_CONFIG7       : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
146 175 jshamlet
 
147 217 jshamlet
  signal init_count          : std_logic_vector(2 downto 0) := (others => '0');
148 175 jshamlet
 
149 217 jshamlet
  constant INIT_40MS         : integer := 40000;
150
  constant INIT_BITS         : integer := ceil_log2(INIT_40MS);
151
  constant INIT_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
152
                               conv_std_logic_vector(INIT_40MS,INIT_BITS);
153 175 jshamlet
 
154
-- For "long" instructions, such as clear display and return home, we need to wait for more
155
--  than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
156 217 jshamlet
  constant CLDSP_2MS         : integer := 2000;
157
  constant CLDSP_DELAY       : std_logic_vector(INIT_BITS-1 downto 0) :=
158
                               conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
159 175 jshamlet
 
160
 -- For some reason, we are required to wait 80uS before checking the busy flag, despite
161
 --  most instructions completing in 37uS. No clue as to why, but it works
162 217 jshamlet
  constant BUSY_50US         : integer := 50;
163
  constant BUSY_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
164
                               conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
165 175 jshamlet
 
166 217 jshamlet
  signal busy_timer          : std_logic_vector(INIT_BITS-1 downto 0);
167 175 jshamlet
 
168 224 jshamlet
  constant SNH_600NS         : integer := integer(Clock_Frequency * 0.000000600);
169 217 jshamlet
  constant SNH_BITS          : integer := ceil_log2(SNH_600NS);
170
  constant SNH_DELAY         : std_logic_vector(SNH_BITS-1 downto 0) :=
171
                               conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
172 175 jshamlet
 
173 217 jshamlet
  signal io_timer            : std_logic_vector(SNH_BITS - 1 downto 0) :=
174
                               (others => '0');
175 175 jshamlet
 
176
  type IO_STATES is (INIT, PWR_WAIT, INIT_S1, INIT_H1,
177
                     INIT_WAIT, FN_JUMP, IDLE,
178 213 jshamlet
                                                   WR_PREP, WR_SETUP_UB, WR_HOLD_UB, WR_SETUP_LB, WR_HOLD_LB,
179 175 jshamlet
                     BUSY_PREP, BUSY_WAIT,
180
                     ISSUE_INT );
181
 
182 217 jshamlet
  signal io_state            : IO_STATES := INIT;
183 175 jshamlet
 
184 217 jshamlet
  signal LCD_Data            : DATA_TYPE := x"00";
185
  signal LCD_Addr            : std_logic := '0';
186 175 jshamlet
 
187
--------------------------------------------------------------------------------
188 213 jshamlet
-- Backlight & Contrast signals
189 175 jshamlet
--------------------------------------------------------------------------------
190
 
191 217 jshamlet
  signal LCD_Contrast        : DATA_TYPE := x"00";
192
  signal LCD_Bright          : DATA_TYPE := x"00";
193 175 jshamlet
 
194
begin
195
 
196
--------------------------------------------------------------------------------
197
-- Open8 Register interface
198
--------------------------------------------------------------------------------
199
 
200 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
201 244 jshamlet
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
202
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
203 175 jshamlet
 
204
  io_reg: process( Clock, Reset )
205
  begin
206
    if( Reset = Reset_Level )then
207 244 jshamlet
      Reg_Sel_q              <= "00";
208
      Wr_En_q                <= '0';
209
      Wr_Data_q              <= x"00";
210
      Rd_En_q                <= '0';
211 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
212 175 jshamlet
 
213 217 jshamlet
      Reg_Valid              <= '0';
214
      Reg_Sel                <= '0';
215
      Reg_Data               <= x"00";
216 175 jshamlet
 
217 217 jshamlet
      LCD_Contrast           <= Default_Contrast;
218
      LCD_Bright             <= Default_Brightness;
219 175 jshamlet
    elsif( rising_edge( Clock ) )then
220 244 jshamlet
      Reg_Sel_q              <= Reg_Sel_d;
221 175 jshamlet
 
222 244 jshamlet
      Wr_En_q                <= Wr_En_d;
223
      Wr_Data_q              <= Wr_Data_d;
224 217 jshamlet
      Reg_Valid              <= '0';
225 244 jshamlet
      if( Wr_En_q = '1' )then
226
        case( Reg_Sel_q )is
227 175 jshamlet
          when "00" | "01" =>
228 217 jshamlet
            Reg_Valid        <= '1';
229 244 jshamlet
            Reg_Sel          <= Reg_Sel_q(0);
230 217 jshamlet
            Reg_Data         <= Wr_Data_q;
231 175 jshamlet
          when "10" =>
232 217 jshamlet
            LCD_Contrast     <= Wr_Data_q;
233 175 jshamlet
          when "11" =>
234 217 jshamlet
            LCD_Bright       <= Wr_Data_q;
235 175 jshamlet
          when others => null;
236
        end case;
237
      end if;
238
 
239 244 jshamlet
      Rd_En_q                <= Rd_En_d;
240 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
241 244 jshamlet
      if( Rd_En_q = '1' )then
242
        case( Reg_Sel_q )is
243 175 jshamlet
          when "00" | "01" =>
244 217 jshamlet
            Rd_Data(7)       <= Tx_Ready;
245 175 jshamlet
          when "10" =>
246 217 jshamlet
            Rd_Data          <= LCD_Contrast;
247 175 jshamlet
          when "11" =>
248 217 jshamlet
            Rd_Data          <= LCD_Bright;
249 175 jshamlet
          when others => null;
250
        end case;
251
      end if;
252
    end if;
253
  end process;
254
 
255
--------------------------------------------------------------------------------
256
-- LCD and Register logic
257
--------------------------------------------------------------------------------
258
 
259 217 jshamlet
  LCD_RW                     <= '0'; -- Permanently wire the RW line low
260 175 jshamlet
 
261
  LCD_IO: process( Clock, Reset )
262
  begin
263
    if( Reset = Reset_Level )then
264 217 jshamlet
      io_state               <= INIT;
265
      init_count             <= (others => '0');
266
      io_timer               <= (others => '0');
267
      busy_timer             <= (others => '0');
268
      LCD_Data               <= (others => '0');
269
      LCD_Addr               <= '0';
270
      LCD_E                  <= '0';
271
      LCD_RS                 <= '0';
272
      LCD_D                  <= (others => '0');
273
      Tx_Ready               <= '0';
274
      Interrupt              <= '0';
275 175 jshamlet
    elsif( rising_edge(Clock) )then
276 217 jshamlet
      LCD_E                  <= '0';
277
      LCD_RS                 <= '0';
278
      LCD_D                  <= (others => '0');
279
      Tx_Ready               <= '0';
280
      Interrupt              <= '0';
281
      io_timer               <= io_timer - 1;
282
      busy_timer             <= busy_timer - uSec_Tick;
283 175 jshamlet
      case( io_state )is
284
 
285
        when INIT =>
286 217 jshamlet
          busy_timer         <= INIT_DELAY;
287
          init_count         <= (others => '1');
288
          io_state           <= PWR_WAIT;
289 175 jshamlet
 
290
        -- We wait for at least 40mS before continuing initalization.
291
        when PWR_WAIT =>
292
          if( busy_timer = 0 )then
293 217 jshamlet
            io_timer         <= SNH_DELAY;
294
            io_state         <= INIT_S1;
295 175 jshamlet
          end if;
296
 
297
        -- We write out the first init byte as if we were using an 8-bit
298
        --  data bus, with a single cycle. This is an exception, and the
299
        --  rest of the commands are sent using 2-cycle transfers.
300
        when INIT_S1 =>
301 217 jshamlet
          LCD_D              <= LCD_CONFIG1;
302
          LCD_E              <= '1';
303 175 jshamlet
          if( io_timer = 0 )then
304 217 jshamlet
            io_timer         <= SNH_DELAY;
305
            io_state         <= INIT_H1;
306 175 jshamlet
          end if;
307
 
308
        when INIT_H1 =>
309 217 jshamlet
          LCD_D              <= LCD_CONFIG1;
310 175 jshamlet
          if( io_timer = 0 )then
311 217 jshamlet
            busy_timer       <= BUSY_DELAY;
312
            io_state         <= INIT_WAIT;
313 175 jshamlet
          end if;
314
 
315
        when INIT_WAIT =>
316
          if( busy_timer = 0 )then
317 217 jshamlet
            io_state         <= FN_JUMP;
318 175 jshamlet
          end if;
319
 
320
        when FN_JUMP =>
321 217 jshamlet
          io_state           <= WR_PREP;
322 175 jshamlet
          case( init_count )is
323
            when "000" =>
324 217 jshamlet
              io_state       <= IDLE;
325 175 jshamlet
            when "001" =>
326 217 jshamlet
              LCD_Addr       <= '0';
327
              LCD_Data       <= LCD_CONFIG7; -- Reset the Cursor
328 175 jshamlet
            when "010" =>
329 217 jshamlet
              LCD_Addr       <= '1';         -- Print a "*", and
330
              LCD_Data       <= LCD_CONFIG6; --  set RS to 1
331 175 jshamlet
            when "011" =>
332 217 jshamlet
              LCD_Data       <= LCD_CONFIG5; -- Entry mode
333 175 jshamlet
            when "100" =>
334 217 jshamlet
              LCD_Data       <= LCD_CONFIG4; -- Clear Display
335 175 jshamlet
            when "101" =>
336 217 jshamlet
              LCD_Data       <= LCD_CONFIG3; -- Display control
337 175 jshamlet
            when "110" | "111" =>
338 217 jshamlet
              LCD_Addr       <= '0';
339
              LCD_Data       <= LCD_CONFIG2; -- Function set
340 175 jshamlet
            when others => null;
341
          end case;
342
 
343
        when IDLE =>
344 217 jshamlet
          Tx_Ready           <= '1';
345 175 jshamlet
          if( Reg_Valid = '1' )then
346 217 jshamlet
            LCD_Addr         <= Reg_Sel;
347
            LCD_Data         <= Reg_Data;
348
            io_state         <= WR_PREP;
349 175 jshamlet
          end if;
350
 
351
        when WR_PREP =>
352 217 jshamlet
          io_timer           <= SNH_DELAY;
353
          io_state           <= WR_SETUP_UB;
354 175 jshamlet
 
355
        when WR_SETUP_UB =>
356 217 jshamlet
          LCD_RS             <= LCD_Addr;
357
          LCD_D              <= LCD_Data(7 downto 4);
358
          LCD_E              <= '1';
359 175 jshamlet
          if( io_timer = 0 )then
360 217 jshamlet
            io_timer         <= SNH_DELAY;
361
            io_state         <= WR_HOLD_UB;
362 175 jshamlet
          end if;
363
 
364
        when WR_HOLD_UB =>
365 217 jshamlet
          LCD_RS             <= LCD_Addr;
366
          LCD_D              <= LCD_Data(7 downto 4);
367 175 jshamlet
          if( io_timer = 0 )then
368 217 jshamlet
            LCD_E            <= '0';
369
            io_timer         <= SNH_DELAY;
370
            io_state         <= WR_SETUP_LB;
371 175 jshamlet
          end if;
372
 
373
        when WR_SETUP_LB =>
374 217 jshamlet
          LCD_RS             <= LCD_Addr;
375
          LCD_D              <= LCD_Data(3 downto 0);
376
          LCD_E              <= '1';
377 175 jshamlet
          if( io_timer = 0 )then
378 217 jshamlet
            io_timer         <= SNH_DELAY;
379
            io_state         <= WR_HOLD_LB;
380 175 jshamlet
          end if;
381
 
382
        when WR_HOLD_LB =>
383 217 jshamlet
          LCD_RS             <= LCD_Addr;
384
          LCD_D              <= LCD_Data(3 downto 0);
385 175 jshamlet
          if( io_timer = 0 )then
386 217 jshamlet
            io_state         <= BUSY_WAIT;
387 175 jshamlet
          end if;
388
 
389
        when BUSY_PREP =>
390 217 jshamlet
          busy_timer         <= BUSY_DELAY;
391 175 jshamlet
          if( LCD_Addr = '0' and LCD_Data < 4 )then
392 217 jshamlet
            busy_timer       <= CLDSP_DELAY;
393 175 jshamlet
          end if;
394 217 jshamlet
          io_state           <= BUSY_WAIT;
395 175 jshamlet
 
396
        when BUSY_WAIT =>
397
          if( busy_timer = 0 )then
398 217 jshamlet
            io_state         <= ISSUE_INT;
399 175 jshamlet
            if( init_count > 0 )then
400 217 jshamlet
              init_count     <= init_count - 1;
401
              io_state       <= FN_JUMP;
402 175 jshamlet
            end if;
403
          end if;
404
 
405
        when ISSUE_INT =>
406 217 jshamlet
          Interrupt          <= '1';
407
          io_state           <= IDLE;
408 175 jshamlet
 
409
        when others => null;
410
 
411
      end case;
412
 
413
    end if;
414
  end process;
415
 
416
--------------------------------------------------------------------------------
417
-- Contrast control logic (optional)
418
--------------------------------------------------------------------------------
419
 
420
Contrast_Disabled: if( not Use_Contrast )generate
421
  LCD_CN                <= '0';
422
end generate;
423
 
424
Contrast_Enabled: if( Use_Contrast )generate
425
 
426 217 jshamlet
  U_CN : entity work.vdsm8
427
  generic map(
428
    Reset_Level              => Reset_Level
429
  )
430
  port map(
431
    Clock                    => Clock,
432
    Reset                    => Reset,
433
    DACin                    => LCD_Contrast,
434
    DACout                   => LCD_CN
435
  );
436 175 jshamlet
 
437
end generate;
438
 
439
--------------------------------------------------------------------------------
440
-- Backlight control logic (optional)
441
--------------------------------------------------------------------------------
442
 
443
Backlight_Disabled: if( not Use_Backlight )generate
444
  LCD_BL                <= '0';
445
end generate;
446
 
447
Backlight_Enabled: if( Use_Backlight )generate
448
 
449 217 jshamlet
  U_BL : entity work.vdsm8
450
  generic map(
451
    Reset_Level              => Reset_Level
452
  )
453
  port map(
454
    Clock                    => Clock,
455
    Reset                    => Reset,
456
    DACin                    => LCD_Bright,
457
    DACout                   => LCD_BL
458
  );
459 175 jshamlet
 
460
end generate;
461
 
462
end architecture;

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