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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_8b.vhd] - Blame information for rev 186

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1 175 jshamlet
-- VHDL Entity: o8_hd44780_8b
2
-- Description: Provides low-level access to a "standard" character LCD using
3
--               the ST/HD44780(U) control ASIC wired in full (8-bit) mode.
4
--              All low-level timing of the control signals are handled by this
5
--               module, allowing client firmware to use a simple register
6
--               interface to program the LCD panel.
7
--              Init routine initializes the display and displays a single
8
--               character to demonstrate correct function, then listens for
9
--               user data on its external interface.
10
 
11
library ieee;
12
use ieee.std_logic_1164.all;
13
use ieee.std_logic_unsigned.all;
14
use ieee.std_logic_arith.all;
15
 
16
library work;
17
use work.open8_pkg.all;
18
 
19
entity o8_hd44780_8b is
20
generic(
21
  Use_Contrast          : boolean;
22
  Default_Contrast      : std_logic_vector(7 downto 0);
23
  Use_Backlight         : boolean;
24
  Default_Brightness    : std_logic_vector(7 downto 0);
25
  Address               : ADDRESS_TYPE;
26
  Reset_Level           : std_logic;
27
  Sys_Freq              : real
28
);
29
port(
30
  Clock                 : in  std_logic;
31
  Reset                 : in  std_logic;
32
  uSec_Tick             : in  std_logic;
33
  --
34
  Bus_Address           : in  ADDRESS_TYPE;
35
  Wr_Enable             : in  std_logic;
36
  Wr_Data               : in  DATA_TYPE;
37
  Rd_Enable             : in  std_logic;
38
  Rd_Data               : out DATA_TYPE;
39
  Interrupt             : out std_logic;
40
  --
41
  LCD_E                 : out std_logic;
42
  LCD_RW                : out std_logic;
43
  LCD_RS                : out std_logic;
44
  LCD_D                 : out std_logic_vector(7 downto 0);
45
  LCD_CN                : out std_logic;
46
  LCD_BL                : out std_logic
47
);
48
end entity;
49
 
50
architecture behave of o8_hd44780_8b is
51
 
52
  -- The ceil_log2 function returns the minimum register width required to
53
  --  hold the supplied integer.
54
  function ceil_log2 (x : in natural) return natural is
55
    variable retval          : natural;
56
  begin
57
    retval                   := 1;
58
    while ((2**retval) - 1) < x loop
59
      retval                 := retval + 1;
60
    end loop;
61
    return retval;
62
  end ceil_log2;
63
 
64
  constant User_Addr    : std_logic_vector(15 downto 2)
65
                          := Address(15 downto 2);
66
  alias  Comp_Addr      is Bus_Address(15 downto 2);
67
  signal Addr_Match     : std_logic;
68
 
69
  alias  Reg_Addr        is Bus_Address(1 downto 0);
70
  signal Reg_Addr_q     : std_logic_vector(1 downto 0);
71
 
72
  signal Wr_En          : std_logic;
73
  signal Wr_Data_q      : DATA_TYPE;
74
  signal Rd_En          : std_logic;
75
 
76
  signal Reg_Valid      : std_logic;
77
  signal Reg_Sel        : std_logic;
78
  signal Reg_Data       : std_logic_vector(7 downto 0);
79
 
80
  signal Tx_Ready       : std_logic;
81
 
82
--------------------------------------------------------------------------------
83
-- LCD Controller
84
--------------------------------------------------------------------------------
85
 
86
-- Register Map
87
-- Address  Function
88
-- Offset  Bitfield Description                        Read/Write
89
-- 0x0     AAAAAAAA LCD Register Write                 (Write-only)
90
-- 0x1     AAAAAAAA LCD Data Write                     (Write-only)
91
-- 0x2     AAAAAAAA LCD Contrast                       (Read-Write)
92
-- 0x3     AAAAAAAA LCD Backlight                      (Read-Write)
93
 
94
-- LCD Instruction Set
95
-- Instruction             RS  RW  D7  D6  D5  D4  D3  D2  D1  D0  Time
96
------------------------------------------------------------------------
97
-- Clear Display         | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
98
-- Return Home           | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
99
-- Entry Mode            | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S |   37uS
100
-- Display Pwr           | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B |   37uS
101
-- Cursor/Display Shift  | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x |   37uS
102
-- Function Set          | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x |   37uS
103
-- Set CGRAM Address     | 0 | 0 | 0 | 1 | A | A | A | A | A | A |   37uS
104
-- Set DDRAM Address     | 0 | 0 | 1 | A | A | A | A | A | A | A |   37uS
105
 
106
-- Notes:
107
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
108
-- S  = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
109
-- D  = Display On/Off (1 = on, 0 = off)
110
-- C  = Cursor On/Off  (1 = on, 0 = off)
111
-- B  = Cursor Blink   (1 = block cursor, 0 = underline cursor)
112
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
113
-- F  = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
114
-- N  = Number of Lines (0 = 1 lines, 1 = 2 lines)
115
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
116
-- A  = Address (see data sheet for usage)
117
 
118
  constant LCD_CONFIG1  : std_logic_vector(7 downto 0) := x"38"; -- Set 4-bit, 2-line mode
119
  constant LCD_CONFIG2  : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
120
  constant LCD_CONFIG3  : std_logic_vector(7 downto 0) := x"01"; -- Clear display
121
  constant LCD_CONFIG4  : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
122
  constant LCD_CONFIG5  : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
123
  constant LCD_CONFIG6  : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
124
 
125
  signal init_count     : std_logic_vector(2 downto 0);
126
 
127
  constant INIT_40MS    : integer := 40000;
128
  constant INIT_BITS    : integer := ceil_log2(INIT_40MS);
129
  constant INIT_DELAY   : std_logic_vector(INIT_BITS-1 downto 0) :=
130
                          conv_std_logic_vector(INIT_40MS,INIT_BITS);
131
 
132
-- For "long" instructions, such as clear display and return home, we need to wait for more
133
--  than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
134
  constant CLDSP_2MS    : integer := 2000;
135
  constant CLDSP_DELAY  : std_logic_vector(INIT_BITS-1 downto 0) :=
136
                          conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
137
 
138
 -- For some reason, we are required to wait 80uS before checking the busy flag, despite
139
 --  most instructions completing in 37uS. No clue as to why, but it works
140
  constant BUSY_50US    : integer := 50;
141
  constant BUSY_DELAY   : std_logic_vector(INIT_BITS-1 downto 0) :=
142
                          conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
143
 
144
  signal busy_timer     : std_logic_vector(INIT_BITS-1 downto 0);
145
 
146
  constant SNH_600NS    : integer := integer(Sys_Freq * 0.000000600);
147
  constant SNH_BITS     : integer := ceil_log2(SNH_600NS);
148
  constant SNH_DELAY    : std_logic_vector(SNH_BITS-1 downto 0) :=
149
                          conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
150
 
151
  signal io_timer       : std_logic_vector(SNH_BITS - 1 downto 0);
152
 
153
  type IO_STATES is (INIT, FN_JUMP, IDLE,
154
                     WR_PREP, WR_SETUP, WR_HOLD,
155
                     BUSY_PREP, BUSY_WAIT,
156
                     ISSUE_INT );
157
  signal io_state       : IO_STATES;
158
 
159
  signal LCD_Data       : std_logic_vector(7 downto 0);
160
  signal LCD_Addr       : std_logic;
161
 
162
--------------------------------------------------------------------------------
163
-- Backlight & Contrast signals
164
--------------------------------------------------------------------------------
165
 
166
  -- Do not adjust alone! DELTA constants must be
167
  --  changed as well.
168
  constant DAC_Width    : integer := 8;
169
 
170
  constant DELTA_1_I    : integer := 1;
171
  constant DELTA_2_I    : integer := 5;
172
  constant DELTA_3_I    : integer := 25;
173
  constant DELTA_4_I    : integer := 75;
174
  constant DELTA_5_I    : integer := 125;
175
  constant DELTA_6_I    : integer := 195;
176
 
177
  constant DELTA_1      : std_logic_vector(DAC_Width-1 downto 0) :=
178
                           conv_std_logic_vector(DELTA_1_I, DAC_Width);
179
  constant DELTA_2      : std_logic_vector(DAC_Width-1 downto 0) :=
180
                           conv_std_logic_vector(DELTA_2_I, DAC_Width);
181
  constant DELTA_3      : std_logic_vector(DAC_Width-1 downto 0) :=
182
                           conv_std_logic_vector(DELTA_3_I, DAC_Width);
183
  constant DELTA_4      : std_logic_vector(DAC_Width-1 downto 0) :=
184
                           conv_std_logic_vector(DELTA_4_I, DAC_Width);
185
  constant DELTA_5      : std_logic_vector(DAC_Width-1 downto 0) :=
186
                           conv_std_logic_vector(DELTA_5_I, DAC_Width);
187
  constant DELTA_6      : std_logic_vector(DAC_Width-1 downto 0) :=
188
                           conv_std_logic_vector(DELTA_6_I, DAC_Width);
189
 
190
  constant MAX_PERIOD   : integer := 2**DAC_Width;
191
  constant DIV_WIDTH    : integer := DAC_Width * 2;
192
 
193
  constant PADJ_1_I     : integer := DELTA_1_I * MAX_PERIOD;
194
  constant PADJ_2_I     : integer := DELTA_2_I * MAX_PERIOD;
195
  constant PADJ_3_I     : integer := DELTA_3_I * MAX_PERIOD;
196
  constant PADJ_4_I     : integer := DELTA_4_I * MAX_PERIOD;
197
  constant PADJ_5_I     : integer := DELTA_5_I * MAX_PERIOD;
198
  constant PADJ_6_I     : integer := DELTA_6_I * MAX_PERIOD;
199
 
200
  constant PADJ_1       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
201
                           conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
202
  constant PADJ_2       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
203
                           conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
204
  constant PADJ_3       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
205
                           conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
206
  constant PADJ_4       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
207
                           conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
208
  constant PADJ_5       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
209
                           conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
210
  constant PADJ_6       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
211
                           conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
212
 
213
  constant CB           : integer := ceil_log2(DIV_WIDTH);
214
 
215
  signal LCD_Contrast   : std_logic_vector(7 downto 0);
216
 
217
  signal CN_DACin_q     : std_logic_vector(DAC_WIDTH-1 downto 0);
218
 
219
  signal CN_Divisor     : std_logic_vector(DIV_WIDTH-1 downto 0);
220
  signal CN_Dividend    : std_logic_vector(DIV_WIDTH-1 downto 0);
221
 
222
  signal CN_q           : std_logic_vector(DIV_WIDTH*2-1 downto 0);
223
  signal CN_diff        : std_logic_vector(DIV_WIDTH downto 0);
224
 
225
  signal CN_count       : std_logic_vector(CB-1 downto 0);
226
 
227
  signal CN_Next_Wdt    : std_logic_vector(DAC_Width-1 downto 0);
228
  signal CN_Next_Per    : std_logic_vector(DAC_Width-1 downto 0);
229
 
230
  signal CN_PWM_Wdt     : std_logic_vector(DAC_Width-1 downto 0);
231
  signal CN_PWM_Per     : std_logic_vector(DAC_Width-1 downto 0);
232
 
233
  signal CN_Wdt_Ctr     : std_logic_vector(DAC_Width-1 downto 0);
234
  signal CN_Per_Ctr     : std_logic_vector(DAC_Width-1 downto 0);
235
 
236
  signal LCD_Bright     : std_logic_vector(7 downto 0);
237
 
238
  signal BL_DACin_q     : std_logic_vector(DAC_WIDTH-1 downto 0);
239
 
240
  signal BL_Divisor     : std_logic_vector(DIV_WIDTH-1 downto 0);
241
  signal BL_Dividend    : std_logic_vector(DIV_WIDTH-1 downto 0);
242
 
243
  signal BL_q           : std_logic_vector(DIV_WIDTH*2-1 downto 0);
244
  signal BL_diff        : std_logic_vector(DIV_WIDTH downto 0);
245
 
246
  signal BL_count       : std_logic_vector(CB-1 downto 0);
247
 
248
  signal BL_Next_Wdt    : std_logic_vector(DAC_Width-1 downto 0);
249
  signal BL_Next_Per    : std_logic_vector(DAC_Width-1 downto 0);
250
 
251
  signal BL_PWM_Wdt     : std_logic_vector(DAC_Width-1 downto 0);
252
  signal BL_PWM_Per     : std_logic_vector(DAC_Width-1 downto 0);
253
 
254
  signal BL_Wdt_Ctr     : std_logic_vector(DAC_Width-1 downto 0);
255
  signal BL_Per_Ctr     : std_logic_vector(DAC_Width-1 downto 0);
256
 
257
begin
258
 
259
--------------------------------------------------------------------------------
260
-- Open8 Register interface
261
--------------------------------------------------------------------------------
262
 
263
  Addr_Match            <= '1' when Comp_Addr = User_Addr else '0';
264
 
265
  io_reg: process( Clock, Reset )
266
  begin
267
    if( Reset = Reset_Level )then
268
      Reg_Addr_q        <= (others => '0');
269
      Wr_Data_q         <= (others => '0');
270
      Wr_En             <= '0';
271
      Rd_En             <= '0';
272
      Rd_Data           <= (others => '0');
273
 
274
      Reg_Valid         <= '0';
275
      Reg_Sel           <= '0';
276
      Reg_Data          <= x"00";
277
 
278
      LCD_Contrast      <= Default_Contrast;
279
      LCD_Bright        <= Default_Brightness;
280
    elsif( rising_edge( Clock ) )then
281
      Reg_Addr_q        <= Reg_Addr;
282
 
283
      Wr_Data_q         <= Wr_Data;
284
      Wr_En             <= Addr_Match and Wr_Enable;
285
 
286
      Reg_Valid         <= '0';
287
 
288
      if( Wr_En = '1' )then
289
        case( Reg_Addr_q )is
290
          when "00" | "01" =>
291
            Reg_Valid   <= '1';
292
            Reg_Sel     <= Reg_Addr_q(0);
293
            Reg_Data    <= Wr_Data_q;
294
          when "10" =>
295
            LCD_Contrast<= Wr_Data_q;
296
          when "11" =>
297
            LCD_Bright  <= Wr_Data_q;
298
          when others => null;
299
        end case;
300
      end if;
301
 
302
      Rd_Data           <= (others => '0');
303
      Rd_En             <= Addr_Match and Rd_Enable;
304
      if( Rd_En = '1' )then
305
        case( Reg_Addr_q )is
306
          when "00" | "01" =>
307
            Rd_Data(7)  <= Tx_Ready;
308
          when "10" =>
309
            Rd_Data     <= LCD_Contrast;
310
          when "11" =>
311
            Rd_Data     <= LCD_Bright;
312
          when others => null;
313
        end case;
314
      end if;
315
    end if;
316
  end process;
317
 
318
--------------------------------------------------------------------------------
319
-- LCD and Register logic
320
--------------------------------------------------------------------------------
321
 
322
  LCD_RW                <= '0'; -- Permanently wire the RW line low
323
 
324
  LCD_IO: process( Clock, Reset )
325
  begin
326
    if( Reset = Reset_Level )then
327
      io_state          <= INIT;
328
      init_count        <= (others => '0');
329
      io_timer          <= (others => '0');
330
      busy_timer        <= (others => '0');
331
      LCD_Data          <= (others => '0');
332
      LCD_Addr          <= '0';
333
      LCD_E             <= '0';
334
      LCD_RS            <= '0';
335
      LCD_D             <= (others => '0');
336
      Tx_Ready          <= '0';
337
      Interrupt         <= '0';
338
    elsif( rising_edge(Clock) )then
339
      LCD_E             <= '0';
340
      LCD_RS            <= '0';
341
      LCD_D             <= (others => '0');
342
      Tx_Ready          <= '0';
343
      Interrupt         <= '0';
344
      io_timer          <= io_timer - 1;
345
      busy_timer        <= busy_timer - uSec_Tick;
346
      case( io_state )is
347
 
348
        when INIT =>
349
          busy_timer    <= INIT_DELAY;
350
          init_count    <= (others => '1');
351
          io_state      <= BUSY_WAIT;
352
 
353
        when FN_JUMP =>
354
          io_state      <= WR_PREP;
355
          case( init_count )is
356
            when "000" =>
357
              io_state  <= IDLE;
358
            when "001" =>
359
              LCD_Addr  <= '0';
360
              LCD_Data  <= LCD_CONFIG6; -- Reset the Cursor
361
            when "010" =>
362
              LCD_Addr  <= '1';         -- Print a "*", and
363
              LCD_Data  <= LCD_CONFIG5; --  set RS to 1
364
            when "011" =>
365
              LCD_Data  <= LCD_CONFIG4; -- Entry mode
366
            when "100" =>
367
              LCD_Data  <= LCD_CONFIG3; -- Clear Display
368
            when "101" =>
369
              LCD_Data  <= LCD_CONFIG2; -- Display control
370
            when "110" | "111" =>
371
              LCD_Addr  <= '0';
372
              LCD_Data  <= LCD_CONFIG1; -- Function set
373
            when others => null;
374
          end case;
375
 
376
        when IDLE =>
377
          Tx_Ready      <= '1';
378
          if( Reg_Valid = '1' )then
379
            LCD_Addr    <= Reg_Sel;
380
            LCD_Data    <= Reg_Data;
381
            io_state    <= WR_PREP;
382
          end if;
383
 
384
        when WR_PREP =>
385
          io_timer      <= SNH_DELAY;
386
          io_state      <= WR_SETUP;
387
 
388
        when WR_SETUP =>
389
          LCD_RS        <= LCD_Addr;
390
          LCD_D         <= LCD_Data;
391
          LCD_E         <= '1';
392
          if( io_timer = 0 )then
393
            io_timer    <= SNH_DELAY;
394
            io_state    <= WR_HOLD;
395
          end if;
396
 
397
        when WR_HOLD =>
398
          LCD_RS        <= LCD_Addr;
399
          LCD_D         <= LCD_Data;
400
          if( io_timer = 0 )then
401
            LCD_E       <= '0';
402
            io_state    <= BUSY_PREP;
403
          end if;
404
 
405
        when BUSY_PREP =>
406
          busy_timer    <= BUSY_DELAY;
407
          if( LCD_Addr = '0' and LCD_Data < 4 )then
408
            busy_timer  <= CLDSP_DELAY;
409
          end if;
410
          io_state      <= BUSY_WAIT;
411
 
412
        when BUSY_WAIT =>
413
          if( busy_timer = 0 )then
414
            io_state    <= ISSUE_INT;
415
            if( init_count > 0 )then
416
              init_count<= init_count - 1;
417
              io_state  <= FN_JUMP;
418
            end if;
419
          end if;
420
 
421
        when ISSUE_INT =>
422
          Interrupt     <= '1';
423
          io_state      <= IDLE;
424
 
425
        when others => null;
426
 
427
      end case;
428
 
429
    end if;
430
  end process;
431
 
432
--------------------------------------------------------------------------------
433
-- Contrast control logic (optional)
434
--------------------------------------------------------------------------------
435
 
436
Contrast_Disabled: if( not Use_Contrast )generate
437
  LCD_CN                <= '0';
438
end generate;
439
 
440
Contrast_Enabled: if( Use_Contrast )generate
441
 
442
  CN_diff               <= ('0' & CN_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
443
                           ('0' & CN_Divisor);
444
 
445
  CN_Dividend<= PADJ_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
446
                PADJ_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
447
                PADJ_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
448
                PADJ_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
449
                PADJ_6 when CN_DACin_q >= DELTA_6_I else
450
                PADJ_1;
451
 
452
  CN_Next_Wdt<= DELTA_1 when CN_DACin_q >= DELTA_1_I and CN_DACin_q < DELTA_2_I else
453
                DELTA_2 when CN_DACin_q >= DELTA_2_I and CN_DACin_q < DELTA_3_I else
454
                DELTA_3 when CN_DACin_q >= DELTA_3_I and CN_DACin_q < DELTA_4_I else
455
                DELTA_4 when CN_DACin_q >= DELTA_4_I and CN_DACin_q < DELTA_5_I else
456
                DELTA_5 when CN_DACin_q >= DELTA_5_I and CN_DACin_q < DELTA_6_I else
457
                DELTA_6 when CN_DACin_q >= DELTA_6_I else
458
                (others => '0');
459
 
460
  CN_Next_Per           <= BL_q(7 downto 0) - 1;
461
 
462
  CN_vDSM_proc: process( Clock, Reset )
463
  begin
464
    if( Reset = Reset_Level )then
465
      CN_q              <= (others => '0');
466
      CN_count          <= (others => '1');
467
      CN_Divisor        <= (others => '0');
468
      CN_DACin_q        <= (others => '0');
469
      CN_PWM_Wdt        <= (others => '0');
470
      CN_PWM_Per        <= (others => '0');
471
      CN_Per_Ctr        <= (others => '0');
472
      CN_Wdt_Ctr        <= (others => '0');
473
      LCD_CN            <= '0';
474
    elsif( rising_edge(Clock) )then
475
      CN_q              <= CN_diff(DIV_WIDTH-1 downto 0) &
476
                           CN_q(DIV_WIDTH-2 downto 0) & '1';
477
      if( CN_diff(DIV_WIDTH) = '1' )then
478
        CN_q            <= CN_q(DIV_WIDTH*2-2 downto 0) & '0';
479
      end if;
480
 
481
      CN_count          <= CN_count + 1;
482
      if( CN_count = DIV_WIDTH )then
483
        CN_PWM_Wdt      <= CN_Next_Wdt;
484
        CN_PWM_Per      <= CN_Next_Per;
485
        CN_DACin_q      <= LCD_Contrast;
486
        CN_Divisor      <= (others => '0');
487
        CN_Divisor(DAC_Width-1 downto 0) <= CN_DACin_q;
488
        CN_q            <= conv_std_logic_vector(0,DIV_WIDTH) & CN_Dividend;
489
        CN_count        <= (others => '0');
490
      end if;
491
 
492
      CN_Per_Ctr        <= CN_Per_Ctr - 1;
493
      CN_Wdt_Ctr        <= CN_Wdt_Ctr - 1;
494
 
495
      LCD_CN            <= '1';
496
      if( CN_Wdt_Ctr = 0 )then
497
        LCD_CN          <= '0';
498
        CN_Wdt_Ctr      <= (others => '0');
499
      end if;
500
 
501
      if( CN_Per_Ctr = 0 )then
502
        CN_Per_Ctr      <= CN_PWM_Per;
503
        CN_Wdt_Ctr      <= CN_PWM_Wdt;
504
      end if;
505
 
506
    end if;
507
  end process;
508
end generate;
509
 
510
--------------------------------------------------------------------------------
511
-- Backlight control logic (optional)
512
--------------------------------------------------------------------------------
513
 
514
Backlight_Disabled: if( not Use_Backlight )generate
515
  LCD_BL                <= '0';
516
end generate;
517
 
518
Backlight_Enabled: if( Use_Backlight )generate
519
 
520
  BL_diff               <= ('0' & BL_q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
521
                           ('0' & BL_Divisor);
522
 
523
  BL_Dividend<= PADJ_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
524
                PADJ_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
525
                PADJ_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
526
                PADJ_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
527
                PADJ_6 when BL_DACin_q >= DELTA_6_I else
528
                PADJ_1;
529
 
530
  BL_Next_Wdt<= DELTA_1 when BL_DACin_q >= DELTA_1_I and BL_DACin_q < DELTA_2_I else
531
                DELTA_2 when BL_DACin_q >= DELTA_2_I and BL_DACin_q < DELTA_3_I else
532
                DELTA_3 when BL_DACin_q >= DELTA_3_I and BL_DACin_q < DELTA_4_I else
533
                DELTA_4 when BL_DACin_q >= DELTA_4_I and BL_DACin_q < DELTA_5_I else
534
                DELTA_5 when BL_DACin_q >= DELTA_5_I and BL_DACin_q < DELTA_6_I else
535
                DELTA_6 when BL_DACin_q >= DELTA_6_I else
536
                (others => '0');
537
 
538
  BL_Next_Per           <= BL_q(7 downto 0) - 1;
539
 
540
  BL_vDSM_proc: process( Clock, Reset )
541
  begin
542
    if( Reset = Reset_Level )then
543
      BL_q              <= (others => '0');
544
      BL_count          <= (others => '1');
545
      BL_Divisor        <= (others => '0');
546
      BL_DACin_q        <= (others => '0');
547
      BL_PWM_Wdt        <= (others => '0');
548
      BL_PWM_Per        <= (others => '0');
549
      BL_Per_Ctr        <= (others => '0');
550
      BL_Wdt_Ctr        <= (others => '0');
551
      LCD_BL            <= '0';
552
    elsif( rising_edge(Clock) )then
553
      BL_q              <= BL_diff(DIV_WIDTH-1 downto 0) &
554
                           BL_q(DIV_WIDTH-2 downto 0) & '1';
555
      if( BL_diff(DIV_WIDTH) = '1' )then
556
        BL_q            <= BL_q(DIV_WIDTH*2-2 downto 0) & '0';
557
      end if;
558
 
559
      BL_count          <= BL_count + 1;
560
      if( BL_count = DIV_WIDTH )then
561
        BL_PWM_Wdt      <= BL_Next_Wdt;
562
        BL_PWM_Per      <= BL_Next_Per;
563
        BL_DACin_q      <= LCD_Bright;
564
        BL_Divisor      <= (others => '0');
565
        BL_Divisor(DAC_Width-1 downto 0) <= BL_DACin_q;
566
        BL_q            <= conv_std_logic_vector(0,DIV_WIDTH) & BL_Dividend;
567
        BL_count        <= (others => '0');
568
      end if;
569
 
570
      BL_Per_Ctr        <= BL_Per_Ctr - 1;
571
      BL_Wdt_Ctr        <= BL_Wdt_Ctr - 1;
572
 
573
      LCD_BL            <= '1';
574
      if( BL_Wdt_Ctr = 0 )then
575
        LCD_BL          <= '0';
576
        BL_Wdt_Ctr      <= (others => '0');
577
      end if;
578
 
579
      if( BL_Per_Ctr = 0 )then
580
        BL_Per_Ctr      <= BL_PWM_Per;
581
        BL_Wdt_Ctr      <= BL_PWM_Wdt;
582
      end if;
583
 
584
    end if;
585
  end process;
586
 
587
end generate;
588
 
589
end architecture;

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