OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_8b.vhd] - Blame information for rev 253

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 194 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 213 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 194 jshamlet
--
24 175 jshamlet
-- VHDL Entity: o8_hd44780_8b
25
-- Description: Provides low-level access to a "standard" character LCD using
26
--               the ST/HD44780(U) control ASIC wired in full (8-bit) mode.
27 213 jshamlet
--              All low-level timing of the control signals are handled by
28
--               this module, allowing client firmware to use a simple
29
--               register interface to program the LCD panel.
30 175 jshamlet
--              Init routine initializes the display and displays a single
31
--               character to demonstrate correct function, then listens for
32
--               user data on its external interface.
33 213 jshamlet
--
34
-- Register Map
35
-- Address  Function
36
-- Offset  Bitfield Description                        Read/Write
37
-- 0x0     AAAAAAAA LCD Register Write                 (Write-only)
38
-- 0x1     AAAAAAAA LCD Data Write                     (Write-only)
39
-- 0x2     AAAAAAAA LCD Contrast                       (Read-Write)
40
-- 0x3     AAAAAAAA LCD Backlight                      (Read-Write)
41
--
42
--------------------------------------------------------------------------------
43
-- LCD Controller
44
--------------------------------------------------------------------------------
45
--
46
-- LCD Instruction Set
47
-- Instruction             RS  RW  D7  D6  D5  D4  D3  D2  D1  D0  Time
48
------------------------------------------------------------------------
49
-- Clear Display         | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
50
-- Return Home           | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
51
-- Entry Mode            | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S |   37uS
52
-- Display Pwr           | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B |   37uS
53
-- Cursor/Display Shift  | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x |   37uS
54
-- Function Set          | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x |   37uS
55
-- Set CGRAM Address     | 0 | 0 | 0 | 1 | A | A | A | A | A | A |   37uS
56
-- Set DDRAM Address     | 0 | 0 | 1 | A | A | A | A | A | A | A |   37uS
57 175 jshamlet
 
58 213 jshamlet
-- Notes:
59
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
60
-- S  = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
61
-- D  = Display On/Off (1 = on, 0 = off)
62
-- C  = Cursor On/Off  (1 = on, 0 = off)
63
-- B  = Cursor Blink   (1 = block cursor, 0 = underline cursor)
64
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
65
-- F  = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
66
-- N  = Number of Lines (0 = 1 lines, 1 = 2 lines)
67
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
68
-- A  = Address (see data sheet for usage)
69
--
70
-- Revision History
71
-- Author          Date     Change
72
------------------ -------- ---------------------------------------------------
73
-- Seth Henry      01/22/13 Design Start
74
-- Seth Henry      04/10/20 Code & comment cleanup
75 224 jshamlet
-- Seth Henry      04/16/20 Modified to use Open8 bus record
76 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
77 213 jshamlet
 
78 175 jshamlet
library ieee;
79
use ieee.std_logic_1164.all;
80
use ieee.std_logic_unsigned.all;
81
use ieee.std_logic_arith.all;
82
 
83
library work;
84
use work.open8_pkg.all;
85
 
86
entity o8_hd44780_8b is
87
generic(
88
  Use_Contrast          : boolean;
89
  Default_Contrast      : std_logic_vector(7 downto 0);
90
  Use_Backlight         : boolean;
91
  Default_Brightness    : std_logic_vector(7 downto 0);
92 224 jshamlet
  Clock_Frequency       : real;
93
  Address               : ADDRESS_TYPE
94 175 jshamlet
);
95
port(
96 223 jshamlet
  Open8_Bus             : in  OPEN8_BUS_TYPE;
97 244 jshamlet
  Write_Qual            : in  std_logic := '1';
98 175 jshamlet
  Rd_Data               : out DATA_TYPE;
99
  Interrupt             : out std_logic;
100
  --
101
  LCD_E                 : out std_logic;
102
  LCD_RW                : out std_logic;
103
  LCD_RS                : out std_logic;
104
  LCD_D                 : out std_logic_vector(7 downto 0);
105
  LCD_CN                : out std_logic;
106
  LCD_BL                : out std_logic
107
);
108
end entity;
109
 
110
architecture behave of o8_hd44780_8b is
111
 
112 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
113
  alias Reset                is Open8_Bus.Reset;
114
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
115
 
116 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 2)
117
                               := Address(15 downto 2);
118 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
119 244 jshamlet
  signal Addr_Match          : std_logic;
120 175 jshamlet
 
121 244 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
122
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
123
  signal Wr_En_d             : std_logic := '0';
124
  signal Wr_En_q             : std_logic := '0';
125
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
126 217 jshamlet
  signal Wr_Data_q           : DATA_TYPE := x"00";
127 244 jshamlet
  signal Rd_En_d             : std_logic := '0';
128
  signal Rd_En_q             : std_logic := '0';
129 175 jshamlet
 
130 217 jshamlet
  signal Reg_Valid           : std_logic := '0';
131
  signal Reg_Sel             : std_logic := '0';
132
  signal Reg_Data            : DATA_TYPE := x"00";
133 175 jshamlet
 
134 217 jshamlet
  signal Tx_Ready            : std_logic := '0';
135 175 jshamlet
 
136 217 jshamlet
  constant LCD_CONFIG1       : std_logic_vector(7 downto 0) := x"38"; -- Set 4-bit, 2-line mode
137
  constant LCD_CONFIG2       : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
138
  constant LCD_CONFIG3       : std_logic_vector(7 downto 0) := x"01"; -- Clear display
139
  constant LCD_CONFIG4       : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
140
  constant LCD_CONFIG5       : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
141
  constant LCD_CONFIG6       : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
142 175 jshamlet
 
143 217 jshamlet
  signal init_count          : std_logic_vector(2 downto 0) := (others => '0');
144 175 jshamlet
 
145 217 jshamlet
  constant INIT_40MS         : integer := 40000;
146
  constant INIT_BITS         : integer := ceil_log2(INIT_40MS);
147
  constant INIT_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
148
                               conv_std_logic_vector(INIT_40MS,INIT_BITS);
149 175 jshamlet
 
150
-- For "long" instructions, such as clear display and return home, we need to wait for more
151
--  than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
152 217 jshamlet
  constant CLDSP_2MS         : integer := 2000;
153
  constant CLDSP_DELAY       : std_logic_vector(INIT_BITS-1 downto 0) :=
154
                               conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
155 175 jshamlet
 
156
 -- For some reason, we are required to wait 80uS before checking the busy flag, despite
157
 --  most instructions completing in 37uS. No clue as to why, but it works
158 217 jshamlet
  constant BUSY_50US         : integer := 50;
159
  constant BUSY_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
160
                               conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
161 175 jshamlet
 
162 217 jshamlet
  signal busy_timer          : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
163 175 jshamlet
 
164 224 jshamlet
  constant SNH_600NS         : integer := integer(Clock_Frequency * 0.000000600);
165 217 jshamlet
  constant SNH_BITS          : integer := ceil_log2(SNH_600NS);
166
  constant SNH_DELAY         : std_logic_vector(SNH_BITS-1 downto 0) :=
167
                               conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
168 175 jshamlet
 
169 217 jshamlet
  signal io_timer            : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');
170 175 jshamlet
 
171
  type IO_STATES is (INIT, FN_JUMP, IDLE,
172
                     WR_PREP, WR_SETUP, WR_HOLD,
173
                     BUSY_PREP, BUSY_WAIT,
174
                     ISSUE_INT );
175 217 jshamlet
  signal io_state            : IO_STATES;
176 175 jshamlet
 
177 217 jshamlet
  signal LCD_Data            : DATA_TYPE := x"00";
178
  signal LCD_Addr            : std_logic := '0';
179 175 jshamlet
 
180
--------------------------------------------------------------------------------
181
-- Backlight & Contrast signals
182
--------------------------------------------------------------------------------
183
 
184 217 jshamlet
  signal LCD_Contrast        : DATA_TYPE := x"00";
185
  signal LCD_Bright          : DATA_TYPE := x"00";
186 175 jshamlet
 
187
begin
188
 
189
--------------------------------------------------------------------------------
190
-- Open8 Register interface
191
--------------------------------------------------------------------------------
192
 
193 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
194 244 jshamlet
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
195
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
196 175 jshamlet
 
197
  io_reg: process( Clock, Reset )
198
  begin
199
    if( Reset = Reset_Level )then
200 244 jshamlet
      Reg_Sel_q              <= "00";
201
      Wr_En_q                <= '0';
202
      Wr_Data_q              <= x"00";
203
      Rd_En_q                <= '0';
204 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
205 175 jshamlet
 
206 217 jshamlet
      Reg_Valid              <= '0';
207
      Reg_Sel                <= '0';
208
      Reg_Data               <= x"00";
209 175 jshamlet
 
210 217 jshamlet
      LCD_Contrast           <= Default_Contrast;
211
      LCD_Bright             <= Default_Brightness;
212 175 jshamlet
    elsif( rising_edge( Clock ) )then
213 244 jshamlet
      Reg_Sel_q              <= Reg_Sel_d;
214 175 jshamlet
 
215 244 jshamlet
      Wr_En_q                <= Wr_En_d;
216
      Wr_Data_q              <= Wr_Data_d;
217 217 jshamlet
      Reg_Valid              <= '0';
218 244 jshamlet
      if( Wr_En_q = '1' )then
219
        case( Reg_Sel_q )is
220 175 jshamlet
          when "00" | "01" =>
221 217 jshamlet
            Reg_Valid        <= '1';
222 244 jshamlet
            Reg_Sel          <= Reg_Sel_q(0);
223 217 jshamlet
            Reg_Data         <= Wr_Data_q;
224 175 jshamlet
          when "10" =>
225 217 jshamlet
            LCD_Contrast     <= Wr_Data_q;
226 175 jshamlet
          when "11" =>
227 217 jshamlet
            LCD_Bright       <= Wr_Data_q;
228 175 jshamlet
          when others => null;
229
        end case;
230
      end if;
231
 
232 244 jshamlet
      Rd_En_q                <= Rd_En_d;
233 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
234 244 jshamlet
      if( Rd_En_q = '1' )then
235
        case( Reg_Sel_q )is
236 175 jshamlet
          when "00" | "01" =>
237 217 jshamlet
            Rd_Data(7)       <= Tx_Ready;
238 175 jshamlet
          when "10" =>
239 217 jshamlet
            Rd_Data          <= LCD_Contrast;
240 175 jshamlet
          when "11" =>
241 217 jshamlet
            Rd_Data          <= LCD_Bright;
242 175 jshamlet
          when others => null;
243
        end case;
244
      end if;
245
    end if;
246
  end process;
247
 
248
--------------------------------------------------------------------------------
249
-- LCD and Register logic
250
--------------------------------------------------------------------------------
251
 
252 217 jshamlet
  LCD_RW                     <= '0'; -- Permanently wire the RW line low
253 175 jshamlet
 
254
  LCD_IO: process( Clock, Reset )
255
  begin
256
    if( Reset = Reset_Level )then
257 217 jshamlet
      io_state               <= INIT;
258
      init_count             <= (others => '0');
259
      io_timer               <= (others => '0');
260
      busy_timer             <= (others => '0');
261
      LCD_Data               <= (others => '0');
262
      LCD_Addr               <= '0';
263
      LCD_E                  <= '0';
264
      LCD_RS                 <= '0';
265
      LCD_D                  <= (others => '0');
266
      Tx_Ready               <= '0';
267
      Interrupt              <= '0';
268 175 jshamlet
    elsif( rising_edge(Clock) )then
269 217 jshamlet
      LCD_E                  <= '0';
270
      LCD_RS                 <= '0';
271
      LCD_D                  <= (others => '0');
272
      Tx_Ready               <= '0';
273
      Interrupt              <= '0';
274
      io_timer               <= io_timer - 1;
275
      busy_timer             <= busy_timer - uSec_Tick;
276 175 jshamlet
      case( io_state )is
277
 
278
        when INIT =>
279 217 jshamlet
          busy_timer         <= INIT_DELAY;
280
          init_count         <= (others => '1');
281
          io_state           <= BUSY_WAIT;
282 175 jshamlet
 
283
        when FN_JUMP =>
284 217 jshamlet
          io_state           <= WR_PREP;
285 175 jshamlet
          case( init_count )is
286
            when "000" =>
287 217 jshamlet
              io_state       <= IDLE;
288 175 jshamlet
            when "001" =>
289 217 jshamlet
              LCD_Addr       <= '0';
290
              LCD_Data       <= LCD_CONFIG6; -- Reset the Cursor
291 175 jshamlet
            when "010" =>
292 217 jshamlet
              LCD_Addr       <= '1';         -- Print a "*", and
293
              LCD_Data       <= LCD_CONFIG5; --  set RS to 1
294 175 jshamlet
            when "011" =>
295 217 jshamlet
              LCD_Data       <= LCD_CONFIG4; -- Entry mode
296 175 jshamlet
            when "100" =>
297 217 jshamlet
              LCD_Data       <= LCD_CONFIG3; -- Clear Display
298 175 jshamlet
            when "101" =>
299 217 jshamlet
              LCD_Data       <= LCD_CONFIG2; -- Display control
300 175 jshamlet
            when "110" | "111" =>
301 217 jshamlet
              LCD_Addr       <= '0';
302
              LCD_Data       <= LCD_CONFIG1; -- Function set
303 175 jshamlet
            when others => null;
304
          end case;
305
 
306
        when IDLE =>
307 217 jshamlet
          Tx_Ready           <= '1';
308 175 jshamlet
          if( Reg_Valid = '1' )then
309 217 jshamlet
            LCD_Addr         <= Reg_Sel;
310
            LCD_Data         <= Reg_Data;
311
            io_state         <= WR_PREP;
312 175 jshamlet
          end if;
313
 
314
        when WR_PREP =>
315 217 jshamlet
          io_timer           <= SNH_DELAY;
316
          io_state           <= WR_SETUP;
317 175 jshamlet
 
318
        when WR_SETUP =>
319 217 jshamlet
          LCD_RS             <= LCD_Addr;
320
          LCD_D              <= LCD_Data;
321
          LCD_E              <= '1';
322 175 jshamlet
          if( io_timer = 0 )then
323 217 jshamlet
            io_timer         <= SNH_DELAY;
324
            io_state         <= WR_HOLD;
325 175 jshamlet
          end if;
326
 
327
        when WR_HOLD =>
328 217 jshamlet
          LCD_RS             <= LCD_Addr;
329
          LCD_D              <= LCD_Data;
330 175 jshamlet
          if( io_timer = 0 )then
331 217 jshamlet
            LCD_E            <= '0';
332
            io_state         <= BUSY_PREP;
333 175 jshamlet
          end if;
334
 
335
        when BUSY_PREP =>
336 217 jshamlet
          busy_timer         <= BUSY_DELAY;
337 175 jshamlet
          if( LCD_Addr = '0' and LCD_Data < 4 )then
338 217 jshamlet
            busy_timer       <= CLDSP_DELAY;
339 175 jshamlet
          end if;
340 217 jshamlet
          io_state           <= BUSY_WAIT;
341 175 jshamlet
 
342
        when BUSY_WAIT =>
343
          if( busy_timer = 0 )then
344 217 jshamlet
            io_state         <= ISSUE_INT;
345 175 jshamlet
            if( init_count > 0 )then
346 217 jshamlet
              init_count     <= init_count - 1;
347
              io_state       <= FN_JUMP;
348 175 jshamlet
            end if;
349
          end if;
350
 
351
        when ISSUE_INT =>
352 217 jshamlet
          Interrupt          <= '1';
353
          io_state           <= IDLE;
354 175 jshamlet
 
355
        when others => null;
356
 
357
      end case;
358
 
359
    end if;
360
  end process;
361
 
362
--------------------------------------------------------------------------------
363
-- Contrast control logic (optional)
364
--------------------------------------------------------------------------------
365
 
366
Contrast_Disabled: if( not Use_Contrast )generate
367 217 jshamlet
  LCD_CN                     <= '0';
368 175 jshamlet
end generate;
369
 
370
Contrast_Enabled: if( Use_Contrast )generate
371
 
372 217 jshamlet
  U_CN : entity work.vdsm8
373
  generic map(
374
    Reset_Level              => Reset_Level
375
  )
376
  port map(
377
    Clock                    => Clock,
378
    Reset                    => Reset,
379
    DACin                    => LCD_Contrast,
380
    DACout                   => LCD_CN
381
  );
382 175 jshamlet
 
383
end generate;
384
 
385
--------------------------------------------------------------------------------
386
-- Backlight control logic (optional)
387
--------------------------------------------------------------------------------
388
 
389
Backlight_Disabled: if( not Use_Backlight )generate
390 217 jshamlet
  LCD_BL                     <= '0';
391 175 jshamlet
end generate;
392
 
393
Backlight_Enabled: if( Use_Backlight )generate
394
 
395 217 jshamlet
  U_BL : entity work.vdsm8
396
  generic map(
397
    Reset_Level              => Reset_Level
398
  )
399
  port map(
400
    Clock                    => Clock,
401
    Reset                    => Reset,
402
    DACin                    => LCD_Bright,
403
    DACout                   => LCD_BL
404
  );
405 175 jshamlet
 
406
end generate;
407
 
408
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.