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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_8b.vhd] - Blame information for rev 297

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1 194 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 213 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 194 jshamlet
--
24 175 jshamlet
-- VHDL Entity: o8_hd44780_8b
25
-- Description: Provides low-level access to a "standard" character LCD using
26
--               the ST/HD44780(U) control ASIC wired in full (8-bit) mode.
27 213 jshamlet
--              All low-level timing of the control signals are handled by
28
--               this module, allowing client firmware to use a simple
29
--               register interface to program the LCD panel.
30 175 jshamlet
--              Init routine initializes the display and displays a single
31
--               character to demonstrate correct function, then listens for
32
--               user data on its external interface.
33 213 jshamlet
--
34
-- Register Map
35
-- Address  Function
36
-- Offset  Bitfield Description                        Read/Write
37 262 jshamlet
-- 0x0     AAAAAAAA LCD Register Write                 (Read-Write*)
38
-- 0x1     AAAAAAAA LCD Data Write                     (Read-Write*)
39 213 jshamlet
-- 0x2     AAAAAAAA LCD Contrast                       (Read-Write)
40
-- 0x3     AAAAAAAA LCD Backlight                      (Read-Write)
41
--
42 262 jshamlet
-- Note: Reading 0x0 or 0x1 will report whether the panel is ready or not in the
43
--        MSB (bit 7). 0x00 = NOT READY / 0x80 = READY
44
--
45 213 jshamlet
--------------------------------------------------------------------------------
46
-- LCD Controller
47
--------------------------------------------------------------------------------
48
--
49
-- LCD Instruction Set
50
-- Instruction             RS  RW  D7  D6  D5  D4  D3  D2  D1  D0  Time
51
------------------------------------------------------------------------
52
-- Clear Display         | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
53
-- Return Home           | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
54
-- Entry Mode            | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S |   37uS
55
-- Display Pwr           | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B |   37uS
56
-- Cursor/Display Shift  | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x |   37uS
57
-- Function Set          | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x |   37uS
58
-- Set CGRAM Address     | 0 | 0 | 0 | 1 | A | A | A | A | A | A |   37uS
59
-- Set DDRAM Address     | 0 | 0 | 1 | A | A | A | A | A | A | A |   37uS
60 175 jshamlet
 
61 213 jshamlet
-- Notes:
62
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
63
-- S  = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
64
-- D  = Display On/Off (1 = on, 0 = off)
65
-- C  = Cursor On/Off  (1 = on, 0 = off)
66
-- B  = Cursor Blink   (1 = block cursor, 0 = underline cursor)
67
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
68
-- F  = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
69
-- N  = Number of Lines (0 = 1 lines, 1 = 2 lines)
70
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
71
-- A  = Address (see data sheet for usage)
72
--
73
-- Revision History
74
-- Author          Date     Change
75
------------------ -------- ---------------------------------------------------
76
-- Seth Henry      01/22/13 Design Start
77
-- Seth Henry      04/10/20 Code & comment cleanup
78 224 jshamlet
-- Seth Henry      04/16/20 Modified to use Open8 bus record
79 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
80 213 jshamlet
 
81 175 jshamlet
library ieee;
82
use ieee.std_logic_1164.all;
83
use ieee.std_logic_unsigned.all;
84
use ieee.std_logic_arith.all;
85
 
86
library work;
87
use work.open8_pkg.all;
88
 
89
entity o8_hd44780_8b is
90
generic(
91
  Use_Contrast          : boolean;
92
  Default_Contrast      : std_logic_vector(7 downto 0);
93
  Use_Backlight         : boolean;
94
  Default_Brightness    : std_logic_vector(7 downto 0);
95 224 jshamlet
  Clock_Frequency       : real;
96
  Address               : ADDRESS_TYPE
97 175 jshamlet
);
98
port(
99 223 jshamlet
  Open8_Bus             : in  OPEN8_BUS_TYPE;
100 244 jshamlet
  Write_Qual            : in  std_logic := '1';
101 175 jshamlet
  Rd_Data               : out DATA_TYPE;
102
  Interrupt             : out std_logic;
103
  --
104
  LCD_E                 : out std_logic;
105
  LCD_RW                : out std_logic;
106
  LCD_RS                : out std_logic;
107
  LCD_D                 : out std_logic_vector(7 downto 0);
108
  LCD_CN                : out std_logic;
109
  LCD_BL                : out std_logic
110
);
111
end entity;
112
 
113
architecture behave of o8_hd44780_8b is
114
 
115 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
116
  alias Reset                is Open8_Bus.Reset;
117
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
118
 
119 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 2)
120
                               := Address(15 downto 2);
121 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
122 244 jshamlet
  signal Addr_Match          : std_logic;
123 175 jshamlet
 
124 244 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
125
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
126
  signal Wr_En_d             : std_logic := '0';
127
  signal Wr_En_q             : std_logic := '0';
128
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
129 217 jshamlet
  signal Wr_Data_q           : DATA_TYPE := x"00";
130 244 jshamlet
  signal Rd_En_d             : std_logic := '0';
131
  signal Rd_En_q             : std_logic := '0';
132 175 jshamlet
 
133 217 jshamlet
  signal Reg_Valid           : std_logic := '0';
134
  signal Reg_Sel             : std_logic := '0';
135
  signal Reg_Data            : DATA_TYPE := x"00";
136 175 jshamlet
 
137 217 jshamlet
  signal Tx_Ready            : std_logic := '0';
138 175 jshamlet
 
139 217 jshamlet
  constant LCD_CONFIG1       : std_logic_vector(7 downto 0) := x"38"; -- Set 4-bit, 2-line mode
140
  constant LCD_CONFIG2       : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
141
  constant LCD_CONFIG3       : std_logic_vector(7 downto 0) := x"01"; -- Clear display
142
  constant LCD_CONFIG4       : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
143
  constant LCD_CONFIG5       : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
144
  constant LCD_CONFIG6       : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
145 175 jshamlet
 
146 217 jshamlet
  signal init_count          : std_logic_vector(2 downto 0) := (others => '0');
147 175 jshamlet
 
148 217 jshamlet
  constant INIT_40MS         : integer := 40000;
149
  constant INIT_BITS         : integer := ceil_log2(INIT_40MS);
150
  constant INIT_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
151
                               conv_std_logic_vector(INIT_40MS,INIT_BITS);
152 175 jshamlet
 
153
-- For "long" instructions, such as clear display and return home, we need to wait for more
154
--  than 1.52mS. Experimentally, 2mS seems to work ideally, and for init this isn't an issue
155 217 jshamlet
  constant CLDSP_2MS         : integer := 2000;
156
  constant CLDSP_DELAY       : std_logic_vector(INIT_BITS-1 downto 0) :=
157
                               conv_std_logic_vector(CLDSP_2MS,INIT_BITS);
158 175 jshamlet
 
159
 -- For some reason, we are required to wait 80uS before checking the busy flag, despite
160
 --  most instructions completing in 37uS. No clue as to why, but it works
161 217 jshamlet
  constant BUSY_50US         : integer := 50;
162
  constant BUSY_DELAY        : std_logic_vector(INIT_BITS-1 downto 0) :=
163
                               conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
164 175 jshamlet
 
165 217 jshamlet
  signal busy_timer          : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
166 175 jshamlet
 
167 224 jshamlet
  constant SNH_600NS         : integer := integer(Clock_Frequency * 0.000000600);
168 217 jshamlet
  constant SNH_BITS          : integer := ceil_log2(SNH_600NS);
169
  constant SNH_DELAY         : std_logic_vector(SNH_BITS-1 downto 0) :=
170
                               conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
171 175 jshamlet
 
172 217 jshamlet
  signal io_timer            : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');
173 175 jshamlet
 
174
  type IO_STATES is (INIT, FN_JUMP, IDLE,
175
                     WR_PREP, WR_SETUP, WR_HOLD,
176
                     BUSY_PREP, BUSY_WAIT,
177
                     ISSUE_INT );
178 217 jshamlet
  signal io_state            : IO_STATES;
179 175 jshamlet
 
180 217 jshamlet
  signal LCD_Data            : DATA_TYPE := x"00";
181
  signal LCD_Addr            : std_logic := '0';
182 175 jshamlet
 
183
--------------------------------------------------------------------------------
184
-- Backlight & Contrast signals
185
--------------------------------------------------------------------------------
186
 
187 217 jshamlet
  signal LCD_Contrast        : DATA_TYPE := x"00";
188
  signal LCD_Bright          : DATA_TYPE := x"00";
189 175 jshamlet
 
190
begin
191
 
192
--------------------------------------------------------------------------------
193
-- Open8 Register interface
194
--------------------------------------------------------------------------------
195
 
196 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
197 244 jshamlet
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
198
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
199 175 jshamlet
 
200
  io_reg: process( Clock, Reset )
201
  begin
202
    if( Reset = Reset_Level )then
203 244 jshamlet
      Reg_Sel_q              <= "00";
204
      Wr_En_q                <= '0';
205
      Wr_Data_q              <= x"00";
206
      Rd_En_q                <= '0';
207 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
208 175 jshamlet
 
209 217 jshamlet
      Reg_Valid              <= '0';
210
      Reg_Sel                <= '0';
211
      Reg_Data               <= x"00";
212 175 jshamlet
 
213 217 jshamlet
      LCD_Contrast           <= Default_Contrast;
214
      LCD_Bright             <= Default_Brightness;
215 175 jshamlet
    elsif( rising_edge( Clock ) )then
216 244 jshamlet
      Reg_Sel_q              <= Reg_Sel_d;
217 175 jshamlet
 
218 244 jshamlet
      Wr_En_q                <= Wr_En_d;
219
      Wr_Data_q              <= Wr_Data_d;
220 217 jshamlet
      Reg_Valid              <= '0';
221 244 jshamlet
      if( Wr_En_q = '1' )then
222
        case( Reg_Sel_q )is
223 175 jshamlet
          when "00" | "01" =>
224 217 jshamlet
            Reg_Valid        <= '1';
225 244 jshamlet
            Reg_Sel          <= Reg_Sel_q(0);
226 217 jshamlet
            Reg_Data         <= Wr_Data_q;
227 175 jshamlet
          when "10" =>
228 217 jshamlet
            LCD_Contrast     <= Wr_Data_q;
229 175 jshamlet
          when "11" =>
230 217 jshamlet
            LCD_Bright       <= Wr_Data_q;
231 175 jshamlet
          when others => null;
232
        end case;
233
      end if;
234
 
235 244 jshamlet
      Rd_En_q                <= Rd_En_d;
236 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
237 244 jshamlet
      if( Rd_En_q = '1' )then
238
        case( Reg_Sel_q )is
239 175 jshamlet
          when "00" | "01" =>
240 217 jshamlet
            Rd_Data(7)       <= Tx_Ready;
241 175 jshamlet
          when "10" =>
242 217 jshamlet
            Rd_Data          <= LCD_Contrast;
243 175 jshamlet
          when "11" =>
244 217 jshamlet
            Rd_Data          <= LCD_Bright;
245 175 jshamlet
          when others => null;
246
        end case;
247
      end if;
248
    end if;
249
  end process;
250
 
251
--------------------------------------------------------------------------------
252
-- LCD and Register logic
253
--------------------------------------------------------------------------------
254
 
255 217 jshamlet
  LCD_RW                     <= '0'; -- Permanently wire the RW line low
256 175 jshamlet
 
257
  LCD_IO: process( Clock, Reset )
258
  begin
259
    if( Reset = Reset_Level )then
260 217 jshamlet
      io_state               <= INIT;
261
      init_count             <= (others => '0');
262
      io_timer               <= (others => '0');
263
      busy_timer             <= (others => '0');
264
      LCD_Data               <= (others => '0');
265
      LCD_Addr               <= '0';
266
      LCD_E                  <= '0';
267
      LCD_RS                 <= '0';
268
      LCD_D                  <= (others => '0');
269
      Tx_Ready               <= '0';
270
      Interrupt              <= '0';
271 175 jshamlet
    elsif( rising_edge(Clock) )then
272 217 jshamlet
      LCD_E                  <= '0';
273
      LCD_RS                 <= '0';
274
      LCD_D                  <= (others => '0');
275
      Tx_Ready               <= '0';
276
      Interrupt              <= '0';
277
      io_timer               <= io_timer - 1;
278
      busy_timer             <= busy_timer - uSec_Tick;
279 175 jshamlet
      case( io_state )is
280
 
281
        when INIT =>
282 217 jshamlet
          busy_timer         <= INIT_DELAY;
283
          init_count         <= (others => '1');
284
          io_state           <= BUSY_WAIT;
285 175 jshamlet
 
286
        when FN_JUMP =>
287 217 jshamlet
          io_state           <= WR_PREP;
288 175 jshamlet
          case( init_count )is
289
            when "000" =>
290 217 jshamlet
              io_state       <= IDLE;
291 175 jshamlet
            when "001" =>
292 217 jshamlet
              LCD_Addr       <= '0';
293
              LCD_Data       <= LCD_CONFIG6; -- Reset the Cursor
294 175 jshamlet
            when "010" =>
295 217 jshamlet
              LCD_Addr       <= '1';         -- Print a "*", and
296
              LCD_Data       <= LCD_CONFIG5; --  set RS to 1
297 175 jshamlet
            when "011" =>
298 217 jshamlet
              LCD_Data       <= LCD_CONFIG4; -- Entry mode
299 175 jshamlet
            when "100" =>
300 217 jshamlet
              LCD_Data       <= LCD_CONFIG3; -- Clear Display
301 175 jshamlet
            when "101" =>
302 217 jshamlet
              LCD_Data       <= LCD_CONFIG2; -- Display control
303 175 jshamlet
            when "110" | "111" =>
304 217 jshamlet
              LCD_Addr       <= '0';
305
              LCD_Data       <= LCD_CONFIG1; -- Function set
306 175 jshamlet
            when others => null;
307
          end case;
308
 
309
        when IDLE =>
310 217 jshamlet
          Tx_Ready           <= '1';
311 175 jshamlet
          if( Reg_Valid = '1' )then
312 217 jshamlet
            LCD_Addr         <= Reg_Sel;
313
            LCD_Data         <= Reg_Data;
314
            io_state         <= WR_PREP;
315 175 jshamlet
          end if;
316
 
317
        when WR_PREP =>
318 217 jshamlet
          io_timer           <= SNH_DELAY;
319
          io_state           <= WR_SETUP;
320 175 jshamlet
 
321
        when WR_SETUP =>
322 217 jshamlet
          LCD_RS             <= LCD_Addr;
323
          LCD_D              <= LCD_Data;
324
          LCD_E              <= '1';
325 175 jshamlet
          if( io_timer = 0 )then
326 217 jshamlet
            io_timer         <= SNH_DELAY;
327
            io_state         <= WR_HOLD;
328 175 jshamlet
          end if;
329
 
330
        when WR_HOLD =>
331 217 jshamlet
          LCD_RS             <= LCD_Addr;
332
          LCD_D              <= LCD_Data;
333 175 jshamlet
          if( io_timer = 0 )then
334 217 jshamlet
            LCD_E            <= '0';
335
            io_state         <= BUSY_PREP;
336 175 jshamlet
          end if;
337
 
338
        when BUSY_PREP =>
339 217 jshamlet
          busy_timer         <= BUSY_DELAY;
340 175 jshamlet
          if( LCD_Addr = '0' and LCD_Data < 4 )then
341 217 jshamlet
            busy_timer       <= CLDSP_DELAY;
342 175 jshamlet
          end if;
343 217 jshamlet
          io_state           <= BUSY_WAIT;
344 175 jshamlet
 
345
        when BUSY_WAIT =>
346
          if( busy_timer = 0 )then
347 217 jshamlet
            io_state         <= ISSUE_INT;
348 175 jshamlet
            if( init_count > 0 )then
349 217 jshamlet
              init_count     <= init_count - 1;
350
              io_state       <= FN_JUMP;
351 175 jshamlet
            end if;
352
          end if;
353
 
354
        when ISSUE_INT =>
355 217 jshamlet
          Interrupt          <= '1';
356
          io_state           <= IDLE;
357 175 jshamlet
 
358
        when others => null;
359
 
360
      end case;
361
 
362
    end if;
363
  end process;
364
 
365
--------------------------------------------------------------------------------
366
-- Contrast control logic (optional)
367
--------------------------------------------------------------------------------
368
 
369
Contrast_Disabled: if( not Use_Contrast )generate
370 217 jshamlet
  LCD_CN                     <= '0';
371 175 jshamlet
end generate;
372
 
373
Contrast_Enabled: if( Use_Contrast )generate
374
 
375 217 jshamlet
  U_CN : entity work.vdsm8
376
  generic map(
377
    Reset_Level              => Reset_Level
378
  )
379
  port map(
380
    Clock                    => Clock,
381
    Reset                    => Reset,
382
    DACin                    => LCD_Contrast,
383
    DACout                   => LCD_CN
384
  );
385 175 jshamlet
 
386
end generate;
387
 
388
--------------------------------------------------------------------------------
389
-- Backlight control logic (optional)
390
--------------------------------------------------------------------------------
391
 
392
Backlight_Disabled: if( not Use_Backlight )generate
393 217 jshamlet
  LCD_BL                     <= '0';
394 175 jshamlet
end generate;
395
 
396
Backlight_Enabled: if( Use_Backlight )generate
397
 
398 217 jshamlet
  U_BL : entity work.vdsm8
399
  generic map(
400
    Reset_Level              => Reset_Level
401
  )
402
  port map(
403
    Clock                    => Clock,
404
    Reset                    => Reset,
405
    DACin                    => LCD_Bright,
406
    DACout                   => LCD_BL
407
  );
408 175 jshamlet
 
409
end generate;
410
 
411
end architecture;

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