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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_int_mgr.vhd] - Blame information for rev 301

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1 245 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_int_mgr
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-- Description:  Provides an 8-bit microsecond resolution timer for generating
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--            :   periodic interrupts for the Open8 CPU as well as providing a
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--            :   second level interrupt manager for I/O interrupts
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--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x00  AAAAAAAA PIT Timer Interval (0 = disabled)    (RW)
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--   0x01  AAAAAAAA External Interrupt Mask              (RW)
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--   0x02  AAAAAAAA Pending External Interrupts*         (RW)
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--   0x03  A------- Interrupt Requested (write to clear) (RW)
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--
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-- Note: Each bit in the pending register is individually clearable by writing
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--        a '1' to it, allowing interrupts to be cleared individually
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      05/21/20 Design Start
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library ieee;
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use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_int_mgr is
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generic(
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  Default_Int_Mask           : DATA_TYPE := x"00";
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  Interrupts                 : in  INTERRUPT_BUNDLE := x"00";
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  Rd_Data                    : out DATA_TYPE;
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  PIT_Interrupt              : out std_logic;
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  EXT_Interrupt              : out std_logic
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);
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end entity;
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architecture behave of o8_int_mgr is
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  alias  Clock               is Open8_Bus.Clock;
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  alias  Reset               is Open8_Bus.Reset;
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  alias  uSec_Tick           is Open8_Bus.uSec_Tick;
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  alias  CPU_ISR_En          is Open8_Bus.GP_Flags(EXT_ISR);
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  alias  CPU_Wr_En           is Open8_Bus.Wr_En;
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  alias  CPU_Rd_En           is Open8_Bus.Rd_En;
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  constant User_Addr         : std_logic_vector(15 downto 2) :=
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                                Address(15 downto 2);
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
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  signal Addr_Match          : std_logic := '0';
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  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
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  signal Reg_Sel_q           : std_logic_vector(1 downto 0);
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  signal Wr_En_d             : std_logic;
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  signal Wr_En_q             : std_logic := '0';
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  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
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  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal Rd_En_d               : std_logic := '0';
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  signal Rd_En_q             : std_logic := '0';
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  signal Interval            : DATA_TYPE := x"00";
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  signal Update_Interval     : std_logic;
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  signal Timer_Cnt           : DATA_TYPE := x"00";
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  signal Int_Mask            : DATA_TYPE := x"00";
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  signal Clear_Pending       : DATA_TYPE := x"00";
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  signal Ack_IO_Ints         : std_logic;
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  signal Pending             : DATA_TYPE := x"00";
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  signal Pending_q           : DATA_TYPE := x"00";
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  signal Pending_RE          : DATA_TYPE := x"00";
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  signal IO_Int_Pending      : std_logic;
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Wr_En_d                    <= Addr_Match and CPU_Wr_En and CPU_ISR_En;
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  Rd_En_d                    <= Addr_Match and CPU_Rd_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Reg_Sel_q              <= (others => '0');
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      Wr_En_q                <= '0';
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      Wr_Data_q              <= x"00";
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      Rd_En_q                <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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      Interval               <= x"00";
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      Update_Interval        <= '0';
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      Int_Mask               <= Default_Int_Mask;
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      Clear_Pending          <= x"00";
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      Ack_IO_Ints            <= '0';
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    elsif( rising_edge( Clock ) )then
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      Reg_Sel_q              <= Reg_Sel_d;
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      Wr_En_q                <= Wr_En_d;
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      Wr_Data_q              <= Wr_Data_d;
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      Update_Interval        <= Wr_En_q;
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      Clear_Pending          <= x"00";
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      Ack_IO_Ints            <= '0';
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      if( Wr_En_q = '1' )then
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        case( Reg_Sel_q )is
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          when "00" =>
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            Interval         <= Wr_Data_q;
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          when "01" =>
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            Int_Mask         <= Wr_Data_q;
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          when "10" =>
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            Clear_Pending    <= Wr_Data_q;
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          when "11" =>
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            Ack_IO_Ints      <= '1';
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          when others =>
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            null;
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        end case;
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      end if;
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      Rd_Data                <= (others => '0');
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      Rd_En_q                <= Rd_En_d;
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      if( Rd_En_q = '1' )then
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        case( Reg_Sel_q )is
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          when "00" =>
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            Rd_Data          <= Interval;
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          when "01" =>
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            Rd_Data          <= Int_Mask;
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          when "10" =>
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            Rd_Data          <= Pending;
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          when "11" =>
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            Rd_Data          <= IO_Int_Pending & "0000000";
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          when others =>
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            null;
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        end case;
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      end if;
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    end if;
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  end process;
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  Interval_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Timer_Cnt              <= x"00";
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      PIT_Interrupt          <= '0';
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    elsif( rising_edge(Clock) )then
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      PIT_Interrupt              <= '0';
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      Timer_Cnt              <= Timer_Cnt - uSec_Tick;
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      if( Update_Interval = '1' )then
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        Timer_Cnt            <= Interval;
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      elsif( or_reduce(Timer_Cnt) = '0' )then
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        Timer_Cnt            <= Interval;
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        PIT_Interrupt        <= or_reduce(Interval); -- Only trigger on Int > 0
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      end if;
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    end if;
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  end process;
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  Interrupt_proc: process( Clock, Reset )
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    variable i               : integer := 0;
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  begin
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    if( Reset = Reset_Level )then
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      Pending                <= x"00";
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      Pending_q              <= x"00";
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      Pending_RE             <= x"00";
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      IO_Int_Pending         <= '0';
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      EXT_Interrupt          <= '0';
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    elsif( rising_edge(Clock) )then
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      for i in 0 to 7 loop
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        if( Interrupts(i) = '1' and Int_Mask(i) = '1' )then
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          Pending(i)         <= '1';
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        elsif( Clear_Pending(i) = '1' )then
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          Pending(i)         <= '0';
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        end if;
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        Pending_q(i)         <= Pending(i);
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        Pending_RE(i)        <= Pending(i) and not Pending_q(i);
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      end loop;
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      EXT_Interrupt          <= '0';
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      if( or_reduce(Pending_RE) = '1' and IO_Int_Pending = '0' )then
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        IO_Int_Pending       <= '1';
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        EXT_Interrupt        <= '1';
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      elsif( Ack_IO_Ints = '1' )then
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        IO_Int_Pending       <= '0';
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      end if;
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    end if;
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  end process;
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end architecture;

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