OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_interval_meas.vhd] - Blame information for rev 287

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 259 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_interval_meas
25
-- Description:  Provides an settable resolution counter for measuring
26
--            :   events
27
-- Register Map:
28
-- Offset  Bitfield Description                        Read/Write
29
--   0x00  AAAAAAAA Captured Interval Byte 0              (RW*)
30
--   0x01  AAAAAAAA Captured Interval Byte 1              (RW*)
31
--
32
-- Notes      :  Writing to either register will clear the timer
33
--
34
-- Revision History
35
-- Author          Date     Change
36
------------------ -------- ---------------------------------------------------
37
-- Seth Henry      06/11/20 Design Start
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
  use ieee.std_logic_unsigned.all;
42
  use ieee.std_logic_arith.all;
43
  use ieee.std_logic_misc.all;
44
 
45
library work;
46
  use work.open8_pkg.all;
47
 
48
entity o8_interval_meas is
49
generic(
50
  Clock_Divide               : integer := 12;
51
  Address                    : ADDRESS_TYPE
52
);
53
port(
54
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
55
  Write_Qual                 : in  std_logic := '1';
56
  Rd_Data                    : out DATA_TYPE;
57
  Interrupt                  : out std_logic;
58
  Trigger_Reset              : in  std_logic := '0';
59
  Trigger_Capture            : in  std_logic
60
);
61
end entity;
62
 
63
architecture behave of o8_interval_meas is
64
 
65
  alias Clock                is Open8_Bus.Clock;
66
  alias Reset                is Open8_Bus.Reset;
67
 
68
  constant User_Addr         : std_logic_vector(15 downto 1) :=
69
                                Address(15 downto 1);
70
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
71
  signal Addr_Match          : std_logic := '0';
72
 
73
  alias  Reg_Sel_d           is Open8_Bus.Address(0);
74
  signal Reg_Sel_q           : std_logic := '0';
75
  signal Wr_En_d             : std_logic := '0';
76
  signal Wr_En_q             : std_logic := '0';
77
  signal Rd_En_d             : std_logic := '0';
78
  signal Rd_En_q             : std_logic := '0';
79
 
80
  signal Trig_Reset_SR       : std_logic_vector(2 downto 0);
81
  signal Trig_Reset_RE       : std_logic;
82
  signal Trig_Capture_SR     : std_logic_vector(2 downto 0);
83
  signal Trig_Capture_RE     : std_logic;
84
 
85
  constant DLY_VAL           : integer := Clock_Divide;
86
  constant DLY_WDT           : integer := ceil_log2(DLY_VAL - 1);
87
  constant DLY_INTV          : std_logic_vector :=
88
                                conv_std_logic_vector( DLY_VAL - 1, DLY_WDT);
89
  signal Intv_Cntr           : std_logic_vector( DLY_WDT - 1 downto 0 );
90
  signal Intv_Tick           : std_logic := '0';
91
 
92
  signal Timer_Latch         : std_logic_vector(15 downto 0) := x"0000";
93
  alias  Timer_Latch_B0      is Timer_Latch(7 downto 0);
94
  alias  Timer_Latch_B1      is Timer_Latch(15 downto 8);
95
 
96
  signal Timer_Counter       : std_logic_vector(15 downto 0) := x"0000";
97
begin
98
 
99
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
100
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
101
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
102
 
103
  io_reg: process( Clock, Reset )
104
  begin
105
    if( Reset = Reset_Level )then
106
      Reg_Sel_q              <= '0';
107
      Wr_En_q                <= '0';
108
      Rd_En_q                <= '0';
109
      Rd_Data                <= OPEN8_NULLBUS;
110
      Interrupt              <= '0';
111
    elsif( rising_edge( Clock ) )then
112
      Reg_Sel_q              <= Reg_Sel_d;
113
 
114
      Wr_En_q                <= Wr_En_d and Write_Qual;
115
 
116
      Rd_Data                <= OPEN8_NULLBUS;
117
      Rd_En_q                <= Rd_En_d;
118
 
119
      if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
120
        Rd_Data              <= Timer_Latch_B0;
121
      end if;
122
 
123
      if( Rd_En_q = '1' and Reg_Sel_q = '1' )then
124
        Rd_Data              <= Timer_Latch_B1;
125
      end if;
126
 
127
      Interrupt              <= Trig_Capture_RE;
128
 
129
    end if;
130
  end process;
131
 
132
  Capture_proc: process( Clock, Reset )
133
  begin
134
    if( Reset = Reset_Level )then
135
      Trig_Reset_SR          <= (others => '0');
136
      Trig_Reset_RE          <= '0';
137
      Trig_Capture_SR        <= (others => '0');
138
      Trig_Capture_RE        <= '0';
139
      Intv_Cntr              <= (others => '0');
140
      Intv_Tick              <= '0';
141
      Timer_Counter          <= (others => '0');
142
      Timer_Latch            <= (others => '0');
143
    elsif( rising_edge(Clock) )then
144
      Trig_Reset_SR          <= Trig_Reset_SR(1 downto 0) & Trigger_Reset;
145
      Trig_Reset_RE          <= Trig_Reset_SR(1) and not Trig_Reset_SR(2);
146
      Trig_Capture_SR        <= Trig_Capture_SR(1 downto 0) & Trigger_Capture;
147
      Trig_Capture_RE        <= Trig_Capture_SR(1) and not Trig_Capture_SR(2);
148
 
149
      Intv_Cntr              <= Intv_Cntr - 1;
150
      Intv_Tick              <= '0';
151
      if( Intv_Cntr = 0 )then
152
        Intv_Cntr            <= DLY_INTV;
153
        Intv_Tick            <= '1';
154
      end if;
155
 
156
      Timer_Counter          <= Timer_Counter + Intv_Tick;
157
      if( Trig_Reset_RE = '1' or Wr_En_q = '1' )then
158
        Timer_Counter        <= (others => '0');
159
      elsif( and_reduce(Timer_Counter) = '1' )then
160
        Timer_Counter        <= Timer_Counter;
161
      end if;
162
 
163
      if( Wr_En_q = '1' )then
164
        Timer_Latch          <= (others => '0');
165
      elsif( Trig_Capture_RE = '1' )then
166
        Timer_Latch          <= Timer_Counter;
167
      end if;
168
 
169
    end if;
170
  end process;
171
 
172
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.