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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_interval_meas.vhd] - Blame information for rev 301

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Line No. Rev Author Line
1 259 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_interval_meas
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-- Description:  Provides an settable resolution counter for measuring
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--            :   events
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x00  AAAAAAAA Captured Interval Byte 0              (RW*)
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--   0x01  AAAAAAAA Captured Interval Byte 1              (RW*)
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--
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-- Notes      :  Writing to either register will clear the timer
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      06/11/20 Design Start
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library ieee;
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use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_interval_meas is
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generic(
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  Clock_Divide               : integer := 12;
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  Write_Qual                 : in  std_logic := '1';
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  Rd_Data                    : out DATA_TYPE;
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  Interrupt                  : out std_logic;
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  Trigger_Reset              : in  std_logic := '0';
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  Trigger_Capture            : in  std_logic
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);
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end entity;
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architecture behave of o8_interval_meas is
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  alias Clock                is Open8_Bus.Clock;
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  alias Reset                is Open8_Bus.Reset;
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  constant User_Addr         : std_logic_vector(15 downto 1) :=
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                                Address(15 downto 1);
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
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  signal Addr_Match          : std_logic := '0';
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  alias  Reg_Sel_d           is Open8_Bus.Address(0);
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  signal Reg_Sel_q           : std_logic := '0';
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  signal Wr_En_d             : std_logic := '0';
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  signal Wr_En_q             : std_logic := '0';
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  signal Rd_En_d             : std_logic := '0';
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  signal Rd_En_q             : std_logic := '0';
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  signal Trig_Reset_SR       : std_logic_vector(2 downto 0);
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  signal Trig_Reset_RE       : std_logic;
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  signal Trig_Capture_SR     : std_logic_vector(2 downto 0);
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  signal Trig_Capture_RE     : std_logic;
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  constant DLY_VAL           : integer := Clock_Divide;
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  constant DLY_WDT           : integer := ceil_log2(DLY_VAL - 1);
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  constant DLY_INTV          : std_logic_vector :=
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                                conv_std_logic_vector( DLY_VAL - 1, DLY_WDT);
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  signal Intv_Cntr           : std_logic_vector( DLY_WDT - 1 downto 0 );
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  signal Intv_Tick           : std_logic := '0';
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  signal Timer_Latch         : std_logic_vector(15 downto 0) := x"0000";
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  alias  Timer_Latch_B0      is Timer_Latch(7 downto 0);
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  alias  Timer_Latch_B1      is Timer_Latch(15 downto 8);
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  signal Timer_Counter       : std_logic_vector(15 downto 0) := x"0000";
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
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  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Reg_Sel_q              <= '0';
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      Wr_En_q                <= '0';
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      Rd_En_q                <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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      Interrupt              <= '0';
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    elsif( rising_edge( Clock ) )then
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      Reg_Sel_q              <= Reg_Sel_d;
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      Wr_En_q                <= Wr_En_d and Write_Qual;
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      Rd_Data                <= OPEN8_NULLBUS;
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      Rd_En_q                <= Rd_En_d;
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      if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
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        Rd_Data              <= Timer_Latch_B0;
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      end if;
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      if( Rd_En_q = '1' and Reg_Sel_q = '1' )then
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        Rd_Data              <= Timer_Latch_B1;
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      end if;
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      Interrupt              <= Trig_Capture_RE;
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    end if;
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  end process;
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  Capture_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Trig_Reset_SR          <= (others => '0');
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      Trig_Reset_RE          <= '0';
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      Trig_Capture_SR        <= (others => '0');
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      Trig_Capture_RE        <= '0';
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      Intv_Cntr              <= (others => '0');
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      Intv_Tick              <= '0';
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      Timer_Counter          <= (others => '0');
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      Timer_Latch            <= (others => '0');
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    elsif( rising_edge(Clock) )then
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      Trig_Reset_SR          <= Trig_Reset_SR(1 downto 0) & Trigger_Reset;
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      Trig_Reset_RE          <= Trig_Reset_SR(1) and not Trig_Reset_SR(2);
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      Trig_Capture_SR        <= Trig_Capture_SR(1 downto 0) & Trigger_Capture;
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      Trig_Capture_RE        <= Trig_Capture_SR(1) and not Trig_Capture_SR(2);
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      Intv_Cntr              <= Intv_Cntr - 1;
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      Intv_Tick              <= '0';
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      if( Intv_Cntr = 0 )then
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        Intv_Cntr            <= DLY_INTV;
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        Intv_Tick            <= '1';
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      end if;
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      Timer_Counter          <= Timer_Counter + Intv_Tick;
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      if( Trig_Reset_RE = '1' or Wr_En_q = '1' )then
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        Timer_Counter        <= (others => '0');
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      elsif( and_reduce(Timer_Counter) = '1' )then
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        Timer_Counter        <= Timer_Counter;
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      end if;
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      if( Wr_En_q = '1' )then
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        Timer_Latch          <= (others => '0');
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      elsif( Trig_Capture_RE = '1' )then
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        Timer_Latch          <= Timer_Counter;
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      end if;
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    end if;
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  end process;
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end architecture;

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