OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_lfsr32.vhd] - Blame information for rev 214

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 214 jshamlet
-- Copyright (c)2018, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_register
25
-- Description:  Provides a byte of pseudo-random data on every read
26
--
27
-- Register Map:
28
-- Offset  Bitfield Description                        Read/Write
29
--   0x00  AAAAAAAA Data output                          (RW)
30
--
31
-- Revision History
32
-- Author          Date     Change
33
------------------ -------- ---------------------------------------------------
34
-- Seth Henry      04/25/18 Design Start
35
-- Seth Henry      04/10/20 Code cleanup and comments
36
 
37
library ieee;
38
  use ieee.std_logic_1164.all;
39
  use ieee.std_logic_misc.all;
40
 
41
library work;
42
  use work.open8_pkg.all;
43
 
44
entity o8_lfsr32 is
45
generic(
46
  Init_Seed             : std_logic_vector(31 downto 0) := x"CAFEBABE";
47
  Reset_Level           : std_logic;
48
  Address               : ADDRESS_TYPE
49
);
50
port(
51
  Clock                 : in  std_logic;
52
  Reset                 : in  std_logic;
53
  --
54
  Bus_Address           : in  ADDRESS_TYPE;
55
  Rd_Enable             : in  std_logic;
56
  Rd_Data               : out DATA_TYPE
57
);
58
end entity;
59
 
60
architecture behave of o8_lfsr32 is
61
 
62
  constant User_Addr    : std_logic_vector(15 downto 1)
63
                          := Address(15 downto 1);
64
  alias  Comp_Addr      is Bus_Address(15 downto 1);
65
  alias  Reg_Sel        is Bus_Address(0);
66
  signal Reg_Sel_q      : std_logic := '0';
67
  signal Addr_Match     : std_logic := '0';
68
  signal Rd_En          : std_logic := '0';
69
 
70
  signal d0             : std_logic := '0';
71
  signal lfsr           : std_logic_vector(31 downto 0) := x"00000000";
72
  signal lfsr_q         : std_logic_vector(31 downto 0) := x"00000000";
73
 
74
begin
75
 
76
  Addr_Match            <= Rd_Enable when Comp_Addr = User_Addr else '0';
77
  d0                    <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
78
 
79
  lfsr_proc: process( Clock, Reset )
80
  begin
81
    if( Reset = Reset_Level )then
82
      Reg_Sel_q         <= '0';
83
      Rd_En             <= '0';
84
      Rd_Data           <= x"00";
85
      lfsr              <= Init_Seed;
86
      lfsr_q            <= x"00000000";
87
    elsif( rising_edge(Clock) )then
88
      Rd_Data           <= x"00";
89
      Reg_Sel_q         <= Reg_Sel;
90
      Rd_En             <= Addr_Match;
91
      if( Rd_En = '1' )then
92
        Rd_Data         <= lfsr_q(31 downto 24);
93
        lfsr_q          <= lfsr_q(23 downto 0) & x"00";
94
        if( Reg_Sel_q = '1' )then
95
          Rd_Data       <= lfsr_q(31) & "0000000";
96
          lfsr_q        <= lfsr_q(30 downto 0) & '0';
97
        end if;
98
      end if;
99
 
100
      if( or_reduce(lfsr_q) = '0' )then
101
        lfsr_q          <= lfsr;
102
        lfsr            <= lfsr(30 downto 0) & d0;
103
      end if;
104
    end if;
105
  end process;
106
 
107
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.