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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_max7221.vhd] - Blame information for rev 193

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Line No. Rev Author Line
1 191 jshamlet
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_max7221 is
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generic(
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  Bit_Rate              : real := 5000000.0;
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  Sys_Freq              : real;
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  Reset_Level           : std_logic;
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  Address               : ADDRESS_TYPE
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);
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port(
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  Clock                 : in  std_logic;
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  Reset                 : in  std_logic;
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  --
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  Bus_Address           : in  ADDRESS_TYPE;
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  Wr_Enable             : in  std_logic;
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  Wr_Data               : in  DATA_TYPE;
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  --
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  Mx_Data               : out std_logic;
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  Mx_Clock              : out std_logic;
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  MX_LDCSn              : out std_logic
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);
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end entity;
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architecture behave of o8_max7221 is
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  signal FIFO_Reset     : std_logic;
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  constant User_Addr    : std_logic_vector(15 downto 4) := Address(15 downto 4);
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  alias  Comp_Addr      is Bus_Address(15 downto 4);
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  signal FIFO_Wr_En     : std_logic;
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  signal FIFO_Wr_Data   : std_logic_vector(11 downto 0);
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  signal FIFO_Rd_En     : std_logic;
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  signal FIFO_Empty     : std_logic;
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  signal FIFO_Rd_Data   : std_logic_vector(11 downto 0);
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  type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
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  signal TX_Ctrl        : TX_CTRL_STATES;
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  signal TX_En          : std_logic;
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  signal TX_Idle        : std_logic;
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  constant BAUD_DLY_VAL : integer := integer((Sys_Freq / Bit_Rate) / 2.0 );
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  constant BAUD_DLY_WDT : integer := ceil_log2(BAUD_DLY_VAL - 1);
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  constant BAUD_DLY     : std_logic_vector :=
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                           conv_std_logic_vector(BAUD_DLY_VAL - 1, BAUD_DLY_WDT);
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  signal Baud_Cntr      : std_logic_vector( BAUD_DLY_WDT - 1 downto 0 )
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                          := (others => '0');
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  signal Baud_Tick      : std_logic;
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  type IO_STATES is ( IDLE, SYNC_CLK, SCLK_L, SCLK_H, ADV_BIT, DONE );
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  signal io_state       : IO_STATES;
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  signal bit_cntr       : std_logic_vector(3 downto 0);
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  signal tx_buffer      : std_logic_vector(15 downto 0);
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begin
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  FIFO_Wr_En            <= Wr_Enable when Comp_Addr = User_Addr else '0';
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  FIFO_Wr_Data          <= Bus_Address(3 downto 0) & Wr_Data;
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  FIFO_Reset            <= Reset when Reset_Level = '1' else (not Reset);
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  U_FIFO : entity work.o8_max7221_fifo
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  port map(
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    aclr                => FIFO_Reset,
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    clock               => Clock,
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    data                => FIFO_Wr_Data,
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    rdreq               => FIFO_Rd_En,
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    wrreq               => FIFO_Wr_En,
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    empty               => FIFO_Empty,
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    q                   => FIFO_Rd_Data
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  );
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  tx_FSM: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      TX_Ctrl          <= IDLE;
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      TX_En            <= '0';
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      FIFO_Rd_En       <= '0';
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    elsif( rising_edge(Clock) )then
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      TX_En            <= '0';
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      FIFO_Rd_En       <= '0';
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      case( TX_Ctrl )is
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        when IDLE =>
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          if( FIFO_Empty = '0' )then
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            FIFO_Rd_En  <= '1';
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            TX_Ctrl     <= TX_BYTE;
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          end if;
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        when TX_BYTE =>
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          TX_En         <= '1';
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          TX_Ctrl       <= TX_START;
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        when TX_START =>
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          if( TX_Idle = '0' )then
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            TX_Ctrl     <= TX_WAIT;
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          end if;
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        when TX_WAIT =>
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          if( TX_Idle = '1' )then
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            TX_Ctrl     <= IDLE;
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          end if;
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        when others => null;
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      end case;
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    end if;
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  end process;
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  Baud_Rate_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Baud_Cntr         <= (others => '0');
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      Baud_Tick         <= '0';
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    elsif( rising_edge( Clock ) )then
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      Baud_Cntr         <= Baud_Cntr - 1;
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      Baud_Tick         <= nor_reduce(Baud_Cntr);
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      if( Baud_Cntr = 0 )then
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        Baud_Cntr       <= BAUD_DLY;
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      end if;
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    end if;
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  end process;
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  io_FSM: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      io_state          <= IDLE;
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      bit_cntr          <= (others => '0');
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      tx_buffer         <= (others => '0');
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      TX_Idle           <= '0';
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      Mx_Clock          <= '0';
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      Mx_Data           <= '0';
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      MX_LDCSn          <= '0';
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    elsif( rising_edge(Clock) )then
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      TX_Idle           <= '0';
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      Mx_Clock          <= '0';
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      case( io_state )is
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        when IDLE =>
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          Mx_Data       <= '0';
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          MX_LDCSn      <= '1';
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          TX_Idle       <= '1';
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          if( TX_En = '1' )then
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            tx_buffer   <= "0000" & FIFO_Rd_Data;
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            bit_cntr    <= (others => '1');
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            io_state    <= SYNC_CLK;
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          end if;
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        when SYNC_CLK =>
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          if( Baud_Tick = '1' )then
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            io_state    <= SCLK_L;
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          end if;
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        when SCLK_L =>
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          MX_LDCSn      <= '0';
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          Mx_Data       <= tx_buffer(conv_integer(bit_cntr));
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          if( Baud_Tick = '1' )then
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            io_state    <= SCLK_H;
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          end if;
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        when SCLK_H =>
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          Mx_Clock      <= '1';
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          if( Baud_Tick = '1' )then
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            bit_cntr    <= bit_cntr - 1;
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            io_state    <= ADV_BIT;
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          end if;
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        when ADV_BIT =>
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          io_state      <= SCLK_L;
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          if( and_reduce(bit_cntr) = '1' )then
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            io_state    <= DONE;
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          end if;
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        when DONE =>
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          Mx_Data       <= '0';
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          if( Baud_Tick = '1' )then
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            io_state    <= IDLE;
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          end if;
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        when others => null;
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      end case;
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    end if;
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  end process;
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end architecture;

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