OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_pwm_adc.vhd] - Blame information for rev 293

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 241 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
22
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Entity: pwm_adc
25
-- Description: Integrates a PWM input to return the approximate duty cycle
26
--              Uses a 1kB block ram as storage for a rolling integrator that
27
--               acts as a simple successive-approximation ADC.
28
--
29
-- Revision History
30
-- Author          Date     Change
31
------------------ -------- ---------------------------------------------------
32
-- Seth Henry      05/07/20 Design Start
33
 
34
library ieee;
35
  use ieee.std_logic_1164.all;
36
  use ieee.std_logic_unsigned.all;
37
 
38
library work;
39
  use work.open8_pkg.all;
40
 
41
entity o8_pwm_adc is
42
generic(
43
  Address                    : ADDRESS_TYPE
44
);
45
port(
46
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
47
  Rd_Data                    : out DATA_TYPE;
48
  --
49
  PWM_In                     : in  std_logic
50
);
51
end entity;
52
 
53
architecture behave of o8_pwm_adc is
54
 
55
  alias Clock                is Open8_Bus.Clock;
56
  alias Reset                is Open8_Bus.Reset;
57
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
58
 
59
  constant User_Addr         : std_logic_vector(15 downto 0) := Address(15 downto 0);
60
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
61
 
62
  signal Addr_Match          : std_logic := '0';
63 244 jshamlet
  signal Rd_En_d             : std_logic := '0';
64
  signal Rd_En_q             : std_logic := '0';
65 241 jshamlet
 
66
  signal Sample              : DATA_TYPE := x"00";
67
  signal RAM_Addr            : std_logic_vector(9 downto 0) := (others => '0');
68
  signal RAM_Data            : DATA_TYPE := x"00";
69
  signal Accumulator         : std_logic_vector(17 downto 0) := (others => '0');
70
  signal Average             : DATA_TYPE := x"00";
71
begin
72
 
73 244 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
74
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
75 241 jshamlet
 
76
  io_reg: process( Clock, Reset )
77
  begin
78
    if( Reset = Reset_Level )then
79 244 jshamlet
      Rd_En_q                <= '0';
80 241 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
81
 
82
    elsif( rising_edge( Clock ) )then
83
 
84 244 jshamlet
      Rd_En_q                <= Rd_En_d;
85 241 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
86 244 jshamlet
      if( Rd_En_q = '1' )then
87 241 jshamlet
        Rd_Data              <= Average;
88
      end if;
89
    end if;
90
  end process;
91
 
92
  -- PWM input is binary, so the sample swings between 0x00 and 0xFF
93
  Sample                     <= (others => PWM_In);
94
 
95
  U_DP : entity work.o8_pwm_adc_ram
96
  port map(
97
                address                  => RAM_Addr,
98
                clock                    => Clock,
99
                data                     => Sample,
100
                wren                     => '1',
101
                q                        => RAM_Data
102
        );
103
 
104
  ADC_proc: process( Clock, Reset )
105
  begin
106
    if( Reset = Reset_Level )then
107
      RAM_Addr               <= (others => '0');
108
      Accumulator            <= (others => '0');
109
      Average                <= (others => '0');
110
    elsif( rising_edge(Clock) )then
111
      RAM_Addr               <= RAM_Addr + 1;
112
      Accumulator            <= Accumulator + ("0000000000" & RAM_Data);
113
      if( RAM_Addr = 0 )then
114
        Accumulator          <= (others => '0');
115
        Average              <= Accumulator(17 downto 10);
116
      end if;
117
    end if;
118
  end process;
119
 
120
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.