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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ram_1k.vhd] - Blame information for rev 217

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-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_ram_1k
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-- Description:  Provides a wrapper layer for a 1kx8 RAM model
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_ram_1k is
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generic(
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  Reset_Level                : std_logic;
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Clock                      : in  std_logic;
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  Reset                      : in  std_logic;
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  --
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  Bus_Address                : in  ADDRESS_TYPE;
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  Wr_Enable                  : in  std_logic;
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  Wr_Data                    : in  DATA_TYPE;
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  Rd_Enable                  : in  std_logic;
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  Rd_Data                    : out DATA_TYPE
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);
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end entity;
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architecture behave of o8_ram_1k is
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  constant User_Addr         : std_logic_vector(15 downto 10)
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                               := Address(15 downto 10);
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  alias Comp_Addr            is Bus_Address(15 downto 10);
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  alias RAM_Addr             is Bus_Address(9 downto 0);
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  signal Addr_Match          : std_logic := '0';
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  signal Wr_En               : std_logic := '0';
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  signal Rd_En               : std_logic := '0';
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  signal Rd_Data_i           : DATA_TYPE := OPEN8_NULLBUS;
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begin
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  -- This decode needs to happen immediately, to give the RAM a chance to
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  --  do the lookup before we have to set Rd_Data
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Wr_En                      <= Addr_Match and Wr_Enable;
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  -- Note that this RAM should be created without an output FF (unregistered Q)
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  U_RAM : entity work.ram_1k_core
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  port map(
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    address                  => RAM_Addr,
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    clock                    => Clock,
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    data                     => Wr_Data,
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    wren                     => Wr_En,
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    q                        => Rd_Data_i
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  );
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  RAM_proc: process( Reset, Clock )
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  begin
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    if( Reset = Reset_Level )then
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      Rd_En                  <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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    elsif( rising_edge(Clock) )then
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      Rd_En                  <= Addr_Match and Rd_Enable;
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      Rd_Data                <= OPEN8_NULLBUS;
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      if( Rd_En = '1' )then
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        Rd_Data              <= Rd_Data_i;
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      end if;
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    end if;
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  end process;
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end architecture;

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