Subversion Repositories open8_urisc

-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry

-- All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution,

--       where applicable (as part of a user interface, debugging port, etc.)

--

-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

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--

-- VHDL Units :  o8_register

-- Description:  Provides a single addressible 8-bit output register

--

-- Register Map:

-- Offset  Bitfield Description                        Read/Write

--   0x00  AAAAAAAA Registered Outputs                    (RW)

--

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      12/20/19 Design Start

library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

  use ieee.std_logic_misc.all;

library work;

  use work.open8_pkg.all;

entity o8_register is

generic(

  Default_Value              : DATA_TYPE := x"00";

  Reset_Level                : std_logic;

  Address                    : ADDRESS_TYPE

);

port(

  Clock                      : in  std_logic;

  Reset                      : in  std_logic;

  --

  Bus_Address                : in  ADDRESS_TYPE;

  Wr_Enable                  : in  std_logic;

  Wr_Data                    : in  DATA_TYPE;

  Rd_Enable                  : in  std_logic;

  Rd_Data                    : out DATA_TYPE;

  --

  Register_Out               : out DATA_TYPE

);

end entity;

architecture behave of o8_register is

  constant User_Addr         : std_logic_vector(15 downto 0)

                               := Address(15 downto 0);

  alias  Comp_Addr           is Bus_Address(15 downto 0);

  signal Addr_Match          : std_logic;

  signal Wr_En               : std_logic;

  signal Wr_Data_q           : DATA_TYPE;

  signal Reg_Out             : DATA_TYPE;

  signal Rd_En               : std_logic;

begin

  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';

  io_reg: process( Clock, Reset )

  begin

    if( Reset = Reset_Level )then

      Wr_En                  <= '0';

      Wr_Data_q              <= (others => '0');

      Reg_Out                <= Default_Value;

      Rd_En                  <= '0';

      Rd_Data                <= OPEN8_NULLBUS;

    elsif( rising_edge( Clock ) )then

      Wr_En                  <= Addr_Match and Wr_Enable;

      Wr_Data_q              <= Wr_Data;

      if( Wr_En = '1' )then

        Reg_Out              <= Wr_Data_q;

      end if;

      Rd_Data                <= OPEN8_NULLBUS;

      Rd_En                  <= Addr_Match and Rd_Enable;

      if( Rd_En = '1' )then

        Rd_Data              <= Reg_Out;

      end if;

    end if;

  end process;

  Register_Out               <= Reg_Out;

end architecture;