OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register_wide.vhd] - Blame information for rev 284

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 249 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_register_wide
25
-- Description:  Provides a single addressible 16-bit output register
26
--
27
-- Register Map:
28
-- Offset  Bitfield Description                        Read/Write
29
--   0x00  AAAAAAAA Registered Outputs                    (RW)
30
--
31
-- Revision History
32
-- Author          Date     Change
33
------------------ -------- ---------------------------------------------------
34 279 jshamlet
-- Seth Henry      05/24/20 Design copied and modified from o8_register
35 249 jshamlet
 
36
library ieee;
37
  use ieee.std_logic_1164.all;
38
  use ieee.std_logic_unsigned.all;
39
  use ieee.std_logic_arith.all;
40
  use ieee.std_logic_misc.all;
41
 
42
library work;
43
  use work.open8_pkg.all;
44
 
45
entity o8_register_wide is
46
generic(
47
  Default_Reg0               : DATA_TYPE := x"00";
48
  Default_Reg1               : DATA_TYPE := x"00";
49
  Default_Reg2               : DATA_TYPE := x"00";
50
  Default_Reg3               : DATA_TYPE := x"00";
51
  Address                    : ADDRESS_TYPE
52
);
53
port(
54
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
55
  Write_Qual                 : in  std_logic := '1';
56
  Rd_Data                    : out DATA_TYPE;
57
  --
58
  Register_0                 : out DATA_TYPE;
59
  Register_1                 : out DATA_TYPE;
60
  Register_2                 : out DATA_TYPE;
61
  Register_3                 : out DATA_TYPE
62
);
63
end entity;
64
 
65
architecture behave of o8_register_wide is
66
 
67
  alias Clock                is Open8_Bus.Clock;
68
  alias Reset                is Open8_Bus.Reset;
69
 
70
  constant User_Addr         : std_logic_vector(15 downto 2)
71
                               := Address(15 downto 2);
72
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
73
  signal Addr_Match          : std_logic;
74
 
75
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
76
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
77
  signal Wr_En_d             : std_logic := '0';
78
  signal Wr_En_q             : std_logic := '0';
79
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
80
  signal Wr_Data_q           : DATA_TYPE := x"00";
81
  signal Rd_En_d             : std_logic := '0';
82
  signal Rd_En_q             : std_logic := '0';
83
 
84
  signal Reg0_Out            : DATA_TYPE := x"00";
85
  signal Reg1_Out            : DATA_TYPE := x"00";
86
  signal Reg2_Out            : DATA_TYPE := x"00";
87
  signal Reg3_Out            : DATA_TYPE := x"00";
88
 
89
begin
90
 
91
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
92
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
93
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
94
 
95
  io_reg: process( Clock, Reset )
96
  begin
97
    if( Reset = Reset_Level )then
98
      Reg_Sel_q              <= "00";
99
      Wr_En_q                <= '0';
100
      Wr_Data_q              <= x"00";
101
      Reg0_Out               <= Default_Reg0;
102
      Reg1_Out               <= Default_Reg1;
103
      Reg2_Out               <= Default_Reg2;
104
      Reg3_Out               <= Default_Reg3;
105
      Rd_En_q                <= '0';
106
      Rd_Data                <= OPEN8_NULLBUS;
107
    elsif( rising_edge( Clock ) )then
108
      Reg_Sel_q              <= Reg_Sel_d;
109
 
110
      Wr_En_q                <= Wr_En_d;
111
      Wr_Data_q              <= Wr_Data_d;
112
      if( Wr_En_q = '1' and Write_Qual = '1' )then
113
        case( Reg_Sel_q )is
114
          when "00" =>
115
            Reg0_Out         <= Wr_Data_q;
116
          when "01" =>
117
            Reg1_Out         <= Wr_Data_q;
118
          when "10" =>
119
            Reg2_Out         <= Wr_Data_q;
120
          when "11" =>
121
            Reg3_Out         <= Wr_Data_q;
122
          when others =>
123
            null;
124
        end case;
125
      end if;
126
 
127
      Rd_Data                <= OPEN8_NULLBUS;
128
      Rd_En_q                <= Rd_En_d;
129
      if( Rd_En_q = '1' )then
130
        case( Reg_Sel_q )is
131
          when "00" =>
132
            Rd_Data          <= Reg0_Out;
133
          when "01" =>
134
            Rd_Data          <= Reg1_Out;
135
          when "10" =>
136
            Rd_Data          <= Reg2_Out;
137
          when "11" =>
138
            Rd_Data          <= Reg3_Out;
139
          when others =>
140
            null;
141
        end case;
142
      end if;
143
    end if;
144
  end process;
145
 
146
  Register_0                 <= Reg0_Out;
147
  Register_1                 <= Reg1_Out;
148
  Register_2                 <= Reg2_Out;
149
  Register_3                 <= Reg3_Out;
150
 
151
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.