OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register_wide.vhd] - Blame information for rev 329

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 249 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_register_wide
25
-- Description:  Provides a single addressible 16-bit output register
26
--
27
-- Register Map:
28
-- Offset  Bitfield Description                        Read/Write
29 297 jshamlet
--   0x00  AAAAAAAA Registered Output 0                   (RW)
30
--   0x01  AAAAAAAA Registered Output 1                   (RW)
31
--   0x02  AAAAAAAA Registered Output 2                   (RW)
32
--   0x03  AAAAAAAA Registered Output 3                   (RW)
33 249 jshamlet
--
34
-- Revision History
35
-- Author          Date     Change
36
------------------ -------- ---------------------------------------------------
37 279 jshamlet
-- Seth Henry      05/24/20 Design copied and modified from o8_register
38 249 jshamlet
 
39
library ieee;
40
  use ieee.std_logic_1164.all;
41
  use ieee.std_logic_unsigned.all;
42
  use ieee.std_logic_arith.all;
43
  use ieee.std_logic_misc.all;
44
 
45
library work;
46
  use work.open8_pkg.all;
47
 
48
entity o8_register_wide is
49
generic(
50
  Default_Reg0               : DATA_TYPE := x"00";
51
  Default_Reg1               : DATA_TYPE := x"00";
52
  Default_Reg2               : DATA_TYPE := x"00";
53
  Default_Reg3               : DATA_TYPE := x"00";
54
  Address                    : ADDRESS_TYPE
55
);
56
port(
57
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
58
  Write_Qual                 : in  std_logic := '1';
59
  Rd_Data                    : out DATA_TYPE;
60
  --
61
  Register_0                 : out DATA_TYPE;
62
  Register_1                 : out DATA_TYPE;
63
  Register_2                 : out DATA_TYPE;
64
  Register_3                 : out DATA_TYPE
65
);
66
end entity;
67
 
68
architecture behave of o8_register_wide is
69
 
70
  alias Clock                is Open8_Bus.Clock;
71
  alias Reset                is Open8_Bus.Reset;
72
 
73
  constant User_Addr         : std_logic_vector(15 downto 2)
74
                               := Address(15 downto 2);
75
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
76
  signal Addr_Match          : std_logic;
77
 
78
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
79
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
80
  signal Wr_En_d             : std_logic := '0';
81
  signal Wr_En_q             : std_logic := '0';
82
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
83
  signal Wr_Data_q           : DATA_TYPE := x"00";
84
  signal Rd_En_d             : std_logic := '0';
85
  signal Rd_En_q             : std_logic := '0';
86
 
87
  signal Reg0_Out            : DATA_TYPE := x"00";
88
  signal Reg1_Out            : DATA_TYPE := x"00";
89
  signal Reg2_Out            : DATA_TYPE := x"00";
90
  signal Reg3_Out            : DATA_TYPE := x"00";
91
 
92
begin
93
 
94
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
95
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
96
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
97
 
98
  io_reg: process( Clock, Reset )
99
  begin
100
    if( Reset = Reset_Level )then
101
      Reg_Sel_q              <= "00";
102
      Wr_En_q                <= '0';
103
      Wr_Data_q              <= x"00";
104
      Reg0_Out               <= Default_Reg0;
105
      Reg1_Out               <= Default_Reg1;
106
      Reg2_Out               <= Default_Reg2;
107
      Reg3_Out               <= Default_Reg3;
108
      Rd_En_q                <= '0';
109
      Rd_Data                <= OPEN8_NULLBUS;
110
    elsif( rising_edge( Clock ) )then
111
      Reg_Sel_q              <= Reg_Sel_d;
112
 
113
      Wr_En_q                <= Wr_En_d;
114
      Wr_Data_q              <= Wr_Data_d;
115
      if( Wr_En_q = '1' and Write_Qual = '1' )then
116
        case( Reg_Sel_q )is
117
          when "00" =>
118
            Reg0_Out         <= Wr_Data_q;
119
          when "01" =>
120
            Reg1_Out         <= Wr_Data_q;
121
          when "10" =>
122
            Reg2_Out         <= Wr_Data_q;
123
          when "11" =>
124
            Reg3_Out         <= Wr_Data_q;
125
          when others =>
126
            null;
127
        end case;
128
      end if;
129
 
130
      Rd_Data                <= OPEN8_NULLBUS;
131
      Rd_En_q                <= Rd_En_d;
132
      if( Rd_En_q = '1' )then
133
        case( Reg_Sel_q )is
134
          when "00" =>
135
            Rd_Data          <= Reg0_Out;
136
          when "01" =>
137
            Rd_Data          <= Reg1_Out;
138
          when "10" =>
139
            Rd_Data          <= Reg2_Out;
140
          when "11" =>
141
            Rd_Data          <= Reg3_Out;
142
          when others =>
143
            null;
144
        end case;
145
      end if;
146
    end if;
147
  end process;
148
 
149
  Register_0                 <= Reg0_Out;
150
  Register_1                 <= Reg1_Out;
151
  Register_2                 <= Reg2_Out;
152
  Register_3                 <= Reg3_Out;
153
 
154
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.