OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rom_32k.vhd] - Blame information for rev 284

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 194 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
2 174 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 174 jshamlet
--
24
-- VHDL Units :  o8_rom_32k
25
-- Description:  Provides a wrapper layer for a 32kx8 ROM model
26 224 jshamlet
--
27
-- Revision History
28
-- Author          Date     Change
29
------------------ -------- ---------------------------------------------------
30
-- Seth Henry      04/16/20 Revision block added
31 174 jshamlet
 
32
library ieee;
33
use ieee.std_logic_1164.all;
34
use ieee.std_logic_unsigned.all;
35
use ieee.std_logic_arith.all;
36
 
37
library work;
38
  use work.open8_pkg.all;
39
 
40
entity o8_rom_32k is
41
generic(
42 217 jshamlet
  Address                    : ADDRESS_TYPE
43 174 jshamlet
);
44
port(
45 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
46 217 jshamlet
  Rd_Data                    : out DATA_TYPE
47 174 jshamlet
);
48
end entity;
49
 
50
architecture behave of o8_rom_32k is
51
 
52 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
53
  alias Reset                is Open8_Bus.Reset;
54
 
55 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 15) :=
56
                               Address(15 downto 15);
57 223 jshamlet
  alias Comp_Addr            is Open8_Bus.Address(15 downto 15);
58
  alias ROM_Addr             is Open8_Bus.Address(14 downto 0);
59 174 jshamlet
 
60 217 jshamlet
  signal Addr_Match          : std_logic := '0';
61
  signal Rd_En               : std_logic := '0';
62
  signal Rd_Data_i           : DATA_TYPE := OPEN8_NULLBUS;
63 174 jshamlet
 
64
begin
65
 
66
  -- Note that this RAM should be created without an output FF (unregistered Q)
67
  U_ROM_CORE : entity work.rom_32k_core
68
  port map(
69 217 jshamlet
    address                  => ROM_Addr,
70
    clock                    => Clock,
71
    q                        => Rd_Data_i
72 174 jshamlet
  );
73
 
74 223 jshamlet
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
75
                                '0';
76 174 jshamlet
 
77 276 jshamlet
  ROM_proc: process( Reset, Clock )
78 174 jshamlet
  begin
79
    if( Reset = Reset_Level )then
80 217 jshamlet
      Rd_En                  <= '0';
81
      Rd_Data                <= OPEN8_NULLBUS;
82 174 jshamlet
    elsif( rising_edge(Clock) )then
83 217 jshamlet
      Rd_En                  <= Addr_Match;
84
      Rd_Data                <= OPEN8_NULLBUS;
85 174 jshamlet
      if( Rd_En = '1' )then
86 217 jshamlet
        Rd_Data              <= Rd_Data_i;
87 174 jshamlet
      end if;
88
    end if;
89
  end process;
90
 
91
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.