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jshamlet |
-- VHDL Units : realtime_clock
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-- Description: Provides automatically updated registers that maintain the
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-- : time of day. Keeps track of the day of week, hours, minutes
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-- : seconds, and tenths of a second. Module is doubled buffered
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-- : to ensure time consistency during accesses. Also provides
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-- : a programmable periodic interrupt timer, as well as a uSec
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-- : tick for external use.
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189 |
jshamlet |
--
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168 |
jshamlet |
-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA Periodic Interval Timer in uS (RW)
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189 |
jshamlet |
-- 0x1 -AAAAAAA Tenths (0x00 - 0x63) (RW)
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-- 0x2 --AAAAAA Seconds (0x00 - 0x3B) (RW)
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-- 0x3 --AAAAAA Minutes (0x00 - 0x3B) (RW)
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-- 0x4 ---AAAAA Hours (0x00 - 0x17) (RW)
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168 |
jshamlet |
-- 0x5 -----AAA Day of Week (0x00 - 0x06) (RW)
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-- 0x6 -------- Update RTC regs from Shadow Regs (WO)
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-- 0x7 A------- Update Shadow Regs from RTC regs (RW)
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-- A = Update is Busy
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.open8_pkg.all;
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entity o8_rtc is
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generic(
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189 |
jshamlet |
Sys_Freq : real;
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168 |
jshamlet |
Reset_Level : std_logic;
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189 |
jshamlet |
Address : ADDRESS_TYPE
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168 |
jshamlet |
);
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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uSec_Tick : out std_logic;
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--
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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--
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Interrupt_PIT : out std_logic;
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Interrupt_RTC : out std_logic
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);
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end entity;
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architecture behave of o8_rtc is
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constant User_Addr : std_logic_vector(15 downto 3)
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:= Address(15 downto 3);
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alias Comp_Addr is Bus_Address(15 downto 3);
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signal Addr_Match : std_logic;
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alias Reg_Addr is Bus_Address(2 downto 0);
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signal Reg_Addr_q : std_logic_vector(2 downto 0);
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signal Wr_En : std_logic;
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signal Wr_Data_q : DATA_TYPE;
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signal Rd_En : std_logic;
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constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
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constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
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constant DLY_1USEC : std_logic_vector :=
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conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
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signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
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:= (others => '0');
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signal uSec_Tick_i : std_logic;
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type PIT_TYPE is record
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timer_cnt : DATA_TYPE;
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timer_ro : std_logic;
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end record;
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signal pit : PIT_TYPE;
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type RTC_TYPE is record
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frac : std_logic_vector(15 downto 0);
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frac_ro : std_logic;
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tens_l : std_logic_vector(3 downto 0);
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tens_l_ro : std_logic;
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tens_u : std_logic_vector(3 downto 0);
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tens_u_ro : std_logic;
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secs_l : std_logic_vector(3 downto 0);
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secs_l_ro : std_logic;
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secs_u : std_logic_vector(3 downto 0);
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secs_u_ro : std_logic;
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mins_l : std_logic_vector(3 downto 0);
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mins_l_ro : std_logic;
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mins_u : std_logic_vector(3 downto 0);
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mins_u_ro : std_logic;
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hours_l : std_logic_vector(3 downto 0);
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hours_l_ro : std_logic;
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hours_u : std_logic_vector(3 downto 0);
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hours_u_ro : std_logic;
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dow : std_logic_vector(2 downto 0);
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end record;
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constant DECISEC : std_logic_vector(15 downto 0) :=
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conv_std_logic_vector(10000,16);
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signal rtc : RTC_TYPE;
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signal interval : DATA_TYPE;
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signal shd_tens : DATA_TYPE;
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signal shd_secs : DATA_TYPE;
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signal shd_mins : DATA_TYPE;
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signal shd_hours : DATA_TYPE;
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signal shd_dow : DATA_TYPE;
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signal update_rtc : std_logic;
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signal update_shd : std_logic;
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signal update_ctmr : std_logic_vector(3 downto 0);
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begin
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uSec_Tick <= uSec_Tick_i;
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Interrupt_PIT <= pit.timer_ro;
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Interrupt_RTC <= rtc.frac_ro;
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io_reg: process( Clock, Reset )
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begin
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if( Reset = Reset_Level )then
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uSec_Cntr <= (others => '0');
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uSec_Tick_i <= '0';
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pit.timer_cnt <= x"00";
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pit.timer_ro <= '0';
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rtc.frac <= DECISEC;
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rtc.frac_ro <= '0';
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rtc.tens_l <= (others => '0');
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rtc.tens_l_ro <= '0';
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rtc.tens_u <= (others => '0');
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rtc.tens_u_ro <= '0';
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rtc.secs_l <= (others => '0');
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rtc.secs_l_ro <= '0';
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rtc.secs_u <= (others => '0');
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rtc.secs_u_ro <= '0';
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rtc.mins_l <= (others => '0');
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rtc.mins_l_ro <= '0';
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rtc.mins_u <= (others => '0');
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rtc.mins_u_ro <= '0';
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rtc.hours_l <= (others => '0');
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rtc.hours_l_ro <= '0';
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rtc.hours_u <= (others => '0');
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rtc.hours_u_ro <= '0';
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rtc.dow <= (others => '0');
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shd_tens <= (others => '0');
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shd_secs <= (others => '0');
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shd_mins <= (others => '0');
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shd_hours <= (others => '0');
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shd_dow <= (others => '0');
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update_rtc <= '0';
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update_shd <= '0';
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update_ctmr <= (others => '0');
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interval <= x"00";
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Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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elsif( rising_edge( Clock ) )then
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uSec_Cntr <= uSec_Cntr - 1;
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uSec_Tick_i <= '0';
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if( uSec_Cntr = 0 )then
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uSec_Cntr <= DLY_1USEC;
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189 |
jshamlet |
uSec_Tick_i <= or_reduce(Interval);
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168 |
jshamlet |
end if;
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pit.timer_ro <= '0';
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rtc.frac_ro <= '0';
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rtc.tens_l_ro <= '0';
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rtc.tens_u_ro <= '0';
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rtc.secs_l_ro <= '0';
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rtc.secs_u_ro <= '0';
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rtc.mins_l_ro <= '0';
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rtc.mins_u_ro <= '0';
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rtc.hours_l_ro <= '0';
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rtc.hours_u_ro <= '0';
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-- Periodic Interval Timer
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pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
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if( or_reduce(pit.timer_cnt) = '0' )then
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pit.timer_cnt <= interval;
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pit.timer_ro <= or_reduce(interval); -- Only issue output on Int > 0
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end if;
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-- Fractional decisecond counter - cycles every 10k microseconds
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rtc.frac <= rtc.frac - uSec_Tick_i;
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if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
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rtc.frac <= DECISEC;
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rtc.frac_ro <= not update_rtc;
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end if;
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| 228 |
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-- Decisecond counter (lower)
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rtc.tens_l <= rtc.tens_l + rtc.frac_ro;
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if( update_rtc = '1' )then
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rtc.tens_l <= shd_tens(3 downto 0);
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elsif( rtc.tens_l > x"9")then
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rtc.tens_l <= (others => '0');
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rtc.tens_l_ro <= '1';
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end if;
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-- Decisecond counter (upper)
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rtc.tens_u <= rtc.tens_u + rtc.tens_l_ro;
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if( update_rtc = '1' )then
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rtc.tens_u <= shd_tens(7 downto 4);
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| 242 |
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elsif( rtc.tens_u > x"9")then
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rtc.tens_u <= (others => '0');
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rtc.tens_u_ro <= '1';
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end if;
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| 246 |
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-- Second counter (lower)
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rtc.secs_l <= rtc.secs_l + rtc.tens_u_ro;
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if( update_rtc = '1' )then
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rtc.secs_l <= shd_secs(3 downto 0);
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| 251 |
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elsif( rtc.secs_l > x"9")then
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rtc.secs_l <= (others => '0');
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rtc.secs_l_ro <= '1';
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end if;
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| 255 |
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-- Second counter (upper)
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rtc.secs_u <= rtc.secs_u + rtc.secs_l_ro;
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| 258 |
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if( update_rtc = '1' )then
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| 259 |
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rtc.secs_u <= shd_secs(7 downto 4);
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| 260 |
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elsif( rtc.secs_u > x"5")then
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| 261 |
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rtc.secs_u <= (others => '0');
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| 262 |
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rtc.secs_u_ro <= '1';
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| 263 |
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end if;
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| 264 |
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-- Minutes counter (lower)
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rtc.mins_l <= rtc.mins_l + rtc.secs_u_ro;
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| 267 |
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if( update_rtc = '1' )then
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rtc.mins_l <= shd_mins(3 downto 0);
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| 269 |
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elsif( rtc.mins_l > x"9")then
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| 270 |
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rtc.mins_l <= (others => '0');
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| 271 |
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rtc.mins_l_ro <= '1';
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end if;
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| 273 |
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| 274 |
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-- Minutes counter (upper)
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rtc.mins_u <= rtc.mins_u + rtc.mins_l_ro;
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| 276 |
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if( update_rtc = '1' )then
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rtc.mins_u <= shd_mins(7 downto 4);
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| 278 |
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elsif( rtc.mins_u > x"5")then
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| 279 |
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rtc.mins_u <= (others => '0');
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| 280 |
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rtc.mins_u_ro <= '1';
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| 281 |
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end if;
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| 282 |
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| 283 |
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-- Hour counter (lower)
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| 284 |
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rtc.hours_l <= rtc.hours_l + rtc.mins_u_ro;
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| 285 |
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if( update_rtc = '1' )then
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| 286 |
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rtc.hours_l <= shd_hours(3 downto 0);
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| 287 |
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elsif( rtc.hours_l > x"9")then
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| 288 |
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rtc.hours_l <= (others => '0');
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| 289 |
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rtc.hours_l_ro <= '1';
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| 290 |
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end if;
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| 291 |
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| 292 |
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-- Hour counter (upper)
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| 293 |
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rtc.hours_u <= rtc.hours_u + rtc.hours_l_ro;
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| 294 |
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if( update_rtc = '1' )then
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| 295 |
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rtc.hours_u <= shd_hours(7 downto 4);
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| 296 |
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end if;
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| 297 |
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| 298 |
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if( rtc.hours_u >= x"2" and rtc.hours_l > x"3" )then
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| 299 |
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rtc.hours_l <= (others => '0');
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| 300 |
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rtc.hours_u <= (others => '0');
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| 301 |
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rtc.hours_u_ro <= '1';
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| 302 |
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end if;
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| 303 |
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| 304 |
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-- Day of Week counter
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| 305 |
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rtc.dow <= rtc.dow + rtc.hours_u_ro;
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| 306 |
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if( update_rtc = '1' )then
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| 307 |
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rtc.dow <= shd_dow(2 downto 0);
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| 308 |
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elsif( rtc.dow = x"07")then
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| 309 |
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rtc.dow <= (others => '0');
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| 310 |
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end if;
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| 311 |
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| 312 |
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-- Copy the RTC registers to the shadow registers when the coherency
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| 313 |
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-- timer is zero (RTC registers are static)
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| 314 |
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if( update_shd = '1' and or_reduce(update_ctmr) = '0' )then
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| 315 |
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shd_tens <= rtc.tens_u & rtc.tens_l;
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| 316 |
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shd_secs <= rtc.secs_u & rtc.secs_l;
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| 317 |
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shd_mins <= rtc.mins_u & rtc.mins_l;
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| 318 |
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shd_hours <= rtc.hours_u & rtc.hours_l;
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| 319 |
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shd_dow <= "00000" & rtc.dow;
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| 320 |
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update_shd <= '0';
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| 321 |
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end if;
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| 322 |
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| 323 |
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Reg_Addr_q <= Reg_Addr;
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| 324 |
|
|
Wr_Data_q <= Wr_Data;
|
| 325 |
|
|
|
| 326 |
|
|
Wr_En <= Addr_Match and Wr_Enable;
|
| 327 |
|
|
update_rtc <= '0';
|
| 328 |
|
|
if( Wr_En = '1' )then
|
| 329 |
|
|
case( Reg_Addr_q )is
|
| 330 |
|
|
when "000" =>
|
| 331 |
|
|
interval <= Wr_Data_q;
|
| 332 |
|
|
|
| 333 |
|
|
when "001" =>
|
| 334 |
|
|
shd_tens <= Wr_Data_q;
|
| 335 |
|
|
|
| 336 |
|
|
when "010" =>
|
| 337 |
|
|
shd_secs <= Wr_Data_q;
|
| 338 |
|
|
|
| 339 |
|
|
when "011" =>
|
| 340 |
|
|
shd_mins <= Wr_Data_q;
|
| 341 |
|
|
|
| 342 |
|
|
when "100" =>
|
| 343 |
|
|
shd_hours <= Wr_Data_q;
|
| 344 |
|
|
|
| 345 |
|
|
when "101" =>
|
| 346 |
|
|
shd_dow <= Wr_Data_q;
|
| 347 |
|
|
|
| 348 |
|
|
when "110" =>
|
| 349 |
|
|
update_rtc <= '1';
|
| 350 |
|
|
|
| 351 |
|
|
when "111" =>
|
| 352 |
|
|
update_shd <= '1';
|
| 353 |
|
|
|
| 354 |
|
|
when others => null;
|
| 355 |
|
|
end case;
|
| 356 |
|
|
end if;
|
| 357 |
|
|
|
| 358 |
|
|
-- Coherency timer - ensures that the shadow registers are updated with
|
| 359 |
|
|
-- valid time data by delaying updates until the rtc registers have
|
| 360 |
|
|
-- finished cascading.
|
| 361 |
|
|
update_ctmr <= update_ctmr - or_reduce(update_ctmr);
|
| 362 |
|
|
if( rtc.frac_ro = '1' )then
|
| 363 |
|
|
update_ctmr <= (others => '1');
|
| 364 |
|
|
end if;
|
| 365 |
|
|
|
| 366 |
|
|
Rd_Data <= (others => '0');
|
| 367 |
|
|
Rd_En <= Addr_Match and Rd_Enable;
|
| 368 |
|
|
if( Rd_En = '1' )then
|
| 369 |
|
|
case( Reg_Addr_q )is
|
| 370 |
|
|
when "000" =>
|
| 371 |
|
|
Rd_Data <= interval;
|
| 372 |
|
|
when "001" =>
|
| 373 |
|
|
Rd_Data <= shd_tens;
|
| 374 |
|
|
when "010" =>
|
| 375 |
|
|
Rd_Data <= shd_secs;
|
| 376 |
|
|
when "011" =>
|
| 377 |
|
|
Rd_Data <= shd_mins;
|
| 378 |
|
|
when "100" =>
|
| 379 |
|
|
Rd_Data <= shd_hours;
|
| 380 |
|
|
when "101" =>
|
| 381 |
|
|
Rd_Data <= shd_dow;
|
| 382 |
|
|
when "110" =>
|
| 383 |
|
|
null;
|
| 384 |
|
|
when "111" =>
|
| 385 |
|
|
Rd_Data <= update_shd & "0000000";
|
| 386 |
|
|
when others => null;
|
| 387 |
|
|
end case;
|
| 388 |
|
|
end if;
|
| 389 |
|
|
|
| 390 |
|
|
end if;
|
| 391 |
|
|
end process;
|
| 392 |
|
|
|
| 393 |
|
|
end architecture;
|
