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-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--       notice, this list of conditions and the following disclaimer.
--     * Redistributions in binary form must reproduce the above copyright
--       notice, this list of conditions and the following disclaimer in the
--       documentation and/or other materials provided with the distribution,
--       where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units :  o8_rtc
-- Description:  Provides automatically updated registers that maintain the
--            :   time of day. Keeps track of the day of week, hours, minutes
--            :   seconds, and tenths of a second in packed BCD format.
--            :  Module is doubled buffered to ensure time consistency during
--            :   accesses.
--            :  Also provides an 8-bit programmable periodic interrupt timer
--            :   with 1uS resolution, a 10uS fixed interrupt, as well as a
--            :   1 uSec tick (1 clock wide) for external use.
--
-- Register Map:
-- Offset  Bitfield Description                        Read/Write
--   0x0   AAAAAAAA Periodic Interval Timer in uS      (RW)
--   0x1   BBBBAAAA Tenths  (0x00 - 0x99)              (RW)
--   0x2   -BBBAAAA Seconds (0x00 - 0x59)              (RW)
--   0x3   -BBBAAAA Minutes (0x00 - 0x59)              (RW)
--   0x4   --BBAAAA Hours   (0x00 - 0x23)              (RW)
--   0x5   -----AAA Day of Week (0x00 - 0x06)          (RW)
--   0x6   -------- Update RTC regs from Shadow Regs   (WO)
--   0x7   A------- Update Shadow Regs from RTC regs   (RW)
--                  A = Update is Busy
 
library ieee;
use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_misc.all;
 
library work;
  use work.open8_pkg.all;
 
entity o8_rtc is
generic(
  Sys_Freq                   : real;
  Reset_Level                : std_logic;
  Address                    : ADDRESS_TYPE
);
port(
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  uSec_Tick                  : out std_logic;
  --
  Bus_Address                : in  ADDRESS_TYPE;
  Wr_Enable                  : in  std_logic;
  Wr_Data                    : in  DATA_TYPE;
  Rd_Enable                  : in  std_logic;
  Rd_Data                    : out DATA_TYPE;
  --
  Interrupt_PIT              : out std_logic;
  Interrupt_RTC              : out std_logic
);
end entity;
 
architecture behave of o8_rtc is
 
  constant User_Addr         : std_logic_vector(15 downto 3)
                               := Address(15 downto 3);
  alias  Comp_Addr           is Bus_Address(15 downto 3);
  signal Addr_Match          : std_logic;
 
  alias  Reg_Addr            is Bus_Address(2 downto 0);
  signal Reg_Addr_q          : std_logic_vector(2 downto 0);
 
  signal Wr_En               : std_logic;
  signal Wr_Data_q           : DATA_TYPE;
  signal Rd_En               : std_logic;
 
  constant DLY_1USEC_VAL     : integer := integer(Sys_Freq / 1000000.0);
  constant DLY_1USEC_WDT     : integer := ceil_log2(DLY_1USEC_VAL - 1);
  constant DLY_1USEC         : std_logic_vector :=
                     conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
 
  signal uSec_Cntr           : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
                               := (others => '0');
  signal uSec_Tick_i         : std_logic;
 
  type PIT_TYPE is record
    timer_cnt                : DATA_TYPE;
    timer_ro                 : std_logic;
  end record;
 
  signal pit                 : PIT_TYPE;
 
  type RTC_TYPE is record
    frac                     : std_logic_vector(15 downto 0);
    frac_ro                  : std_logic;
 
    tens_l                   : std_logic_vector(3 downto 0);
    tens_l_ro                : std_logic;
 
    tens_u                   : std_logic_vector(3 downto 0);
    tens_u_ro                : std_logic;
 
    secs_l                   : std_logic_vector(3 downto 0);
    secs_l_ro                : std_logic;
 
    secs_u                   : std_logic_vector(3 downto 0);
    secs_u_ro                : std_logic;
 
    mins_l                   : std_logic_vector(3 downto 0);
    mins_l_ro                : std_logic;
 
    mins_u                   : std_logic_vector(3 downto 0);
    mins_u_ro                : std_logic;
 
    hours_l                  : std_logic_vector(3 downto 0);
    hours_l_ro               : std_logic;
 
    hours_u                  : std_logic_vector(3 downto 0);
    hours_u_ro               : std_logic;
 
    dow                      : std_logic_vector(2 downto 0);
  end record;
 
  constant DECISEC           : std_logic_vector(15 downto 0) :=
                                conv_std_logic_vector(10000,16);
 
  signal rtc                 : RTC_TYPE;
 
  signal interval            : DATA_TYPE;
  signal update_interval     : std_logic;
 
  signal shd_tens            : DATA_TYPE;
  signal shd_secs            : DATA_TYPE;
  signal shd_mins            : DATA_TYPE;
  signal shd_hours           : DATA_TYPE;
  signal shd_dow             : DATA_TYPE;
 
  signal update_rtc          : std_logic;
  signal update_shd          : std_logic;
  signal update_ctmr         : std_logic_vector(3 downto 0);
 
begin
 
  uSec_Tick                  <= uSec_Tick_i;
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Interrupt_PIT              <= pit.timer_ro;
  Interrupt_RTC              <= rtc.frac_ro;
 
  io_reg: process( Clock, Reset )
  begin
    if( Reset = Reset_Level )then
      uSec_Cntr              <= (others => '0');
      uSec_Tick_i            <= '0';
 
      pit.timer_cnt          <= x"00";
      pit.timer_ro           <= '0';
 
      rtc.frac               <= DECISEC;
      rtc.frac_ro            <= '0';
 
      rtc.tens_l             <= (others => '0');
      rtc.tens_l_ro          <= '0';
 
      rtc.tens_u             <= (others => '0');
      rtc.tens_u_ro          <= '0';
 
      rtc.secs_l             <= (others => '0');
      rtc.secs_l_ro          <= '0';
 
      rtc.secs_u             <= (others => '0');
      rtc.secs_u_ro          <= '0';
 
      rtc.mins_l             <= (others => '0');
      rtc.mins_l_ro          <= '0';
 
      rtc.mins_u             <= (others => '0');
      rtc.mins_u_ro          <= '0';
 
      rtc.hours_l            <= (others => '0');
      rtc.hours_l_ro         <= '0';
 
      rtc.hours_u            <= (others => '0');
      rtc.hours_u_ro         <= '0';
 
      rtc.dow                <= (others => '0');
 
      shd_tens               <= (others => '0');
      shd_secs               <= (others => '0');
      shd_mins               <= (others => '0');
      shd_hours              <= (others => '0');
      shd_dow                <= (others => '0');
 
      update_rtc             <= '0';
      update_shd             <= '0';
      update_ctmr            <= (others => '0');
 
      interval               <= x"00";
      update_interval        <= '0';
 
      Wr_Data_q              <= (others => '0');
      Reg_Addr_q             <= (others => '0');
      Wr_En                  <= '0';
      Rd_En                  <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
 
    elsif( rising_edge( Clock ) )then
 
      uSec_Cntr              <= uSec_Cntr - 1;
      uSec_Tick_i            <= '0';
      if( uSec_Cntr = 0 )then
        uSec_Cntr            <= DLY_1USEC;
        uSec_Tick_i          <= '1';
      end if;
 
      -- Periodic Interval Timer
      pit.timer_cnt          <= pit.timer_cnt - uSec_Tick_i;
      pit.timer_ro           <= '0';
      if( update_interval = '1' )then
        pit.timer_cnt        <= interval;
      elsif( or_reduce(pit.timer_cnt) = '0' )then
        pit.timer_cnt        <= interval;
        pit.timer_ro         <= or_reduce(interval);
      end if;
 
      -- Fractional decisecond counter - cycles every 10k microseconds
      rtc.frac               <= rtc.frac - uSec_Tick_i;
      rtc.frac_ro            <= '0';
      if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
        rtc.frac             <= DECISEC;
        rtc.frac_ro          <= not update_rtc;
      end if;
 
      -- Decisecond counter (lower)
      rtc.tens_l             <= rtc.tens_l + rtc.frac_ro;
      rtc.tens_l_ro          <= '0';
      if( update_rtc = '1' )then
        rtc.tens_l           <= shd_tens(3 downto 0);
      elsif( rtc.tens_l > x"9")then
        rtc.tens_l           <= (others => '0');
        rtc.tens_l_ro        <= '1';
      end if;
 
      -- Decisecond counter (upper)
      rtc.tens_u             <= rtc.tens_u + rtc.tens_l_ro;
      rtc.tens_u_ro          <= '0';
      if( update_rtc = '1' )then
        rtc.tens_u           <= shd_tens(7 downto 4);
      elsif( rtc.tens_u > x"9")then
        rtc.tens_u           <= (others => '0');
        rtc.tens_u_ro        <= '1';
      end if;
 
      -- Second counter (lower)
      rtc.secs_l             <= rtc.secs_l + rtc.tens_u_ro;
      rtc.secs_l_ro          <= '0';
      if( update_rtc = '1' )then
        rtc.secs_l           <= shd_secs(3 downto 0);
      elsif( rtc.secs_l > x"9")then
        rtc.secs_l           <= (others => '0');
        rtc.secs_l_ro        <= '1';
      end if;
 
      -- Second counter (upper)
      rtc.secs_u             <= rtc.secs_u + rtc.secs_l_ro;
      rtc.secs_u_ro          <= '0';
      if( update_rtc = '1' )then
        rtc.secs_u           <= shd_secs(7 downto 4);
      elsif( rtc.secs_u > x"5")then
        rtc.secs_u           <= (others => '0');
        rtc.secs_u_ro        <= '1';
      end if;
 
      -- Minutes counter (lower)
      rtc.mins_l             <= rtc.mins_l + rtc.secs_u_ro;
      rtc.mins_l_ro          <= '0';
      if( update_rtc = '1' )then
        rtc.mins_l           <= shd_mins(3 downto 0);
      elsif( rtc.mins_l > x"9")then
        rtc.mins_l           <= (others => '0');
        rtc.mins_l_ro        <= '1';
      end if;
 
      -- Minutes counter (upper)
      rtc.mins_u             <= rtc.mins_u + rtc.mins_l_ro;
      rtc.mins_u_ro          <= '0';
      if( update_rtc = '1' )then
        rtc.mins_u           <= shd_mins(7 downto 4);
      elsif( rtc.mins_u > x"5")then
        rtc.mins_u           <= (others => '0');
        rtc.mins_u_ro        <= '1';
      end if;
 
      -- Hour counter (lower)
      rtc.hours_l            <= rtc.hours_l + rtc.mins_u_ro;
      rtc.hours_l_ro         <= '0';
      if( update_rtc = '1' )then
        rtc.hours_l          <= shd_hours(3 downto 0);
      elsif( rtc.hours_l > x"9")then
        rtc.hours_l          <= (others => '0');
        rtc.hours_l_ro       <= '1';
      end if;
 
      -- Hour counter (upper)
      rtc.hours_u            <= rtc.hours_u + rtc.hours_l_ro;
      if( update_rtc = '1' )then
        rtc.hours_u          <= shd_hours(7 downto 4);
      end if;
 
      rtc.hours_u_ro         <= '0';
      if( rtc.hours_u >= x"2" and rtc.hours_l > x"3" )then
        rtc.hours_l          <= (others => '0');
        rtc.hours_u          <= (others => '0');
        rtc.hours_u_ro       <= '1';
      end if;
 
      -- Day of Week counter
      rtc.dow                <= rtc.dow + rtc.hours_u_ro;
      if( update_rtc = '1' )then
        rtc.dow              <= shd_dow(2 downto 0);
      elsif( rtc.dow = x"07")then
        rtc.dow              <= (others => '0');
      end if;
 
      -- Copy the RTC registers to the shadow registers when the coherency
      --  timer is zero (RTC registers are static)
      if( update_shd = '1' and or_reduce(update_ctmr) = '0' )then
        shd_tens             <= rtc.tens_u & rtc.tens_l;
        shd_secs             <= rtc.secs_u & rtc.secs_l;
        shd_mins             <= rtc.mins_u & rtc.mins_l;
        shd_hours            <= rtc.hours_u & rtc.hours_l;
        shd_dow              <= "00000" & rtc.dow;
        update_shd           <= '0';
      end if;
 
      update_interval        <= '0';
 
      Reg_Addr_q             <= Reg_Addr;
      Wr_Data_q              <= Wr_Data;
 
      Wr_En                  <= Addr_Match and Wr_Enable;
      update_rtc             <= '0';
      if( Wr_En = '1' )then
        case( Reg_Addr_q )is
          when "000" =>
            interval         <= Wr_Data_q;
            update_interval  <= '1';
 
          when "001" =>
            shd_tens         <= Wr_Data_q;
 
          when "010" =>
            shd_secs         <= Wr_Data_q;
 
          when "011" =>
            shd_mins         <= Wr_Data_q;
 
          when "100" =>
            shd_hours        <= Wr_Data_q;
 
          when "101" =>
            shd_dow          <= Wr_Data_q;
 
          when "110" =>
            update_rtc       <= '1';
 
          when "111" =>
            update_shd  <= '1';
 
          when others => null;
        end case;
      end if;
 
      -- Coherency timer - ensures that the shadow registers are updated with
      --  valid time data by delaying updates until the rtc registers have
      --  finished cascading.
      update_ctmr            <= update_ctmr - or_reduce(update_ctmr);
      if( rtc.frac_ro = '1' )then
        update_ctmr          <= (others => '1');
      end if;
 
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= Addr_Match and Rd_Enable;
      if( Rd_En = '1' )then
        case( Reg_Addr_q )is
          when "000" =>
            Rd_Data          <= interval;
          when "001" =>
            Rd_Data          <= shd_tens;
          when "010" =>
            Rd_Data          <= shd_secs;
          when "011" =>
            Rd_Data          <= shd_mins;
          when "100" =>
            Rd_Data          <= shd_hours;
          when "101" =>
            Rd_Data          <= shd_dow;
          when "110" =>
            null;
          when "111" =>
            Rd_Data          <= update_shd & "0000000";
          when others => null;
        end case;
      end if;
 
    end if;
  end process;
 
end architecture;

Line No.	Rev	Author	Line
1	191	jshamlet	`-- Copyright (c)2020 Jeremy Seth Henry`
2			`-- All rights reserved.`
3			`--`
4			`-- Redistribution and use in source and binary forms, with or without`
5			`-- modification, are permitted provided that the following conditions are met:`
6			`-- * Redistributions of source code must retain the above copyright`
7			`-- notice, this list of conditions and the following disclaimer.`
8			`-- * Redistributions in binary form must reproduce the above copyright`
9			`-- notice, this list of conditions and the following disclaimer in the`
10			`-- documentation and/or other materials provided with the distribution,`
11			`-- where applicable (as part of a user interface, debugging port, etc.)`
12			`--`
13			-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14			`-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED`
15			`-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
16			`-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY`
17			`-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
18			`-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
19			`-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
20			`-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
21	194	jshamlet	`-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
22			`-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
23	191	jshamlet	`--`
24			`-- VHDL Units : o8_rtc`
25	168	jshamlet	`-- Description: Provides automatically updated registers that maintain the`
26			`-- : time of day. Keeps track of the day of week, hours, minutes`
27	213	jshamlet	`-- : seconds, and tenths of a second in packed BCD format.`
28			`-- : Module is doubled buffered to ensure time consistency during`
29			`-- : accesses.`
30			`-- : Also provides an 8-bit programmable periodic interrupt timer`
31			`-- : with 1uS resolution, a 10uS fixed interrupt, as well as a`
32			`-- : 1 uSec tick (1 clock wide) for external use.`
33	191	jshamlet	`--`
34	168	jshamlet	`-- Register Map:`
35			`-- Offset Bitfield Description Read/Write`
36			`-- 0x0 AAAAAAAA Periodic Interval Timer in uS (RW)`
37	213	jshamlet	`-- 0x1 BBBBAAAA Tenths (0x00 - 0x99) (RW)`
38			`-- 0x2 -BBBAAAA Seconds (0x00 - 0x59) (RW)`
39			`-- 0x3 -BBBAAAA Minutes (0x00 - 0x59) (RW)`
40			`-- 0x4 --BBAAAA Hours (0x00 - 0x23) (RW)`
41	168	jshamlet	`-- 0x5 -----AAA Day of Week (0x00 - 0x06) (RW)`
42			`-- 0x6 -------- Update RTC regs from Shadow Regs (WO)`
43			`-- 0x7 A------- Update Shadow Regs from RTC regs (RW)`
44			`-- A = Update is Busy`
45
46			`library ieee;`
47			`use ieee.std_logic_1164.all;`
48			`use ieee.std_logic_unsigned.all;`
49			`use ieee.std_logic_arith.all;`
50			`use ieee.std_logic_misc.all;`
51
52			`library work;`
53			`use work.open8_pkg.all;`
54
55			`entity o8_rtc is`
56			`generic(`
57	210	jshamlet	`Sys_Freq : real;`
58			`Reset_Level : std_logic;`
59			`Address : ADDRESS_TYPE`
60	168	jshamlet	`);`
61			`port(`
62	210	jshamlet	`Clock : in std_logic;`
63			`Reset : in std_logic;`
64			`uSec_Tick : out std_logic;`
65	168	jshamlet	`--`
66	210	jshamlet	`Bus_Address : in ADDRESS_TYPE;`
67			`Wr_Enable : in std_logic;`
68			`Wr_Data : in DATA_TYPE;`
69			`Rd_Enable : in std_logic;`
70			`Rd_Data : out DATA_TYPE;`
71	168	jshamlet	`--`
72	210	jshamlet	`Interrupt_PIT : out std_logic;`
73			`Interrupt_RTC : out std_logic`
74	168	jshamlet	`);`
75			`end entity;`
76
77			`architecture behave of o8_rtc is`
78
79	210	jshamlet	`constant User_Addr : std_logic_vector(15 downto 3)`
80			`:= Address(15 downto 3);`
81			`alias Comp_Addr is Bus_Address(15 downto 3);`
82			`signal Addr_Match : std_logic;`
83	168	jshamlet
84	210	jshamlet	`alias Reg_Addr is Bus_Address(2 downto 0);`
85			`signal Reg_Addr_q : std_logic_vector(2 downto 0);`
86	168	jshamlet
87	210	jshamlet	`signal Wr_En : std_logic;`
88			`signal Wr_Data_q : DATA_TYPE;`
89			`signal Rd_En : std_logic;`
90	168	jshamlet
91	210	jshamlet	`constant DLY_1USEC_VAL : integer := integer(Sys_Freq / 1000000.0);`
92			`constant DLY_1USEC_WDT : integer := ceil_log2(DLY_1USEC_VAL - 1);`
93			`constant DLY_1USEC : std_logic_vector :=`
94			`conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);`
95	168	jshamlet
96	210	jshamlet	`signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )`
97			`:= (others => '0');`
98			`signal uSec_Tick_i : std_logic;`
99	168	jshamlet
100			`type PIT_TYPE is record`
101	217	jshamlet	`timer_cnt : DATA_TYPE;`
102			`timer_ro : std_logic;`
103	168	jshamlet	`end record;`
104
105	217	jshamlet	`signal pit : PIT_TYPE;`
106	168	jshamlet
107			`type RTC_TYPE is record`
108	217	jshamlet	`frac : std_logic_vector(15 downto 0);`
109			`frac_ro : std_logic;`
110	168	jshamlet
111	217	jshamlet	`tens_l : std_logic_vector(3 downto 0);`
112			`tens_l_ro : std_logic;`
113	168	jshamlet
114	217	jshamlet	`tens_u : std_logic_vector(3 downto 0);`
115			`tens_u_ro : std_logic;`
116	168	jshamlet
117	217	jshamlet	`secs_l : std_logic_vector(3 downto 0);`
118			`secs_l_ro : std_logic;`
119	168	jshamlet
120	217	jshamlet	`secs_u : std_logic_vector(3 downto 0);`
121			`secs_u_ro : std_logic;`
122	168	jshamlet
123	217	jshamlet	`mins_l : std_logic_vector(3 downto 0);`
124			`mins_l_ro : std_logic;`
125	168	jshamlet
126	217	jshamlet	`mins_u : std_logic_vector(3 downto 0);`
127			`mins_u_ro : std_logic;`
128	168	jshamlet
129	217	jshamlet	`hours_l : std_logic_vector(3 downto 0);`
130			`hours_l_ro : std_logic;`
131	168	jshamlet
132	217	jshamlet	`hours_u : std_logic_vector(3 downto 0);`
133			`hours_u_ro : std_logic;`
134	168	jshamlet
135	217	jshamlet	`dow : std_logic_vector(2 downto 0);`
136	168	jshamlet	`end record;`
137
138	217	jshamlet	`constant DECISEC : std_logic_vector(15 downto 0) :=`
139			`conv_std_logic_vector(10000,16);`
140	168	jshamlet
141	217	jshamlet	`signal rtc : RTC_TYPE;`
142	168	jshamlet
143	217	jshamlet	`signal interval : DATA_TYPE;`
144			`signal update_interval : std_logic;`
145	168	jshamlet
146	217	jshamlet	`signal shd_tens : DATA_TYPE;`
147			`signal shd_secs : DATA_TYPE;`
148			`signal shd_mins : DATA_TYPE;`
149			`signal shd_hours : DATA_TYPE;`
150			`signal shd_dow : DATA_TYPE;`
151	168	jshamlet
152	217	jshamlet	`signal update_rtc : std_logic;`
153			`signal update_shd : std_logic;`
154			`signal update_ctmr : std_logic_vector(3 downto 0);`
155	168	jshamlet
156			`begin`
157
158	210	jshamlet	`uSec_Tick <= uSec_Tick_i;`
159			`Addr_Match <= '1' when Comp_Addr = User_Addr else '0';`
160	168	jshamlet
161	210	jshamlet	`Interrupt_PIT <= pit.timer_ro;`
162			`Interrupt_RTC <= rtc.frac_ro;`
163	168	jshamlet
164			`io_reg: process( Clock, Reset )`
165			`begin`
166			`if( Reset = Reset_Level )then`
167	210	jshamlet	`uSec_Cntr <= (others => '0');`
168			`uSec_Tick_i <= '0';`
169	168	jshamlet
170	210	jshamlet	`pit.timer_cnt <= x"00";`
171			`pit.timer_ro <= '0';`
172	168	jshamlet
173	210	jshamlet	`rtc.frac <= DECISEC;`
174			`rtc.frac_ro <= '0';`
175	168	jshamlet
176	210	jshamlet	`rtc.tens_l <= (others => '0');`
177			`rtc.tens_l_ro <= '0';`
178	168	jshamlet
179	210	jshamlet	`rtc.tens_u <= (others => '0');`
180			`rtc.tens_u_ro <= '0';`
181	168	jshamlet
182	210	jshamlet	`rtc.secs_l <= (others => '0');`
183			`rtc.secs_l_ro <= '0';`
184	168	jshamlet
185	210	jshamlet	`rtc.secs_u <= (others => '0');`
186			`rtc.secs_u_ro <= '0';`
187	168	jshamlet
188	210	jshamlet	`rtc.mins_l <= (others => '0');`
189			`rtc.mins_l_ro <= '0';`
190	168	jshamlet
191	210	jshamlet	`rtc.mins_u <= (others => '0');`
192			`rtc.mins_u_ro <= '0';`
193	168	jshamlet
194	210	jshamlet	`rtc.hours_l <= (others => '0');`
195			`rtc.hours_l_ro <= '0';`
196	168	jshamlet
197	210	jshamlet	`rtc.hours_u <= (others => '0');`
198			`rtc.hours_u_ro <= '0';`
199	168	jshamlet
200	210	jshamlet	`rtc.dow <= (others => '0');`
201	168	jshamlet
202	210	jshamlet	`shd_tens <= (others => '0');`
203			`shd_secs <= (others => '0');`
204			`shd_mins <= (others => '0');`
205			`shd_hours <= (others => '0');`
206			`shd_dow <= (others => '0');`
207	168	jshamlet
208	210	jshamlet	`update_rtc <= '0';`
209			`update_shd <= '0';`
210			`update_ctmr <= (others => '0');`
211	168	jshamlet
212	210	jshamlet	`interval <= x"00";`
213			`update_interval <= '0';`
214	168	jshamlet
215	210	jshamlet	`Wr_Data_q <= (others => '0');`
216			`Reg_Addr_q <= (others => '0');`
217			`Wr_En <= '0';`
218			`Rd_En <= '0';`
219			`Rd_Data <= OPEN8_NULLBUS;`
220	168	jshamlet
221			`elsif( rising_edge( Clock ) )then`
222
223	210	jshamlet	`uSec_Cntr <= uSec_Cntr - 1;`
224			`uSec_Tick_i <= '0';`
225	168	jshamlet	`if( uSec_Cntr = 0 )then`
226	210	jshamlet	`uSec_Cntr <= DLY_1USEC;`
227			`uSec_Tick_i <= '1';`
228	168	jshamlet	`end if;`
229
230			`-- Periodic Interval Timer`
231	210	jshamlet	`pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;`
232			`pit.timer_ro <= '0';`
233			`if( update_interval = '1' )then`
234	211	jshamlet	`pit.timer_cnt <= interval;`
235	210	jshamlet	`elsif( or_reduce(pit.timer_cnt) = '0' )then`
236			`pit.timer_cnt <= interval;`
237			`pit.timer_ro <= or_reduce(interval);`
238	168	jshamlet	`end if;`
239
240			`-- Fractional decisecond counter - cycles every 10k microseconds`
241	210	jshamlet	`rtc.frac <= rtc.frac - uSec_Tick_i;`
242			`rtc.frac_ro <= '0';`
243	168	jshamlet	`if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then`
244	210	jshamlet	`rtc.frac <= DECISEC;`
245			`rtc.frac_ro <= not update_rtc;`
246	168	jshamlet	`end if;`
247
248			`-- Decisecond counter (lower)`
249	210	jshamlet	`rtc.tens_l <= rtc.tens_l + rtc.frac_ro;`
250			`rtc.tens_l_ro <= '0';`
251	168	jshamlet	`if( update_rtc = '1' )then`
252	210	jshamlet	`rtc.tens_l <= shd_tens(3 downto 0);`
253	168	jshamlet	`elsif( rtc.tens_l > x"9")then`
254	210	jshamlet	`rtc.tens_l <= (others => '0');`
255			`rtc.tens_l_ro <= '1';`
256	168	jshamlet	`end if;`
257
258			`-- Decisecond counter (upper)`
259	210	jshamlet	`rtc.tens_u <= rtc.tens_u + rtc.tens_l_ro;`
260			`rtc.tens_u_ro <= '0';`
261	168	jshamlet	`if( update_rtc = '1' )then`
262	210	jshamlet	`rtc.tens_u <= shd_tens(7 downto 4);`
263	168	jshamlet	`elsif( rtc.tens_u > x"9")then`
264	210	jshamlet	`rtc.tens_u <= (others => '0');`
265			`rtc.tens_u_ro <= '1';`
266	168	jshamlet	`end if;`
267
268			`-- Second counter (lower)`
269	210	jshamlet	`rtc.secs_l <= rtc.secs_l + rtc.tens_u_ro;`
270			`rtc.secs_l_ro <= '0';`
271	168	jshamlet	`if( update_rtc = '1' )then`
272	210	jshamlet	`rtc.secs_l <= shd_secs(3 downto 0);`
273	168	jshamlet	`elsif( rtc.secs_l > x"9")then`
274	210	jshamlet	`rtc.secs_l <= (others => '0');`
275			`rtc.secs_l_ro <= '1';`
276	168	jshamlet	`end if;`
277
278			`-- Second counter (upper)`
279	210	jshamlet	`rtc.secs_u <= rtc.secs_u + rtc.secs_l_ro;`
280			`rtc.secs_u_ro <= '0';`
281	168	jshamlet	`if( update_rtc = '1' )then`
282	210	jshamlet	`rtc.secs_u <= shd_secs(7 downto 4);`
283	168	jshamlet	`elsif( rtc.secs_u > x"5")then`
284	210	jshamlet	`rtc.secs_u <= (others => '0');`
285			`rtc.secs_u_ro <= '1';`
286	168	jshamlet	`end if;`
287
288			`-- Minutes counter (lower)`
289	210	jshamlet	`rtc.mins_l <= rtc.mins_l + rtc.secs_u_ro;`
290			`rtc.mins_l_ro <= '0';`
291	168	jshamlet	`if( update_rtc = '1' )then`
292	210	jshamlet	`rtc.mins_l <= shd_mins(3 downto 0);`
293	168	jshamlet	`elsif( rtc.mins_l > x"9")then`
294	210	jshamlet	`rtc.mins_l <= (others => '0');`
295			`rtc.mins_l_ro <= '1';`
296	168	jshamlet	`end if;`
297
298			`-- Minutes counter (upper)`
299	210	jshamlet	`rtc.mins_u <= rtc.mins_u + rtc.mins_l_ro;`
300			`rtc.mins_u_ro <= '0';`
301	168	jshamlet	`if( update_rtc = '1' )then`
302	210	jshamlet	`rtc.mins_u <= shd_mins(7 downto 4);`
303	168	jshamlet	`elsif( rtc.mins_u > x"5")then`
304	210	jshamlet	`rtc.mins_u <= (others => '0');`
305			`rtc.mins_u_ro <= '1';`
306	168	jshamlet	`end if;`
307
308			`-- Hour counter (lower)`
309	210	jshamlet	`rtc.hours_l <= rtc.hours_l + rtc.mins_u_ro;`
310			`rtc.hours_l_ro <= '0';`
311	168	jshamlet	`if( update_rtc = '1' )then`
312	210	jshamlet	`rtc.hours_l <= shd_hours(3 downto 0);`
313	168	jshamlet	`elsif( rtc.hours_l > x"9")then`
314	210	jshamlet	`rtc.hours_l <= (others => '0');`
315			`rtc.hours_l_ro <= '1';`
316	168	jshamlet	`end if;`
317
318			`-- Hour counter (upper)`
319	210	jshamlet	`rtc.hours_u <= rtc.hours_u + rtc.hours_l_ro;`
320	168	jshamlet	`if( update_rtc = '1' )then`
321	210	jshamlet	`rtc.hours_u <= shd_hours(7 downto 4);`
322	168	jshamlet	`end if;`
323
324	210	jshamlet	`rtc.hours_u_ro <= '0';`
325	168	jshamlet	`if( rtc.hours_u >= x"2" and rtc.hours_l > x"3" )then`
326	210	jshamlet	`rtc.hours_l <= (others => '0');`
327			`rtc.hours_u <= (others => '0');`
328			`rtc.hours_u_ro <= '1';`
329	168	jshamlet	`end if;`
330
331			`-- Day of Week counter`
332	210	jshamlet	`rtc.dow <= rtc.dow + rtc.hours_u_ro;`
333	168	jshamlet	`if( update_rtc = '1' )then`
334	210	jshamlet	`rtc.dow <= shd_dow(2 downto 0);`
335	168	jshamlet	`elsif( rtc.dow = x"07")then`
336	210	jshamlet	`rtc.dow <= (others => '0');`
337	168	jshamlet	`end if;`
338
339			`-- Copy the RTC registers to the shadow registers when the coherency`
340			`-- timer is zero (RTC registers are static)`
341			`if( update_shd = '1' and or_reduce(update_ctmr) = '0' )then`
342	210	jshamlet	`shd_tens <= rtc.tens_u & rtc.tens_l;`
343			`shd_secs <= rtc.secs_u & rtc.secs_l;`
344			`shd_mins <= rtc.mins_u & rtc.mins_l;`
345			`shd_hours <= rtc.hours_u & rtc.hours_l;`
346			`shd_dow <= "00000" & rtc.dow;`
347			`update_shd <= '0';`
348	168	jshamlet	`end if;`
349
350	210	jshamlet	`update_interval <= '0';`
351	209	jshamlet
352	210	jshamlet	`Reg_Addr_q <= Reg_Addr;`
353			`Wr_Data_q <= Wr_Data;`
354	168	jshamlet
355	210	jshamlet	`Wr_En <= Addr_Match and Wr_Enable;`
356			`update_rtc <= '0';`
357	168	jshamlet	`if( Wr_En = '1' )then`
358			`case( Reg_Addr_q )is`
359			`when "000" =>`
360	211	jshamlet	`interval <= Wr_Data_q;`
361	210	jshamlet	`update_interval <= '1';`
362	168	jshamlet
363			`when "001" =>`
364	210	jshamlet	`shd_tens <= Wr_Data_q;`
365	168	jshamlet
366			`when "010" =>`
367	210	jshamlet	`shd_secs <= Wr_Data_q;`
368	168	jshamlet
369			`when "011" =>`
370	210	jshamlet	`shd_mins <= Wr_Data_q;`
371	168	jshamlet
372			`when "100" =>`
373	210	jshamlet	`shd_hours <= Wr_Data_q;`
374	168	jshamlet
375			`when "101" =>`
376	210	jshamlet	`shd_dow <= Wr_Data_q;`
377	168	jshamlet
378			`when "110" =>`
379	210	jshamlet	`update_rtc <= '1';`
380	168	jshamlet
381			`when "111" =>`
382			`update_shd <= '1';`
383
384			`when others => null;`
385			`end case;`
386			`end if;`
387
388			`-- Coherency timer - ensures that the shadow registers are updated with`
389			`-- valid time data by delaying updates until the rtc registers have`
390			`-- finished cascading.`
391	210	jshamlet	`update_ctmr <= update_ctmr - or_reduce(update_ctmr);`
392	168	jshamlet	`if( rtc.frac_ro = '1' )then`
393	210	jshamlet	`update_ctmr <= (others => '1');`
394	168	jshamlet	`end if;`
395
396	210	jshamlet	`Rd_Data <= OPEN8_NULLBUS;`
397			`Rd_En <= Addr_Match and Rd_Enable;`
398	168	jshamlet	`if( Rd_En = '1' )then`
399			`case( Reg_Addr_q )is`
400			`when "000" =>`
401	210	jshamlet	`Rd_Data <= interval;`
402	168	jshamlet	`when "001" =>`
403	210	jshamlet	`Rd_Data <= shd_tens;`
404	168	jshamlet	`when "010" =>`
405	210	jshamlet	`Rd_Data <= shd_secs;`
406	168	jshamlet	`when "011" =>`
407	210	jshamlet	`Rd_Data <= shd_mins;`
408	168	jshamlet	`when "100" =>`
409	210	jshamlet	`Rd_Data <= shd_hours;`
410	168	jshamlet	`when "101" =>`
411	210	jshamlet	`Rd_Data <= shd_dow;`
412	168	jshamlet	`when "110" =>`
413			`null;`
414			`when "111" =>`
415	210	jshamlet	`Rd_Data <= update_shd & "0000000";`
416	168	jshamlet	`when others => null;`
417			`end case;`
418			`end if;`
419
420			`end if;`
421			`end process;`
422
423			`end architecture;`

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