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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Blame information for rev 242

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1 191 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 191 jshamlet
--
24
-- VHDL Units :  o8_rtc
25 168 jshamlet
-- Description:  Provides automatically updated registers that maintain the
26
--            :   time of day. Keeps track of the day of week, hours, minutes
27 213 jshamlet
--            :   seconds, and tenths of a second in packed BCD format.
28
--            :  Module is doubled buffered to ensure time consistency during
29
--            :   accesses.
30
--            :  Also provides an 8-bit programmable periodic interrupt timer
31
--            :   with 1uS resolution, a 10uS fixed interrupt, as well as a
32
--            :   1 uSec tick (1 clock wide) for external use.
33 191 jshamlet
--
34 168 jshamlet
-- Register Map:
35
-- Offset  Bitfield Description                        Read/Write
36
--   0x0   AAAAAAAA Periodic Interval Timer in uS      (RW)
37 213 jshamlet
--   0x1   BBBBAAAA Tenths  (0x00 - 0x99)              (RW)
38
--   0x2   -BBBAAAA Seconds (0x00 - 0x59)              (RW)
39
--   0x3   -BBBAAAA Minutes (0x00 - 0x59)              (RW)
40
--   0x4   --BBAAAA Hours   (0x00 - 0x23)              (RW)
41 168 jshamlet
--   0x5   -----AAA Day of Week (0x00 - 0x06)          (RW)
42
--   0x6   -------- Update RTC regs from Shadow Regs   (WO)
43
--   0x7   A------- Update Shadow Regs from RTC regs   (RW)
44
--                  A = Update is Busy
45 224 jshamlet
--
46
-- Revision History
47
-- Author          Date     Change
48
------------------ -------- ---------------------------------------------------
49
-- Seth Henry      04/16/20 Revision block added
50 168 jshamlet
 
51
library ieee;
52
use ieee.std_logic_1164.all;
53
  use ieee.std_logic_unsigned.all;
54
  use ieee.std_logic_arith.all;
55
  use ieee.std_logic_misc.all;
56
 
57
library work;
58
  use work.open8_pkg.all;
59
 
60
entity o8_rtc is
61
generic(
62 210 jshamlet
  Address                    : ADDRESS_TYPE
63 168 jshamlet
);
64
port(
65 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
66 210 jshamlet
  Rd_Data                    : out DATA_TYPE;
67 168 jshamlet
  --
68 210 jshamlet
  Interrupt_PIT              : out std_logic;
69
  Interrupt_RTC              : out std_logic
70 168 jshamlet
);
71
end entity;
72
 
73
architecture behave of o8_rtc is
74
 
75 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
76
  alias Reset                is Open8_Bus.Reset;
77
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
78
 
79 210 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 3)
80
                               := Address(15 downto 3);
81 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
82 210 jshamlet
  signal Addr_Match          : std_logic;
83 168 jshamlet
 
84 223 jshamlet
  alias  Reg_Addr            is Open8_Bus.Address(2 downto 0);
85 210 jshamlet
  signal Reg_Addr_q          : std_logic_vector(2 downto 0);
86 168 jshamlet
 
87 210 jshamlet
  signal Wr_En               : std_logic;
88
  signal Wr_Data_q           : DATA_TYPE;
89
  signal Rd_En               : std_logic;
90 168 jshamlet
 
91
  type PIT_TYPE is record
92 217 jshamlet
    timer_cnt                : DATA_TYPE;
93
    timer_ro                 : std_logic;
94 168 jshamlet
  end record;
95
 
96 217 jshamlet
  signal pit                 : PIT_TYPE;
97 168 jshamlet
 
98
  type RTC_TYPE is record
99 217 jshamlet
    frac                     : std_logic_vector(15 downto 0);
100
    frac_ro                  : std_logic;
101 168 jshamlet
 
102 217 jshamlet
    tens_l                   : std_logic_vector(3 downto 0);
103
    tens_l_ro                : std_logic;
104 168 jshamlet
 
105 217 jshamlet
    tens_u                   : std_logic_vector(3 downto 0);
106
    tens_u_ro                : std_logic;
107 168 jshamlet
 
108 217 jshamlet
    secs_l                   : std_logic_vector(3 downto 0);
109
    secs_l_ro                : std_logic;
110 168 jshamlet
 
111 217 jshamlet
    secs_u                   : std_logic_vector(3 downto 0);
112
    secs_u_ro                : std_logic;
113 168 jshamlet
 
114 217 jshamlet
    mins_l                   : std_logic_vector(3 downto 0);
115
    mins_l_ro                : std_logic;
116 168 jshamlet
 
117 217 jshamlet
    mins_u                   : std_logic_vector(3 downto 0);
118
    mins_u_ro                : std_logic;
119 168 jshamlet
 
120 217 jshamlet
    hours_l                  : std_logic_vector(3 downto 0);
121
    hours_l_ro               : std_logic;
122 168 jshamlet
 
123 217 jshamlet
    hours_u                  : std_logic_vector(3 downto 0);
124
    hours_u_ro               : std_logic;
125 168 jshamlet
 
126 217 jshamlet
    dow                      : std_logic_vector(2 downto 0);
127 168 jshamlet
  end record;
128
 
129 217 jshamlet
  constant DECISEC           : std_logic_vector(15 downto 0) :=
130
                                conv_std_logic_vector(10000,16);
131 168 jshamlet
 
132 217 jshamlet
  signal rtc                 : RTC_TYPE;
133 168 jshamlet
 
134 217 jshamlet
  signal interval            : DATA_TYPE;
135
  signal update_interval     : std_logic;
136 168 jshamlet
 
137 217 jshamlet
  signal shd_tens            : DATA_TYPE;
138
  signal shd_secs            : DATA_TYPE;
139
  signal shd_mins            : DATA_TYPE;
140
  signal shd_hours           : DATA_TYPE;
141
  signal shd_dow             : DATA_TYPE;
142 168 jshamlet
 
143 217 jshamlet
  signal update_rtc          : std_logic;
144
  signal update_shd          : std_logic;
145
  signal update_ctmr         : std_logic_vector(3 downto 0);
146 168 jshamlet
 
147
begin
148
 
149 210 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
150 168 jshamlet
 
151 210 jshamlet
  Interrupt_PIT              <= pit.timer_ro;
152
  Interrupt_RTC              <= rtc.frac_ro;
153 168 jshamlet
 
154
  io_reg: process( Clock, Reset )
155
  begin
156
    if( Reset = Reset_Level )then
157 210 jshamlet
      pit.timer_cnt          <= x"00";
158
      pit.timer_ro           <= '0';
159 168 jshamlet
 
160 210 jshamlet
      rtc.frac               <= DECISEC;
161
      rtc.frac_ro            <= '0';
162 168 jshamlet
 
163 210 jshamlet
      rtc.tens_l             <= (others => '0');
164
      rtc.tens_l_ro          <= '0';
165 168 jshamlet
 
166 210 jshamlet
      rtc.tens_u             <= (others => '0');
167
      rtc.tens_u_ro          <= '0';
168 168 jshamlet
 
169 210 jshamlet
      rtc.secs_l             <= (others => '0');
170
      rtc.secs_l_ro          <= '0';
171 168 jshamlet
 
172 210 jshamlet
      rtc.secs_u             <= (others => '0');
173
      rtc.secs_u_ro          <= '0';
174 168 jshamlet
 
175 210 jshamlet
      rtc.mins_l             <= (others => '0');
176
      rtc.mins_l_ro          <= '0';
177 168 jshamlet
 
178 210 jshamlet
      rtc.mins_u             <= (others => '0');
179
      rtc.mins_u_ro          <= '0';
180 168 jshamlet
 
181 210 jshamlet
      rtc.hours_l            <= (others => '0');
182
      rtc.hours_l_ro         <= '0';
183 168 jshamlet
 
184 210 jshamlet
      rtc.hours_u            <= (others => '0');
185
      rtc.hours_u_ro         <= '0';
186 168 jshamlet
 
187 210 jshamlet
      rtc.dow                <= (others => '0');
188 168 jshamlet
 
189 210 jshamlet
      shd_tens               <= (others => '0');
190
      shd_secs               <= (others => '0');
191
      shd_mins               <= (others => '0');
192
      shd_hours              <= (others => '0');
193
      shd_dow                <= (others => '0');
194 168 jshamlet
 
195 210 jshamlet
      update_rtc             <= '0';
196
      update_shd             <= '0';
197
      update_ctmr            <= (others => '0');
198 168 jshamlet
 
199 210 jshamlet
      interval               <= x"00";
200
      update_interval        <= '0';
201 168 jshamlet
 
202 210 jshamlet
      Wr_Data_q              <= (others => '0');
203
      Reg_Addr_q             <= (others => '0');
204
      Wr_En                  <= '0';
205
      Rd_En                  <= '0';
206
      Rd_Data                <= OPEN8_NULLBUS;
207 168 jshamlet
 
208
    elsif( rising_edge( Clock ) )then
209
 
210
      -- Periodic Interval Timer
211 224 jshamlet
      pit.timer_cnt          <= pit.timer_cnt - uSec_Tick;
212 210 jshamlet
      pit.timer_ro           <= '0';
213
      if( update_interval = '1' )then
214 211 jshamlet
        pit.timer_cnt        <= interval;
215 210 jshamlet
      elsif( or_reduce(pit.timer_cnt) = '0' )then
216
        pit.timer_cnt        <= interval;
217
        pit.timer_ro         <= or_reduce(interval);
218 168 jshamlet
      end if;
219
 
220
      -- Fractional decisecond counter - cycles every 10k microseconds
221 224 jshamlet
      rtc.frac               <= rtc.frac - uSec_Tick;
222 210 jshamlet
      rtc.frac_ro            <= '0';
223 168 jshamlet
      if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
224 210 jshamlet
        rtc.frac             <= DECISEC;
225
        rtc.frac_ro          <= not update_rtc;
226 168 jshamlet
      end if;
227
 
228
      -- Decisecond counter (lower)
229 210 jshamlet
      rtc.tens_l             <= rtc.tens_l + rtc.frac_ro;
230
      rtc.tens_l_ro          <= '0';
231 168 jshamlet
      if( update_rtc = '1' )then
232 210 jshamlet
        rtc.tens_l           <= shd_tens(3 downto 0);
233 168 jshamlet
      elsif( rtc.tens_l > x"9")then
234 210 jshamlet
        rtc.tens_l           <= (others => '0');
235
        rtc.tens_l_ro        <= '1';
236 168 jshamlet
      end if;
237
 
238
      -- Decisecond counter (upper)
239 210 jshamlet
      rtc.tens_u             <= rtc.tens_u + rtc.tens_l_ro;
240
      rtc.tens_u_ro          <= '0';
241 168 jshamlet
      if( update_rtc = '1' )then
242 210 jshamlet
        rtc.tens_u           <= shd_tens(7 downto 4);
243 168 jshamlet
      elsif( rtc.tens_u > x"9")then
244 210 jshamlet
        rtc.tens_u           <= (others => '0');
245
        rtc.tens_u_ro        <= '1';
246 168 jshamlet
      end if;
247
 
248
      -- Second counter (lower)
249 210 jshamlet
      rtc.secs_l             <= rtc.secs_l + rtc.tens_u_ro;
250
      rtc.secs_l_ro          <= '0';
251 168 jshamlet
      if( update_rtc = '1' )then
252 210 jshamlet
        rtc.secs_l           <= shd_secs(3 downto 0);
253 168 jshamlet
      elsif( rtc.secs_l > x"9")then
254 210 jshamlet
        rtc.secs_l           <= (others => '0');
255
        rtc.secs_l_ro        <= '1';
256 168 jshamlet
      end if;
257
 
258
      -- Second counter (upper)
259 210 jshamlet
      rtc.secs_u             <= rtc.secs_u + rtc.secs_l_ro;
260
      rtc.secs_u_ro          <= '0';
261 168 jshamlet
      if( update_rtc = '1' )then
262 210 jshamlet
        rtc.secs_u           <= shd_secs(7 downto 4);
263 168 jshamlet
      elsif( rtc.secs_u > x"5")then
264 210 jshamlet
        rtc.secs_u           <= (others => '0');
265
        rtc.secs_u_ro        <= '1';
266 168 jshamlet
      end if;
267
 
268
      -- Minutes counter (lower)
269 210 jshamlet
      rtc.mins_l             <= rtc.mins_l + rtc.secs_u_ro;
270
      rtc.mins_l_ro          <= '0';
271 168 jshamlet
      if( update_rtc = '1' )then
272 210 jshamlet
        rtc.mins_l           <= shd_mins(3 downto 0);
273 168 jshamlet
      elsif( rtc.mins_l > x"9")then
274 210 jshamlet
        rtc.mins_l           <= (others => '0');
275
        rtc.mins_l_ro        <= '1';
276 168 jshamlet
      end if;
277
 
278
      -- Minutes counter (upper)
279 210 jshamlet
      rtc.mins_u             <= rtc.mins_u + rtc.mins_l_ro;
280
      rtc.mins_u_ro          <= '0';
281 168 jshamlet
      if( update_rtc = '1' )then
282 210 jshamlet
        rtc.mins_u           <= shd_mins(7 downto 4);
283 168 jshamlet
      elsif( rtc.mins_u > x"5")then
284 210 jshamlet
        rtc.mins_u           <= (others => '0');
285
        rtc.mins_u_ro        <= '1';
286 168 jshamlet
      end if;
287
 
288
      -- Hour counter (lower)
289 210 jshamlet
      rtc.hours_l            <= rtc.hours_l + rtc.mins_u_ro;
290
      rtc.hours_l_ro         <= '0';
291 168 jshamlet
      if( update_rtc = '1' )then
292 210 jshamlet
        rtc.hours_l          <= shd_hours(3 downto 0);
293 168 jshamlet
      elsif( rtc.hours_l > x"9")then
294 210 jshamlet
        rtc.hours_l          <= (others => '0');
295
        rtc.hours_l_ro       <= '1';
296 168 jshamlet
      end if;
297
 
298
      -- Hour counter (upper)
299 210 jshamlet
      rtc.hours_u            <= rtc.hours_u + rtc.hours_l_ro;
300 168 jshamlet
      if( update_rtc = '1' )then
301 210 jshamlet
        rtc.hours_u          <= shd_hours(7 downto 4);
302 168 jshamlet
      end if;
303
 
304 210 jshamlet
      rtc.hours_u_ro         <= '0';
305 168 jshamlet
      if( rtc.hours_u >= x"2" and rtc.hours_l > x"3" )then
306 210 jshamlet
        rtc.hours_l          <= (others => '0');
307
        rtc.hours_u          <= (others => '0');
308
        rtc.hours_u_ro       <= '1';
309 168 jshamlet
      end if;
310
 
311
      -- Day of Week counter
312 210 jshamlet
      rtc.dow                <= rtc.dow + rtc.hours_u_ro;
313 168 jshamlet
      if( update_rtc = '1' )then
314 210 jshamlet
        rtc.dow              <= shd_dow(2 downto 0);
315 168 jshamlet
      elsif( rtc.dow = x"07")then
316 210 jshamlet
        rtc.dow              <= (others => '0');
317 168 jshamlet
      end if;
318
 
319
      -- Copy the RTC registers to the shadow registers when the coherency
320
      --  timer is zero (RTC registers are static)
321
      if( update_shd = '1' and or_reduce(update_ctmr) = '0' )then
322 210 jshamlet
        shd_tens             <= rtc.tens_u & rtc.tens_l;
323
        shd_secs             <= rtc.secs_u & rtc.secs_l;
324
        shd_mins             <= rtc.mins_u & rtc.mins_l;
325
        shd_hours            <= rtc.hours_u & rtc.hours_l;
326
        shd_dow              <= "00000" & rtc.dow;
327
        update_shd           <= '0';
328 168 jshamlet
      end if;
329
 
330 210 jshamlet
      update_interval        <= '0';
331 209 jshamlet
 
332 210 jshamlet
      Reg_Addr_q             <= Reg_Addr;
333 223 jshamlet
      Wr_Data_q              <= Open8_Bus.Wr_Data;
334 168 jshamlet
 
335 223 jshamlet
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
336 210 jshamlet
      update_rtc             <= '0';
337 168 jshamlet
      if( Wr_En = '1' )then
338
        case( Reg_Addr_q )is
339
          when "000" =>
340 211 jshamlet
            interval         <= Wr_Data_q;
341 210 jshamlet
            update_interval  <= '1';
342 168 jshamlet
 
343
          when "001" =>
344 210 jshamlet
            shd_tens         <= Wr_Data_q;
345 168 jshamlet
 
346
          when "010" =>
347 210 jshamlet
            shd_secs         <= Wr_Data_q;
348 168 jshamlet
 
349
          when "011" =>
350 210 jshamlet
            shd_mins         <= Wr_Data_q;
351 168 jshamlet
 
352
          when "100" =>
353 210 jshamlet
            shd_hours        <= Wr_Data_q;
354 168 jshamlet
 
355
          when "101" =>
356 210 jshamlet
            shd_dow          <= Wr_Data_q;
357 168 jshamlet
 
358
          when "110" =>
359 210 jshamlet
            update_rtc       <= '1';
360 168 jshamlet
 
361
          when "111" =>
362
            update_shd  <= '1';
363
 
364
          when others => null;
365
        end case;
366
      end if;
367
 
368
      -- Coherency timer - ensures that the shadow registers are updated with
369
      --  valid time data by delaying updates until the rtc registers have
370
      --  finished cascading.
371 210 jshamlet
      update_ctmr            <= update_ctmr - or_reduce(update_ctmr);
372 168 jshamlet
      if( rtc.frac_ro = '1' )then
373 210 jshamlet
        update_ctmr          <= (others => '1');
374 168 jshamlet
      end if;
375
 
376 210 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
377 223 jshamlet
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
378 168 jshamlet
      if( Rd_En = '1' )then
379
        case( Reg_Addr_q )is
380
          when "000" =>
381 210 jshamlet
            Rd_Data          <= interval;
382 168 jshamlet
          when "001" =>
383 210 jshamlet
            Rd_Data          <= shd_tens;
384 168 jshamlet
          when "010" =>
385 210 jshamlet
            Rd_Data          <= shd_secs;
386 168 jshamlet
          when "011" =>
387 210 jshamlet
            Rd_Data          <= shd_mins;
388 168 jshamlet
          when "100" =>
389 210 jshamlet
            Rd_Data          <= shd_hours;
390 168 jshamlet
          when "101" =>
391 210 jshamlet
            Rd_Data          <= shd_dow;
392 168 jshamlet
          when "110" =>
393
            null;
394
          when "111" =>
395 210 jshamlet
            Rd_Data          <= update_shd & "0000000";
396 168 jshamlet
          when others => null;
397
        end case;
398
      end if;
399
 
400
    end if;
401
  end process;
402
 
403
end architecture;

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