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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Blame information for rev 224

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1 192 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_sdlc_if
25
-- Description:  Provides a full memory-mapped SDLC stack with automatic CRC16
26
--                Checksum insertion and integrity checking.
27
--
28
-- Transmit Memory Map
29
-- "0_0000_0000" (0x000) TX Buffer START
30
-- "0_1111_1101" (0x0FD) TX Buffer END
31
-- "0_1111_1110" (0x0FE) Clock Status*
32
-- "0_1111_1111" (0x0FF) TX Length / Status**
33
--
34
-- Receive Memory Map
35
-- "1_0000_0000" (0x100) RX Buffer START
36 196 jshamlet
-- "1_1111_1101" (0x1FD) RX Buffer END
37 201 jshamlet
-- "1_1111_1110" (0x0FE) RX Checksum Status***
38
-- "1_1111_1111" (0x1FF) RX Length   Status****
39 192 jshamlet
--
40 201 jshamlet
-- *    Address 0xFE reports the SDLC bit clock status and updates on changes.
41
--      1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
42
--          0x00. Otherwise, it will report 0xFF if the bitclock is present.
43
--      2) Writing any value to the register will cause the controller to
44
--         silently reset the clock status without causing an interrupt.
45 199 jshamlet
--
46 201 jshamlet
-- **   This location serves as the control/status register for transmit
47
--      1) Writing a value between 1 and 253 will trigger the transmit engine,
48
--          using the write value as the packet length.
49
--      2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
50
--      3) This value will change from the user written value to 0xFF once the
51
--          packet is transmitted to indicate the transmission is complete.
52 199 jshamlet
--
53 201 jshamlet
-- ***  This location serves as the status register for receive checksum test
54
--      1) A value of 0x00 indicates the CRC did NOT match, while a value
55
--         of 0xFF indicates that the recieved CRC matches the calculated CRC.
56
--
57
-- **** This location serves as the status register for the receive
58
--      1) This value is only updated on reception of a full frame, indicated
59
--          by a start followed by a stop flag. Incomplete frames are ignored.
60 204 jshamlet
--      2) If too many bytes are received (buffer overflow), a value of
61 201 jshamlet
--          ERR_LENGTH is written.
62 224 jshamlet
--
63
-- Revision History
64
-- Author          Date     Change
65
------------------ -------- ---------------------------------------------------
66
-- Seth Henry      04/16/20 Revision block added
67 192 jshamlet
 
68
library ieee;
69
  use ieee.std_logic_1164.all;
70
  use ieee.std_logic_unsigned.all;
71
  use ieee.std_logic_arith.all;
72
 
73
library work;
74
  use work.open8_pkg.all;
75
 
76
library work;
77
  use work.sdlc_serial_pkg.all;
78
 
79
entity o8_sdlc_if is
80
generic(
81 202 jshamlet
  Monitor_Enable             : boolean := false;
82 199 jshamlet
  Attach_Monitor_to_CPU_Side : boolean := false;
83 192 jshamlet
  Poly_Init                  : std_logic_vector(15 downto 0) := x"0000";
84
  Set_As_Master              : boolean := true;
85
  Clock_Offset               : integer := 6;
86 224 jshamlet
  BitClock_Frequency         : real := 500000.0;
87
  Clock_Frequency            : real := 100000000.0;
88 192 jshamlet
  Address                    : ADDRESS_TYPE
89
);
90
port(
91 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
92 192 jshamlet
  Rd_Data                    : out DATA_TYPE;
93
  Interrupt                  : out std_logic;
94
  -- Serial IO
95
  SDLC_In                    : in  std_logic;
96
  SDLC_SClk                  : in  std_logic;
97
  SDLC_MClk                  : out std_logic;
98
  SDLC_Out                   : out std_logic
99
);
100
end entity;
101
 
102
architecture behave of o8_sdlc_if is
103
 
104 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
105
  alias Reset                is Open8_Bus.Reset;
106
 
107 192 jshamlet
  constant Base_Addr         : std_logic_vector(15 downto 9)
108
                               := Address(15 downto 9);
109
 
110 223 jshamlet
  alias CPU_Upper_Addr       is Open8_Bus.Address(15 downto 9);
111 205 jshamlet
  signal Base_Addr_Match     : std_logic := '0';
112 192 jshamlet
 
113 223 jshamlet
  alias DP_A_Addr            is Open8_Bus.Address(8 downto 0);
114 205 jshamlet
  signal DP_A_Wr_En          : std_logic := '0';
115 223 jshamlet
  alias  DP_A_Wr_Data        is Open8_Bus.Wr_Data;
116 205 jshamlet
  signal DP_A_Rd_En          : std_logic := '0';
117
  signal DP_A_Rd_Data        : DATA_TYPE := OPEN8_NULLBUS;
118 192 jshamlet
 
119 196 jshamlet
  constant Reg_Sub_Addr      : std_logic_vector(8 downto 1) := x"7F";
120 223 jshamlet
  alias Reg_Upper_Addr       is Open8_Bus.Address(8 downto 1);
121
  alias Reg_Lower_Addr       is Open8_Bus.Address(0);
122 196 jshamlet
 
123
  signal Reg_Addr            : std_logic_vector(8 downto 1) := (others => '0');
124 205 jshamlet
  signal Reg_Sel             : std_logic     := '0';
125
  signal Reg_Wr_En           : std_logic     := '0';
126
  signal Reg_Clk_Sel         : std_logic     := '0';
127
  signal Reg_TxS_Sel         : std_logic     := '0';
128 196 jshamlet
 
129 205 jshamlet
  signal DP_B_Addr           : std_logic_vector(8 downto 0) := (others => '0');
130
  signal DP_B_Wr_Data        : DATA_IN_TYPE  := x"00";
131
  signal DP_B_Wr_En          : std_logic     := '0';
132
  signal DP_B_Rd_Data        : DATA_IN_TYPE  := x"00";
133 192 jshamlet
 
134 202 jshamlet
  signal DP_Port0_Addr       : DATA_IN_TYPE  := x"00";
135
  signal DP_Port0_RWn        : std_logic     := '0';
136
  signal DP_Port0_WrData     : DATA_IN_TYPE  := x"00";
137
  signal DP_Port0_RdData     : DATA_IN_TYPE  := x"00";
138
  signal DP_Port0_Req        : std_logic     := '0';
139
  signal DP_Port0_Ack        : std_logic     := '0';
140
 
141
  signal DP_Port1_Addr       : DATA_IN_TYPE  := x"00";
142
  signal DP_Port1_RWn        : std_logic     := '0';
143
  signal DP_Port1_WrData     : DATA_IN_TYPE  := x"00";
144
  signal DP_Port1_RdData     : DATA_IN_TYPE  := x"00";
145
  signal DP_Port1_Req        : std_logic     := '0';
146
  signal DP_Port1_Ack        : std_logic     := '0';
147
 
148 205 jshamlet
  signal BClk_RE             : std_logic     := '0';
149
  signal BClk_FE             : std_logic     := '0';
150 202 jshamlet
  signal BClk_Okay           : std_logic     := '0';
151 192 jshamlet
 
152 202 jshamlet
  signal TX_Wr_En            : std_logic     := '0';
153
  signal TX_Wr_Flag          : std_logic     := '0';
154
  signal TX_Wr_Data          : DATA_IN_TYPE  := x"00";
155
  signal TX_Req_Next         : std_logic     := '0';
156 192 jshamlet
 
157 202 jshamlet
  signal TX_CRC_Clr          : std_logic     := '0';
158
  signal TX_CRC_En           : std_logic     := '0';
159
  signal TX_CRC_Data         : CRC_OUT_TYPE  := x"0000";
160
  signal TX_CRC_Valid        : std_logic     := '0';
161 192 jshamlet
 
162 202 jshamlet
  signal TX_Interrupt        : std_logic     := '0';
163 192 jshamlet
 
164 202 jshamlet
  signal RX_Valid            : std_logic     := '0';
165
  signal RX_Flag             : std_logic     := '0';
166
  signal RX_Data             : DATA_IN_TYPE;
167
  signal RX_Idle             : std_logic     := '0';
168 192 jshamlet
 
169 202 jshamlet
  signal RX_Frame_Start      : std_logic     := '0';
170
  signal RX_Frame_Stop       : std_logic     := '0';
171
  signal RX_Frame_Valid      : std_logic     := '0';
172
  signal RX_Frame_Data       : DATA_IN_TYPE  := x"00";
173 192 jshamlet
 
174 202 jshamlet
  signal RX_CRC_Valid        : std_logic     := '0';
175
  signal RX_CRC_Data         : CRC_OUT_TYPE  := x"0000";
176
 
177
  signal RX_Interrupt        : std_logic     := '0';
178
 
179 192 jshamlet
begin
180
 
181 202 jshamlet
-- ***************************************************************************
182
-- *          Open8 Bus Interface and Control Register Detection             *
183
-- ***************************************************************************
184
 
185 192 jshamlet
  -- This decode needs to happen immediately, to give the RAM a chance to
186
  --  do the lookup before we have to set Rd_Data
187 205 jshamlet
  Base_Addr_Match            <= '1' when Base_Addr = CPU_Upper_Addr else '0';
188 223 jshamlet
  DP_A_Wr_En                 <= Base_Addr_Match and Open8_Bus.Wr_En;
189 192 jshamlet
 
190 206 jshamlet
  CPU_IF_proc: process( Reset, Clock )
191 192 jshamlet
  begin
192
    if( Reset = Reset_Level )then
193
      Reg_Addr               <= (others => '0');
194
      Reg_Wr_En              <= '0';
195 196 jshamlet
      Reg_Clk_Sel            <= '0';
196
      Reg_TxS_Sel            <= '0';
197 205 jshamlet
      DP_A_Rd_En             <= '0';
198 192 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
199 206 jshamlet
      Interrupt              <= '0';
200 192 jshamlet
    elsif( rising_edge(Clock) )then
201 196 jshamlet
      Reg_Addr               <= Reg_Upper_Addr;
202
      Reg_Sel                <= Reg_Lower_Addr;
203 223 jshamlet
      Reg_Wr_En              <= Base_Addr_Match and Open8_Bus.Wr_En;
204 192 jshamlet
 
205 196 jshamlet
      Reg_Clk_Sel            <= '0';
206
      Reg_TxS_Sel            <= '0';
207 192 jshamlet
      if( Reg_Addr = Reg_Sub_Addr )then
208 196 jshamlet
        Reg_Clk_Sel          <= Reg_Wr_En and not Reg_Sel;
209
        Reg_TxS_Sel          <= Reg_Wr_En and Reg_Sel;
210 192 jshamlet
      end if;
211
 
212 223 jshamlet
      DP_A_Rd_En             <= Base_Addr_Match and Open8_Bus.Rd_En;
213 192 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
214 205 jshamlet
      if( DP_A_Rd_En = '1' )then
215
        Rd_Data              <= DP_A_Rd_Data;
216 192 jshamlet
      end if;
217 206 jshamlet
 
218
      Interrupt              <= RX_Interrupt or TX_Interrupt;
219 192 jshamlet
    end if;
220
  end process;
221
 
222 202 jshamlet
-- ***************************************************************************
223
-- *                     Shared Dual-Port Memory                             *
224
-- ***************************************************************************
225
 
226 200 jshamlet
  U_RAM : entity work.sdlc_dp512b_ram
227 192 jshamlet
  port map(
228
    clock                    => Clock,
229 205 jshamlet
    address_a                => DP_A_Addr,
230
    address_b                => DP_B_Addr,
231
    data_a                   => DP_A_Wr_Data,
232
    data_b                   => DP_B_Wr_Data,
233
    wren_a                   => DP_A_Wr_En,
234
    wren_b                   => DP_B_Wr_En,
235
    q_a                      => DP_A_Rd_Data,
236
    q_b                      => DP_B_Rd_Data
237 192 jshamlet
  );
238
 
239 199 jshamlet
Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
240
 
241
  U_MON: entity work.sdlc_monitor
242
  port map(
243
    clock                    => Clock,
244 205 jshamlet
    address                  => DP_A_Addr,
245
    data                     => DP_A_Wr_Data,
246
    wren                     => DP_A_Wr_En,
247 199 jshamlet
    q                        => open
248
  );
249
end generate;
250
 
251
Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
252
 
253
  U_MON: entity work.sdlc_monitor
254
  port map(
255
    clock                    => Clock,
256 205 jshamlet
    address                  => DP_B_Addr,
257
    data                     => DP_B_Wr_Data,
258
    wren                     => DP_B_Wr_En,
259 199 jshamlet
    q                        => open
260
  );
261
 
262
end generate;
263
 
264 202 jshamlet
-- ***************************************************************************
265
-- *                     Memory Arbitration                                  *
266
-- ***************************************************************************
267
 
268
  U_ARB : entity work.sdlc_serial_arbfsm
269
  generic map(
270
    Reset_Level              => Reset_Level
271
  )
272
  port map(
273
    Clock                    => Clock,
274
    Reset                    => Reset,
275
    --
276 205 jshamlet
    DP_Addr                  => DP_B_Addr,
277
    DP_Wr_Data               => DP_B_Wr_Data,
278
    DP_Wr_En                 => DP_B_Wr_En,
279
    DP_Rd_Data               => DP_B_Rd_Data,
280
    --
281 202 jshamlet
    DP_Port0_Addr            => DP_Port0_Addr,
282
    DP_Port0_RWn             => DP_Port0_RWn,
283
    DP_Port0_WrData          => DP_Port0_WrData,
284
    DP_Port0_RdData          => DP_Port0_RdData,
285
    DP_Port0_Req             => DP_Port0_Req,
286
    DP_Port0_Ack             => DP_Port0_Ack,
287
    --
288
    DP_Port1_Addr            => DP_Port1_Addr,
289
    DP_Port1_RWn             => DP_Port1_RWn,
290
    DP_Port1_WrData          => DP_Port1_WrData,
291
    DP_Port1_RdData          => DP_Port1_RdData,
292
    DP_Port1_Req             => DP_Port1_Req,
293 205 jshamlet
    DP_Port1_Ack             => DP_Port1_Ack
294 202 jshamlet
  );
295
 
296
-- ***************************************************************************
297
-- *                        Serial BitClock                                  *
298
-- ***************************************************************************
299
 
300 192 jshamlet
  U_BCLK : entity work.sdlc_serial_clk
301
  generic map(
302
    Set_As_Master            => Set_As_Master,
303 224 jshamlet
    BitClock_Freq            => BitClock_Frequency,
304 192 jshamlet
    Reset_Level              => Reset_Level,
305 224 jshamlet
    Sys_Freq                 => Clock_Frequency
306 192 jshamlet
  )
307
  port map(
308
    Clock                    => Clock,
309
    Reset                    => Reset,
310
    --
311
    BClk_In                  => SDLC_SClk,
312
    BClk_Out                 => SDLC_MClk,
313
    BClk_FE                  => BClk_FE,
314
    BClk_RE                  => BClk_RE,
315
    BClk_Okay                => BClk_Okay
316
  );
317
 
318 202 jshamlet
-- ***************************************************************************
319
-- *                     Serial Transmit Path                                *
320
-- ***************************************************************************
321
 
322
  U_TXFSM: entity work.sdlc_serial_txfsm
323 192 jshamlet
  generic map(
324
    Reset_Level              => Reset_Level
325
  )
326
  port map(
327
    Clock                    => Clock,
328
    Reset                    => Reset,
329
    --
330
    BClk_Okay                => BClk_Okay,
331
    --
332 196 jshamlet
    Reg_Clk_Sel              => Reg_Clk_Sel,
333
    Reg_TxS_Sel              => Reg_TxS_Sel,
334 192 jshamlet
    --
335 202 jshamlet
    DP_Port0_Addr            => DP_Port0_Addr,
336
    DP_Port0_RWn             => DP_Port0_RWn,
337
    DP_Port0_WrData          => DP_Port0_WrData,
338
    DP_Port0_RdData          => DP_Port0_RdData,
339
    DP_Port0_Req             => DP_Port0_Req,
340
    DP_Port0_Ack             => DP_Port0_Ack,
341 192 jshamlet
    --
342
    TX_Wr_En                 => TX_Wr_En,
343
    TX_Wr_Flag               => TX_Wr_Flag,
344
    TX_Wr_Data               => TX_Wr_Data,
345
    TX_Req_Next              => TX_Req_Next,
346
    --
347
    TX_CRC_Clr               => TX_CRC_Clr,
348
    TX_CRC_En                => TX_CRC_En,
349
    TX_CRC_Data              => TX_CRC_Data,
350
    TX_CRC_Valid             => TX_CRC_Valid,
351
    --
352 202 jshamlet
    TX_Interrupt             => TX_Interrupt
353
  );
354
 
355
  U_TX_CRC : entity work.sdlc_crc16_ccitt
356
  generic map(
357
    Poly_Init                => Poly_Init,
358
    Reset_Level              => Reset_Level
359
  )
360
  port map(
361
    Clock                    => Clock,
362
    Reset                    => Reset,
363 192 jshamlet
    --
364 202 jshamlet
    Clear                    => TX_CRC_Clr,
365
    Wr_En                    => TX_CRC_En,
366
    Wr_Data                  => TX_Wr_Data,
367 192 jshamlet
    --
368 202 jshamlet
    CRC16_Valid              => TX_CRC_Valid,
369
    CRC16_Out                => TX_CRC_Data
370 192 jshamlet
  );
371
 
372
  U_TX_SER : entity work.sdlc_serial_tx
373
  generic map(
374
    Reset_Level              => Reset_Level
375
  )
376
  port map(
377
    Clock                    => Clock,
378
    Reset                    => Reset,
379
    --
380
    BClk_FE                  => BClk_FE,
381
    BClk_RE                  => BClk_RE,
382
    BClk_Okay                => BClk_Okay,
383
    --
384
    TX_En                    => TX_Wr_En,
385
    TX_FSS_Flag              => TX_Wr_Flag,
386
    TX_Data                  => TX_Wr_Data,
387
    TX_Req_Next              => TX_Req_Next,
388
    --
389
    Serial_Out               => SDLC_Out
390
  );
391
 
392 202 jshamlet
-- ***************************************************************************
393
-- *                     Serial Receive Path                                 *
394
-- ***************************************************************************
395 192 jshamlet
 
396
  U_RX_SER : entity work.sdlc_serial_rx
397
  generic map(
398
    Set_As_Master            => Set_As_Master,
399
    Clock_Offset             => Clock_Offset,
400
    Reset_Level              => Reset_Level
401
  )
402
  port map(
403
    Clock                    => Clock,
404
    Reset                    => Reset,
405
    --
406
    BClk_RE                  => BClk_RE,
407
    BClk_Okay                => BClk_Okay,
408
    --
409
    Serial_In                => SDLC_In,
410
    --
411
    RX_Valid                 => RX_Valid,
412
    RX_Flag                  => RX_Flag,
413
    RX_Data                  => RX_Data,
414
    RX_Idle                  => RX_Idle
415
  );
416
 
417 202 jshamlet
  U_RX_PKT : entity work.sdlc_serial_frame
418
  generic map(
419
    Reset_Level              => Reset_Level
420
  )
421
  port map(
422
    Clock                    => Clock,
423
    Reset                    => Reset,
424
    --
425
    RX_Valid                 => RX_Valid,
426
    RX_Flag                  => RX_Flag,
427
    RX_Data                  => RX_Data,
428
    RX_Idle                  => RX_Idle,
429
    --
430
    RX_Frame_Start           => RX_Frame_Start,
431
    RX_Frame_Stop            => RX_Frame_Stop,
432
    RX_Frame_Valid           => RX_Frame_Valid,
433
    RX_Frame_Data            => RX_Frame_Data
434
  );
435
 
436 192 jshamlet
  U_RX_CRC : entity work.sdlc_crc16_ccitt
437
  generic map(
438
    Poly_Init                => Poly_Init,
439
    Reset_Level              => Reset_Level
440
  )
441
  port map(
442
    Clock                    => Clock,
443
    Reset                    => Reset,
444
    --
445 202 jshamlet
    Clear                    => RX_Frame_Start,
446
    Wr_En                    => RX_Frame_Valid,
447
    Wr_Data                  => RX_Frame_Data,
448 192 jshamlet
    --
449 202 jshamlet
    CRC16_Valid              => RX_CRC_Valid,
450
    CRC16_Out                => RX_CRC_Data
451 192 jshamlet
  );
452
 
453 202 jshamlet
  U_RX_FSM : entity work.sdlc_serial_rxfsm
454
  generic map(
455
    Reset_Level              => Reset_Level
456
  )
457
  port map(
458
    Clock                    => Clock,
459
    Reset                    => Reset,
460
    --
461
    BClk_Okay                => BClk_Okay,
462
    --
463
    DP_Port1_Addr            => DP_Port1_Addr,
464
    DP_Port1_RWn             => DP_Port1_RWn,
465
    DP_Port1_WrData          => DP_Port1_WrData,
466
    DP_Port1_RdData          => DP_Port1_RdData,
467
    DP_Port1_Req             => DP_Port1_Req,
468
    DP_Port1_Ack             => DP_Port1_Ack,
469
    --
470
    RX_CRC_Valid             => RX_CRC_Valid,
471
    RX_CRC_Data              => RX_CRC_Data,
472
    --
473
    RX_Frame_Start           => RX_Frame_Start,
474
    RX_Frame_Stop            => RX_Frame_Stop,
475
    RX_Frame_Valid           => RX_Frame_Valid,
476
    RX_Frame_Data            => RX_Frame_Data,
477
    --
478
    RX_Interrupt             => RX_Interrupt
479
  );
480
 
481 192 jshamlet
end architecture;

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