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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Blame information for rev 244

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1 192 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_sdlc_if
25
-- Description:  Provides a full memory-mapped SDLC stack with automatic CRC16
26
--                Checksum insertion and integrity checking.
27
--
28
-- Transmit Memory Map
29
-- "0_0000_0000" (0x000) TX Buffer START
30
-- "0_1111_1101" (0x0FD) TX Buffer END
31
-- "0_1111_1110" (0x0FE) Clock Status*
32
-- "0_1111_1111" (0x0FF) TX Length / Status**
33
--
34
-- Receive Memory Map
35
-- "1_0000_0000" (0x100) RX Buffer START
36 196 jshamlet
-- "1_1111_1101" (0x1FD) RX Buffer END
37 201 jshamlet
-- "1_1111_1110" (0x0FE) RX Checksum Status***
38
-- "1_1111_1111" (0x1FF) RX Length   Status****
39 192 jshamlet
--
40 201 jshamlet
-- *    Address 0xFE reports the SDLC bit clock status and updates on changes.
41
--      1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
42
--          0x00. Otherwise, it will report 0xFF if the bitclock is present.
43
--      2) Writing any value to the register will cause the controller to
44
--         silently reset the clock status without causing an interrupt.
45 199 jshamlet
--
46 201 jshamlet
-- **   This location serves as the control/status register for transmit
47
--      1) Writing a value between 1 and 253 will trigger the transmit engine,
48
--          using the write value as the packet length.
49
--      2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
50
--      3) This value will change from the user written value to 0xFF once the
51
--          packet is transmitted to indicate the transmission is complete.
52 199 jshamlet
--
53 201 jshamlet
-- ***  This location serves as the status register for receive checksum test
54
--      1) A value of 0x00 indicates the CRC did NOT match, while a value
55
--         of 0xFF indicates that the recieved CRC matches the calculated CRC.
56
--
57
-- **** This location serves as the status register for the receive
58
--      1) This value is only updated on reception of a full frame, indicated
59
--          by a start followed by a stop flag. Incomplete frames are ignored.
60 204 jshamlet
--      2) If too many bytes are received (buffer overflow), a value of
61 201 jshamlet
--          ERR_LENGTH is written.
62 224 jshamlet
--
63
-- Revision History
64
-- Author          Date     Change
65
------------------ -------- ---------------------------------------------------
66
-- Seth Henry      04/16/20 Revision block added
67 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
68 192 jshamlet
 
69
library ieee;
70
  use ieee.std_logic_1164.all;
71
  use ieee.std_logic_unsigned.all;
72
  use ieee.std_logic_arith.all;
73
 
74
library work;
75
  use work.open8_pkg.all;
76
 
77
library work;
78
  use work.sdlc_serial_pkg.all;
79
 
80
entity o8_sdlc_if is
81
generic(
82 202 jshamlet
  Monitor_Enable             : boolean := false;
83 199 jshamlet
  Attach_Monitor_to_CPU_Side : boolean := false;
84 192 jshamlet
  Poly_Init                  : std_logic_vector(15 downto 0) := x"0000";
85
  Set_As_Master              : boolean := true;
86
  Clock_Offset               : integer := 6;
87 224 jshamlet
  BitClock_Frequency         : real := 500000.0;
88
  Clock_Frequency            : real := 100000000.0;
89 192 jshamlet
  Address                    : ADDRESS_TYPE
90
);
91
port(
92 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
93 244 jshamlet
  Write_Qual                 : in  std_logic := '1';
94 192 jshamlet
  Rd_Data                    : out DATA_TYPE;
95
  Interrupt                  : out std_logic;
96
  -- Serial IO
97
  SDLC_In                    : in  std_logic;
98
  SDLC_SClk                  : in  std_logic;
99
  SDLC_MClk                  : out std_logic;
100
  SDLC_Out                   : out std_logic
101
);
102
end entity;
103
 
104
architecture behave of o8_sdlc_if is
105
 
106 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
107
  alias Reset                is Open8_Bus.Reset;
108
 
109 192 jshamlet
  constant Base_Addr         : std_logic_vector(15 downto 9)
110
                               := Address(15 downto 9);
111
 
112 223 jshamlet
  alias CPU_Upper_Addr       is Open8_Bus.Address(15 downto 9);
113 205 jshamlet
  signal Base_Addr_Match     : std_logic := '0';
114 192 jshamlet
 
115 244 jshamlet
  alias  DP_A_Addr           is Open8_Bus.Address(8 downto 0);
116 205 jshamlet
  signal DP_A_Wr_En          : std_logic := '0';
117 223 jshamlet
  alias  DP_A_Wr_Data        is Open8_Bus.Wr_Data;
118 244 jshamlet
  signal DP_A_Rd_En_d        : std_logic := '0';
119
  signal DP_A_Rd_En_q        : std_logic := '0';
120 205 jshamlet
  signal DP_A_Rd_Data        : DATA_TYPE := OPEN8_NULLBUS;
121 192 jshamlet
 
122 196 jshamlet
  constant Reg_Sub_Addr      : std_logic_vector(8 downto 1) := x"7F";
123 223 jshamlet
  alias Reg_Upper_Addr       is Open8_Bus.Address(8 downto 1);
124
  alias Reg_Lower_Addr       is Open8_Bus.Address(0);
125 196 jshamlet
 
126
  signal Reg_Addr            : std_logic_vector(8 downto 1) := (others => '0');
127 205 jshamlet
  signal Reg_Sel             : std_logic     := '0';
128 244 jshamlet
  signal Reg_Wr_En_d         : std_logic     := '0';
129
  signal Reg_Wr_En_q         : std_logic     := '0';
130 205 jshamlet
  signal Reg_Clk_Sel         : std_logic     := '0';
131
  signal Reg_TxS_Sel         : std_logic     := '0';
132 196 jshamlet
 
133 205 jshamlet
  signal DP_B_Addr           : std_logic_vector(8 downto 0) := (others => '0');
134
  signal DP_B_Wr_Data        : DATA_IN_TYPE  := x"00";
135
  signal DP_B_Wr_En          : std_logic     := '0';
136
  signal DP_B_Rd_Data        : DATA_IN_TYPE  := x"00";
137 192 jshamlet
 
138 202 jshamlet
  signal DP_Port0_Addr       : DATA_IN_TYPE  := x"00";
139
  signal DP_Port0_RWn        : std_logic     := '0';
140
  signal DP_Port0_WrData     : DATA_IN_TYPE  := x"00";
141
  signal DP_Port0_RdData     : DATA_IN_TYPE  := x"00";
142
  signal DP_Port0_Req        : std_logic     := '0';
143
  signal DP_Port0_Ack        : std_logic     := '0';
144
 
145
  signal DP_Port1_Addr       : DATA_IN_TYPE  := x"00";
146
  signal DP_Port1_RWn        : std_logic     := '0';
147
  signal DP_Port1_WrData     : DATA_IN_TYPE  := x"00";
148
  signal DP_Port1_RdData     : DATA_IN_TYPE  := x"00";
149
  signal DP_Port1_Req        : std_logic     := '0';
150
  signal DP_Port1_Ack        : std_logic     := '0';
151
 
152 205 jshamlet
  signal BClk_RE             : std_logic     := '0';
153
  signal BClk_FE             : std_logic     := '0';
154 202 jshamlet
  signal BClk_Okay           : std_logic     := '0';
155 192 jshamlet
 
156 202 jshamlet
  signal TX_Wr_En            : std_logic     := '0';
157
  signal TX_Wr_Flag          : std_logic     := '0';
158
  signal TX_Wr_Data          : DATA_IN_TYPE  := x"00";
159
  signal TX_Req_Next         : std_logic     := '0';
160 192 jshamlet
 
161 202 jshamlet
  signal TX_CRC_Clr          : std_logic     := '0';
162
  signal TX_CRC_En           : std_logic     := '0';
163
  signal TX_CRC_Data         : CRC_OUT_TYPE  := x"0000";
164
  signal TX_CRC_Valid        : std_logic     := '0';
165 192 jshamlet
 
166 202 jshamlet
  signal TX_Interrupt        : std_logic     := '0';
167 192 jshamlet
 
168 202 jshamlet
  signal RX_Valid            : std_logic     := '0';
169
  signal RX_Flag             : std_logic     := '0';
170
  signal RX_Data             : DATA_IN_TYPE;
171
  signal RX_Idle             : std_logic     := '0';
172 192 jshamlet
 
173 202 jshamlet
  signal RX_Frame_Start      : std_logic     := '0';
174
  signal RX_Frame_Stop       : std_logic     := '0';
175
  signal RX_Frame_Valid      : std_logic     := '0';
176
  signal RX_Frame_Data       : DATA_IN_TYPE  := x"00";
177 192 jshamlet
 
178 202 jshamlet
  signal RX_CRC_Valid        : std_logic     := '0';
179
  signal RX_CRC_Data         : CRC_OUT_TYPE  := x"0000";
180
 
181
  signal RX_Interrupt        : std_logic     := '0';
182
 
183 192 jshamlet
begin
184
 
185 202 jshamlet
-- ***************************************************************************
186
-- *          Open8 Bus Interface and Control Register Detection             *
187
-- ***************************************************************************
188
 
189 192 jshamlet
  -- This decode needs to happen immediately, to give the RAM a chance to
190
  --  do the lookup before we have to set Rd_Data
191 205 jshamlet
  Base_Addr_Match            <= '1' when Base_Addr = CPU_Upper_Addr else '0';
192 244 jshamlet
  Reg_Wr_En_d                <= Base_Addr_Match and
193
                                Open8_Bus.Wr_En and
194
                                Write_Qual;
195 192 jshamlet
 
196 244 jshamlet
  DP_A_Wr_En                 <= Base_Addr_Match and
197
                                Open8_Bus.Wr_En and
198
                                Write_Qual;
199
 
200
  DP_A_Rd_En_d               <= Base_Addr_Match and Open8_Bus.Rd_En;
201
 
202 206 jshamlet
  CPU_IF_proc: process( Reset, Clock )
203 192 jshamlet
  begin
204
    if( Reset = Reset_Level )then
205
      Reg_Addr               <= (others => '0');
206 244 jshamlet
      Reg_Wr_En_q            <= '0';
207 196 jshamlet
      Reg_Clk_Sel            <= '0';
208
      Reg_TxS_Sel            <= '0';
209 244 jshamlet
      DP_A_Rd_En_q           <= '0';
210 192 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
211 206 jshamlet
      Interrupt              <= '0';
212 192 jshamlet
    elsif( rising_edge(Clock) )then
213 196 jshamlet
      Reg_Addr               <= Reg_Upper_Addr;
214
      Reg_Sel                <= Reg_Lower_Addr;
215 244 jshamlet
      Reg_Wr_En_q            <= Reg_Wr_En_d;
216 192 jshamlet
 
217 196 jshamlet
      Reg_Clk_Sel            <= '0';
218
      Reg_TxS_Sel            <= '0';
219 192 jshamlet
      if( Reg_Addr = Reg_Sub_Addr )then
220 244 jshamlet
        Reg_Clk_Sel          <= Reg_Wr_En_q and not Reg_Sel;
221
        Reg_TxS_Sel          <= Reg_Wr_En_q and Reg_Sel;
222 192 jshamlet
      end if;
223
 
224 244 jshamlet
      DP_A_Rd_En_q           <= DP_A_Rd_En_d;
225 192 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
226 244 jshamlet
      if( DP_A_Rd_En_q = '1' )then
227 205 jshamlet
        Rd_Data              <= DP_A_Rd_Data;
228 192 jshamlet
      end if;
229 206 jshamlet
 
230
      Interrupt              <= RX_Interrupt or TX_Interrupt;
231 192 jshamlet
    end if;
232
  end process;
233
 
234 202 jshamlet
-- ***************************************************************************
235
-- *                     Shared Dual-Port Memory                             *
236
-- ***************************************************************************
237
 
238 200 jshamlet
  U_RAM : entity work.sdlc_dp512b_ram
239 192 jshamlet
  port map(
240
    clock                    => Clock,
241 205 jshamlet
    address_a                => DP_A_Addr,
242
    address_b                => DP_B_Addr,
243
    data_a                   => DP_A_Wr_Data,
244
    data_b                   => DP_B_Wr_Data,
245
    wren_a                   => DP_A_Wr_En,
246
    wren_b                   => DP_B_Wr_En,
247
    q_a                      => DP_A_Rd_Data,
248
    q_b                      => DP_B_Rd_Data
249 192 jshamlet
  );
250
 
251 199 jshamlet
Attach_to_CPU_side: if( Monitor_Enable and Attach_Monitor_to_CPU_Side )generate
252
 
253
  U_MON: entity work.sdlc_monitor
254
  port map(
255
    clock                    => Clock,
256 205 jshamlet
    address                  => DP_A_Addr,
257
    data                     => DP_A_Wr_Data,
258
    wren                     => DP_A_Wr_En,
259 199 jshamlet
    q                        => open
260
  );
261
end generate;
262
 
263
Attach_to_Int_side: if( Monitor_Enable and not Attach_Monitor_to_CPU_Side )generate
264
 
265
  U_MON: entity work.sdlc_monitor
266
  port map(
267
    clock                    => Clock,
268 205 jshamlet
    address                  => DP_B_Addr,
269
    data                     => DP_B_Wr_Data,
270
    wren                     => DP_B_Wr_En,
271 199 jshamlet
    q                        => open
272
  );
273
 
274
end generate;
275
 
276 202 jshamlet
-- ***************************************************************************
277
-- *                     Memory Arbitration                                  *
278
-- ***************************************************************************
279
 
280
  U_ARB : entity work.sdlc_serial_arbfsm
281
  generic map(
282
    Reset_Level              => Reset_Level
283
  )
284
  port map(
285
    Clock                    => Clock,
286
    Reset                    => Reset,
287
    --
288 205 jshamlet
    DP_Addr                  => DP_B_Addr,
289
    DP_Wr_Data               => DP_B_Wr_Data,
290
    DP_Wr_En                 => DP_B_Wr_En,
291
    DP_Rd_Data               => DP_B_Rd_Data,
292
    --
293 202 jshamlet
    DP_Port0_Addr            => DP_Port0_Addr,
294
    DP_Port0_RWn             => DP_Port0_RWn,
295
    DP_Port0_WrData          => DP_Port0_WrData,
296
    DP_Port0_RdData          => DP_Port0_RdData,
297
    DP_Port0_Req             => DP_Port0_Req,
298
    DP_Port0_Ack             => DP_Port0_Ack,
299
    --
300
    DP_Port1_Addr            => DP_Port1_Addr,
301
    DP_Port1_RWn             => DP_Port1_RWn,
302
    DP_Port1_WrData          => DP_Port1_WrData,
303
    DP_Port1_RdData          => DP_Port1_RdData,
304
    DP_Port1_Req             => DP_Port1_Req,
305 205 jshamlet
    DP_Port1_Ack             => DP_Port1_Ack
306 202 jshamlet
  );
307
 
308
-- ***************************************************************************
309
-- *                        Serial BitClock                                  *
310
-- ***************************************************************************
311
 
312 192 jshamlet
  U_BCLK : entity work.sdlc_serial_clk
313
  generic map(
314
    Set_As_Master            => Set_As_Master,
315 224 jshamlet
    BitClock_Freq            => BitClock_Frequency,
316 192 jshamlet
    Reset_Level              => Reset_Level,
317 224 jshamlet
    Sys_Freq                 => Clock_Frequency
318 192 jshamlet
  )
319
  port map(
320
    Clock                    => Clock,
321
    Reset                    => Reset,
322
    --
323
    BClk_In                  => SDLC_SClk,
324
    BClk_Out                 => SDLC_MClk,
325
    BClk_FE                  => BClk_FE,
326
    BClk_RE                  => BClk_RE,
327
    BClk_Okay                => BClk_Okay
328
  );
329
 
330 202 jshamlet
-- ***************************************************************************
331
-- *                     Serial Transmit Path                                *
332
-- ***************************************************************************
333
 
334
  U_TXFSM: entity work.sdlc_serial_txfsm
335 192 jshamlet
  generic map(
336
    Reset_Level              => Reset_Level
337
  )
338
  port map(
339
    Clock                    => Clock,
340
    Reset                    => Reset,
341
    --
342
    BClk_Okay                => BClk_Okay,
343
    --
344 196 jshamlet
    Reg_Clk_Sel              => Reg_Clk_Sel,
345
    Reg_TxS_Sel              => Reg_TxS_Sel,
346 192 jshamlet
    --
347 202 jshamlet
    DP_Port0_Addr            => DP_Port0_Addr,
348
    DP_Port0_RWn             => DP_Port0_RWn,
349
    DP_Port0_WrData          => DP_Port0_WrData,
350
    DP_Port0_RdData          => DP_Port0_RdData,
351
    DP_Port0_Req             => DP_Port0_Req,
352
    DP_Port0_Ack             => DP_Port0_Ack,
353 192 jshamlet
    --
354
    TX_Wr_En                 => TX_Wr_En,
355
    TX_Wr_Flag               => TX_Wr_Flag,
356
    TX_Wr_Data               => TX_Wr_Data,
357
    TX_Req_Next              => TX_Req_Next,
358
    --
359
    TX_CRC_Clr               => TX_CRC_Clr,
360
    TX_CRC_En                => TX_CRC_En,
361
    TX_CRC_Data              => TX_CRC_Data,
362
    TX_CRC_Valid             => TX_CRC_Valid,
363
    --
364 202 jshamlet
    TX_Interrupt             => TX_Interrupt
365
  );
366
 
367
  U_TX_CRC : entity work.sdlc_crc16_ccitt
368
  generic map(
369
    Poly_Init                => Poly_Init,
370
    Reset_Level              => Reset_Level
371
  )
372
  port map(
373
    Clock                    => Clock,
374
    Reset                    => Reset,
375 192 jshamlet
    --
376 202 jshamlet
    Clear                    => TX_CRC_Clr,
377
    Wr_En                    => TX_CRC_En,
378
    Wr_Data                  => TX_Wr_Data,
379 192 jshamlet
    --
380 202 jshamlet
    CRC16_Valid              => TX_CRC_Valid,
381
    CRC16_Out                => TX_CRC_Data
382 192 jshamlet
  );
383
 
384
  U_TX_SER : entity work.sdlc_serial_tx
385
  generic map(
386
    Reset_Level              => Reset_Level
387
  )
388
  port map(
389
    Clock                    => Clock,
390
    Reset                    => Reset,
391
    --
392
    BClk_FE                  => BClk_FE,
393
    BClk_RE                  => BClk_RE,
394
    BClk_Okay                => BClk_Okay,
395
    --
396
    TX_En                    => TX_Wr_En,
397
    TX_FSS_Flag              => TX_Wr_Flag,
398
    TX_Data                  => TX_Wr_Data,
399
    TX_Req_Next              => TX_Req_Next,
400
    --
401
    Serial_Out               => SDLC_Out
402
  );
403
 
404 202 jshamlet
-- ***************************************************************************
405
-- *                     Serial Receive Path                                 *
406
-- ***************************************************************************
407 192 jshamlet
 
408
  U_RX_SER : entity work.sdlc_serial_rx
409
  generic map(
410
    Set_As_Master            => Set_As_Master,
411
    Clock_Offset             => Clock_Offset,
412
    Reset_Level              => Reset_Level
413
  )
414
  port map(
415
    Clock                    => Clock,
416
    Reset                    => Reset,
417
    --
418
    BClk_RE                  => BClk_RE,
419
    BClk_Okay                => BClk_Okay,
420
    --
421
    Serial_In                => SDLC_In,
422
    --
423
    RX_Valid                 => RX_Valid,
424
    RX_Flag                  => RX_Flag,
425
    RX_Data                  => RX_Data,
426
    RX_Idle                  => RX_Idle
427
  );
428
 
429 202 jshamlet
  U_RX_PKT : entity work.sdlc_serial_frame
430
  generic map(
431
    Reset_Level              => Reset_Level
432
  )
433
  port map(
434
    Clock                    => Clock,
435
    Reset                    => Reset,
436
    --
437
    RX_Valid                 => RX_Valid,
438
    RX_Flag                  => RX_Flag,
439
    RX_Data                  => RX_Data,
440
    RX_Idle                  => RX_Idle,
441
    --
442
    RX_Frame_Start           => RX_Frame_Start,
443
    RX_Frame_Stop            => RX_Frame_Stop,
444
    RX_Frame_Valid           => RX_Frame_Valid,
445
    RX_Frame_Data            => RX_Frame_Data
446
  );
447
 
448 192 jshamlet
  U_RX_CRC : entity work.sdlc_crc16_ccitt
449
  generic map(
450
    Poly_Init                => Poly_Init,
451
    Reset_Level              => Reset_Level
452
  )
453
  port map(
454
    Clock                    => Clock,
455
    Reset                    => Reset,
456
    --
457 202 jshamlet
    Clear                    => RX_Frame_Start,
458
    Wr_En                    => RX_Frame_Valid,
459
    Wr_Data                  => RX_Frame_Data,
460 192 jshamlet
    --
461 202 jshamlet
    CRC16_Valid              => RX_CRC_Valid,
462
    CRC16_Out                => RX_CRC_Data
463 192 jshamlet
  );
464
 
465 202 jshamlet
  U_RX_FSM : entity work.sdlc_serial_rxfsm
466
  generic map(
467
    Reset_Level              => Reset_Level
468
  )
469
  port map(
470
    Clock                    => Clock,
471
    Reset                    => Reset,
472
    --
473
    BClk_Okay                => BClk_Okay,
474
    --
475
    DP_Port1_Addr            => DP_Port1_Addr,
476
    DP_Port1_RWn             => DP_Port1_RWn,
477
    DP_Port1_WrData          => DP_Port1_WrData,
478
    DP_Port1_RdData          => DP_Port1_RdData,
479
    DP_Port1_Req             => DP_Port1_Req,
480
    DP_Port1_Ack             => DP_Port1_Ack,
481
    --
482
    RX_CRC_Valid             => RX_CRC_Valid,
483
    RX_CRC_Data              => RX_CRC_Data,
484
    --
485
    RX_Frame_Start           => RX_Frame_Start,
486
    RX_Frame_Stop            => RX_Frame_Stop,
487
    RX_Frame_Valid           => RX_Frame_Valid,
488
    RX_Frame_Data            => RX_Frame_Data,
489
    --
490
    RX_Interrupt             => RX_Interrupt
491
  );
492
 
493 192 jshamlet
end architecture;

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