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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Blame information for rev 287

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1 192 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_sdlc_if
25
-- Description:  Provides a full memory-mapped SDLC stack with automatic CRC16
26 273 jshamlet
--                Checksum insertion and integrity checking. Note that this
27
--                entity ONLY provides packet framing and checksum calculation.
28 192 jshamlet
--
29
-- Transmit Memory Map
30
-- "0_0000_0000" (0x000) TX Buffer START
31
-- "0_1111_1101" (0x0FD) TX Buffer END
32
-- "0_1111_1110" (0x0FE) Clock Status*
33
-- "0_1111_1111" (0x0FF) TX Length / Status**
34
--
35
-- Receive Memory Map
36
-- "1_0000_0000" (0x100) RX Buffer START
37 196 jshamlet
-- "1_1111_1101" (0x1FD) RX Buffer END
38 201 jshamlet
-- "1_1111_1110" (0x0FE) RX Checksum Status***
39
-- "1_1111_1111" (0x1FF) RX Length   Status****
40 192 jshamlet
--
41 201 jshamlet
-- *    Address 0xFE reports the SDLC bit clock status and updates on changes.
42
--      1) If BClk_Okay = '0' (Bitclock is NOT present), the field will report
43
--          0x00. Otherwise, it will report 0xFF if the bitclock is present.
44
--      2) Writing any value to the register will cause the controller to
45
--         silently reset the clock status without causing an interrupt.
46 199 jshamlet
--
47 201 jshamlet
-- **   This location serves as the control/status register for transmit
48
--      1) Writing a value between 1 and 253 will trigger the transmit engine,
49
--          using the write value as the packet length.
50
--      2) Values 0x00, 0xFE, or 0xFF are invalid, and will be ignored.
51
--      3) This value will change from the user written value to 0xFF once the
52
--          packet is transmitted to indicate the transmission is complete.
53 199 jshamlet
--
54 201 jshamlet
-- ***  This location serves as the status register for receive checksum test
55
--      1) A value of 0x00 indicates the CRC did NOT match, while a value
56
--         of 0xFF indicates that the recieved CRC matches the calculated CRC.
57
--
58
-- **** This location serves as the status register for the receive
59
--      1) This value is only updated on reception of a full frame, indicated
60
--          by a start followed by a stop flag. Incomplete frames are ignored.
61 204 jshamlet
--      2) If too many bytes are received (buffer overflow), a value of
62 201 jshamlet
--          ERR_LENGTH is written.
63 224 jshamlet
--
64
-- Revision History
65
-- Author          Date     Change
66
------------------ -------- ---------------------------------------------------
67 278 jshamlet
-- Seth Henry      12/09/20 Created from merged sub-entities into flat file
68 192 jshamlet
 
69
library ieee;
70
  use ieee.std_logic_1164.all;
71
  use ieee.std_logic_unsigned.all;
72
  use ieee.std_logic_arith.all;
73 278 jshamlet
  use ieee.std_logic_misc.all;
74 192 jshamlet
 
75
library work;
76
  use work.open8_pkg.all;
77
 
78
entity o8_sdlc_if is
79
generic(
80
  Poly_Init                  : std_logic_vector(15 downto 0) := x"0000";
81
  Set_As_Master              : boolean := true;
82
  Clock_Offset               : integer := 6;
83 224 jshamlet
  BitClock_Frequency         : real := 500000.0;
84
  Clock_Frequency            : real := 100000000.0;
85 192 jshamlet
  Address                    : ADDRESS_TYPE
86
);
87
port(
88 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
89 244 jshamlet
  Write_Qual                 : in  std_logic := '1';
90 192 jshamlet
  Rd_Data                    : out DATA_TYPE;
91 263 jshamlet
  TX_Interrupt               : out std_logic;
92
  RX_Interrupt               : out std_logic;
93 192 jshamlet
  -- Serial IO
94
  SDLC_In                    : in  std_logic;
95
  SDLC_SClk                  : in  std_logic;
96
  SDLC_MClk                  : out std_logic;
97
  SDLC_Out                   : out std_logic
98
);
99
end entity;
100
 
101
architecture behave of o8_sdlc_if is
102
 
103 278 jshamlet
  -- convenient subtypes & constants
104
  subtype CRC_TYPE           is std_logic_vector(15 downto 0);
105
 
106
  -- Bus interface
107 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
108
  alias Reset                is Open8_Bus.Reset;
109
 
110 192 jshamlet
  constant Base_Addr         : std_logic_vector(15 downto 9)
111
                               := Address(15 downto 9);
112
 
113 223 jshamlet
  alias CPU_Upper_Addr       is Open8_Bus.Address(15 downto 9);
114 205 jshamlet
  signal Base_Addr_Match     : std_logic := '0';
115 192 jshamlet
 
116 244 jshamlet
  alias  DP_A_Addr           is Open8_Bus.Address(8 downto 0);
117 205 jshamlet
  signal DP_A_Wr_En          : std_logic := '0';
118 223 jshamlet
  alias  DP_A_Wr_Data        is Open8_Bus.Wr_Data;
119 244 jshamlet
  signal DP_A_Rd_En_d        : std_logic := '0';
120
  signal DP_A_Rd_En_q        : std_logic := '0';
121 205 jshamlet
  signal DP_A_Rd_Data        : DATA_TYPE := OPEN8_NULLBUS;
122 192 jshamlet
 
123 196 jshamlet
  constant Reg_Sub_Addr      : std_logic_vector(8 downto 1) := x"7F";
124 223 jshamlet
  alias Reg_Upper_Addr       is Open8_Bus.Address(8 downto 1);
125
  alias Reg_Lower_Addr       is Open8_Bus.Address(0);
126 196 jshamlet
 
127
  signal Reg_Addr            : std_logic_vector(8 downto 1) := (others => '0');
128 278 jshamlet
  signal Reg_Sel             : std_logic := '0';
129
  signal Reg_Wr_En_d         : std_logic := '0';
130
  signal Reg_Wr_En_q         : std_logic := '0';
131
  signal TX_Ctl_Clk          : std_logic := '0';
132
  signal TX_Ctl_Len          : std_logic := '0';
133 196 jshamlet
 
134 278 jshamlet
  -- Dual-port memory
135 281 jshamlet
  signal DP_B_Addr           : std_logic_vector(8 downto 0) := (others => '0');
136
  signal DP_B_Wr_Data        : DATA_TYPE := x"00";
137
  signal DP_B_Wr_En          : std_logic := '0';
138
  signal DP_B_Rd_Data        : DATA_TYPE := x"00";
139 192 jshamlet
 
140 278 jshamlet
  -- Internal definitions
141
  constant SDLC_Flag         : DATA_TYPE := x"7E";
142 202 jshamlet
 
143 278 jshamlet
  constant CK_REGISTER       : DATA_TYPE := x"FE";
144
  constant TX_REGISTER       : DATA_TYPE := x"FF";
145
  constant CS_REGISTER       : DATA_TYPE := x"FE";
146
  constant RX_REGISTER       : DATA_TYPE := x"FF";
147 192 jshamlet
 
148 278 jshamlet
  constant TX_RESERVED_LOW   : integer := 0;
149
  constant TX_RESERVED_HIGH  : integer := 254;
150 192 jshamlet
 
151 278 jshamlet
  constant FLAG_DONE         : DATA_TYPE := x"FF";
152 192 jshamlet
 
153 278 jshamlet
  constant ERR_LENGTH        : DATA_TYPE := x"00";
154 192 jshamlet
 
155 278 jshamlet
  -- RAM Arbitration logic
156
  type DP_ARB_STATES is (PAUSE, IDLE,
157
                         PORT0_AD, PORT0_WR, PORT0_RD0, PORT0_RD1,
158
                         PORT1_AD, PORT1_WR, PORT1_RD0, PORT1_RD1  );
159
  signal DP_Arb_State        : DP_ARB_STATES := IDLE;
160
  signal DP_Last_Port        : std_logic := '0';
161 192 jshamlet
 
162 278 jshamlet
  signal DP_Port0_Addr       : DATA_TYPE := x"00";
163
  signal DP_Port0_RWn        : std_logic := '0';
164
  signal DP_Port0_WrData     : DATA_TYPE := x"00";
165
  signal DP_Port0_RdData     : DATA_TYPE := x"00";
166
  signal DP_Port0_Req        : std_logic := '0';
167
  signal DP_Port0_Ack        : std_logic := '0';
168 202 jshamlet
 
169 278 jshamlet
  signal DP_Port1_Addr       : DATA_TYPE := x"00";
170
  signal DP_Port1_RWn        : std_logic := '0';
171
  signal DP_Port1_WrData     : DATA_TYPE := x"00";
172
  signal DP_Port1_RdData     : DATA_TYPE := x"00";
173
  signal DP_Port1_Req        : std_logic := '0';
174
  signal DP_Port1_Ack        : std_logic := '0';
175
 
176
-- Clock generation
177
  constant DLY_VAL           : integer := integer(Clock_Frequency / (2.0 * BitClock_Frequency) );
178
  constant DLY_WDT           : integer := ceil_log2(DLY_VAL - 1);
179
  constant DLY_VEC           : std_logic_vector :=
180
                               conv_std_logic_vector( DLY_VAL - 1, DLY_WDT);
181
  signal BClk_Cntr           : std_logic_vector( DLY_WDT - 1 downto 0 ) := (others => '0');
182
 
183
  signal BClk_Adv            : std_logic := '0';
184
  signal BClk_Accum          : std_logic_vector(31 downto 0) := (others => '0');
185
  signal BClk_Div            : std_logic := '0';
186
  signal BClk_Okay_SR        : std_logic_vector(3 downto 0)  := (others => '0');
187
 
188
  signal BClk_SR             : std_logic_vector(2 downto 0)  := (others => '0');
189
 
190
  constant CLK_RATIO_R       : real := Clock_Frequency / (1.0 * BitClock_Frequency);
191
  constant CLK_DEVIATION_5P  : real := CLK_RATIO_R * 0.05;
192
  constant CLK_RATIO_ADJ_R   : real := CLK_RATIO_R + CLK_DEVIATION_5P;
193
  constant CLK_RATIO_ADJ_I   : integer := integer(CLK_RATIO_ADJ_R);
194
 
195
  constant Threshold_bits    : integer := ceil_log2(CLK_RATIO_ADJ_I);
196
  constant THRESHOLD         : std_logic_vector(Threshold_bits - 1 downto 0) :=
197
                        conv_std_logic_vector(CLK_RATIO_ADJ_I,Threshold_bits);
198
 
199
  signal RE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0) :=
200
                                (others => '0');
201
  signal FE_Threshold_Ctr    : std_logic_vector(Threshold_Bits - 1 downto 0) :=
202
                                (others => '0');
203
 
204
  signal Ref_In_SR           : std_logic_vector(2 downto 0) := (others => '0');
205
  alias  Ref_In_q1           is Ref_In_SR(1);
206
  alias  Ref_In_q2           is Ref_In_SR(2);
207
  signal Ref_In_RE           : std_logic := '0';
208
  signal Ref_In_FE           : std_logic := '0';
209
 
210
  signal BClk_RE             : std_logic := '0';
211
  signal BClk_FE             : std_logic := '0';
212
  signal BClk_Okay           : std_logic := '0';
213
 
214
-- Packet Transmit state logic
215 283 jshamlet
  type TX_FSM_STATES is ( INIT_FLAG, WR_CLOCK_STATE, WAIT_FOR_UPDATE,
216 278 jshamlet
                          RD_TX_REGISTER, TX_INIT,
217
                          TX_START_FLAG, TX_WAIT_START_FLAG,
218
                          TX_MESG_DATA, TX_ADV_ADDR, TX_WAIT_MESG_DATA,
219 282 jshamlet
                          TX_CRC_LB_WR, TX_WAIT_CRC_LB,
220
                          TX_CRC_UB_WR, TX_WAIT_CRC_UB,
221 278 jshamlet
                          TX_STOP_FLAG, TX_WAIT_STOP_FLAG, TX_SET_FLAG );
222
 
223
  signal TX_FSM_State        : TX_FSM_STATES := WR_CLOCK_STATE;
224
  signal TX_Length           : DATA_TYPE := x"00";
225
 
226
  signal BClk_q1, BClk_CoS   : std_logic := '0';
227
  signal TX_Int_pend         : std_logic := '0';
228
 
229
  signal TX_Wr_En            : std_logic := '0';
230
  signal TX_Wr_Flag          : std_logic := '0';
231
  signal TX_Wr_Data          : DATA_TYPE := x"00";
232
  signal TX_Req_Next         : std_logic := '0';
233
 
234
  signal TX_CRC_Clr          : std_logic := '0';
235
  signal TX_CRC_En           : std_logic := '0';
236
  signal TX_CRC_Data         : CRC_TYPE  := x"0000";
237
  signal TX_CRC_Valid        : std_logic := '0';
238
 
239
  alias  TX_CRC_Data_LB      is TX_CRC_Data(7 downto 0);
240
  alias  TX_CRC_Data_UB      is TX_CRC_Data(15 downto 8);
241
 
242
  signal TX_Arm              : std_logic := '0';
243
  signal TX_Flag             : std_logic := '0';
244
  signal TX_Buffer           : std_logic_vector(8 downto 0) := (others => '0');
245
  alias  TX_Buffer_Flag      is TX_Buffer(8);
246
  alias  TX_Buffer_Data      is TX_Buffer(7 downto 0);
247
 
248
-- SDLC transmitter
249
  type TX_STATES is (INIT, IDLE, XMIT, SPACE, TERM, LD_NEXT);
250
  signal TX_State            : TX_STATES := INIT;
251
 
252
  signal TX_ShftReg          : DATA_TYPE := (others => '0');
253
  signal TX_Next             : std_logic := '0';
254
  signal TX_BitStuff         : std_logic_vector(4 downto 0) := (others => '0');
255
  signal TX_BitCntr          : std_logic_vector(3 downto 0) := (others => '0');
256
  alias  TX_BitSel           is TX_BitCntr(2 downto 0);
257
  alias  TX_Term             is TX_BitCntr(3);
258
 
259
-- SDLC receiver
260
  signal RX_LatchEn_SR       : std_logic_vector(Clock_Offset downto 0) := (others => '0');
261
  alias  RX_LatchEn_M        is RX_LatchEn_SR(Clock_Offset);
262
  alias  RX_LatchEn_S        is BClk_RE;
263
  signal RX_LatchEn          : std_logic := '0';
264
 
265
  signal RX_Serial_SR        : std_logic_vector(1 downto 0) := (others => '0');
266
  alias  RX_Serial           is RX_Serial_SR(1);
267
 
268
  type RX_STATES is (INIT, IDLE, RCV_DATA, SKIP_ZERO, WRITE_DATA);
269
  signal RX_State            : RX_STATES := INIT;
270
  signal RX_Buffer           : DATA_TYPE := x"00";
271
  signal RX_BitStuff_SR      : std_logic_vector(4 downto 0) := (others => '0');
272
  signal RX_BitCntr          : std_logic_vector(3 downto 0) := (others => '0');
273
  alias  RX_BitSel           is RX_BitCntr(2 downto 0);
274
  alias  RX_Term             is RX_BitCntr(3);
275
 
276
  signal RX_Flag_SR          : DATA_TYPE := x"00";
277
 
278
  signal RX_Idle_Cntr        : std_logic_vector(2 downto 0) := (others => '0');
279
 
280
  signal RX_Valid            : std_logic := '0';
281
  signal RX_Flag             : std_logic := '0';
282
  signal RX_Data             : DATA_TYPE := x"00";
283
  signal RX_Idle             : std_logic := '0';
284
 
285
-- Packet detection logic
286
  type PACKET_STATES is (IDLE, FRAME_START, FRAME_DATA, FRAME_STOP );
287
  signal Pkt_State           : PACKET_STATES := IDLE;
288
  signal First_Byte          : std_logic := '0';
289
 
290
  signal RX_Frame_Start      : std_logic := '0';
291
  signal RX_Frame_Stop       : std_logic := '0';
292
  signal RX_Frame_Valid      : std_logic := '0';
293
  signal RX_Frame_Data       : DATA_TYPE := x"00";
294
 
295
-- Receive data CRC calculation
296
  signal RX_CRC_Valid        : std_logic := '0';
297
  signal RX_CRC_Data         : CRC_TYPE  := x"0000";
298
 
299
  type CRC_HISTORY is array(0 to 2) of CRC_TYPE;
300
  signal RX_CRC_Hist         : CRC_HISTORY := (x"0000",x"0000",x"0000");
301
  alias  RX_CRC_Calc         is RX_CRC_Hist(2);
302
 
303
  signal RX_CRC_Rcvd         : CRC_TYPE  := x"0000";
304
  alias  RX_CRC_Rcvd_LB      is RX_CRC_Rcvd(7 downto 0);
305
  alias  RX_CRC_Rcvd_UB      is RX_CRC_Rcvd(15 downto 8);
306
 
307
-- Packet receive state logic
308
  type RX_FSM_STATES is ( WAIT_FOR_CLOCK, WAIT_FOR_FLAG,
309
                          RX_MESG_DATA, RX_WR_DATA,
310
                          RX_CRC_LB_RD, RX_CRC_UB_RD,
311
                          RX_WR_CRC, RX_WR_COUNT );
312
 
313
  signal RX_FSM_State        : RX_FSM_STATES := WAIT_FOR_CLOCK;
314
 
315
  signal RX_Length           : DATA_TYPE := x"00";
316
 
317 192 jshamlet
begin
318 278 jshamlet
 
319
-- ***************************************************************************
320
-- *          Open8 Bus Interface and Control Register Detection             *
321
-- ***************************************************************************
322
 
323
  -- This decode needs to happen immediately, to give the RAM a chance to
324
  --  do the lookup before we have to set Rd_Data
325
  Base_Addr_Match            <= '1' when Base_Addr = CPU_Upper_Addr else '0';
326
  Reg_Wr_En_d                <= Base_Addr_Match and
327
                                Open8_Bus.Wr_En and
328
                                Write_Qual;
329
 
330
  DP_A_Wr_En                 <= Base_Addr_Match and
331
                                Open8_Bus.Wr_En and
332
                                Write_Qual;
333
 
334
  DP_A_Rd_En_d               <= Base_Addr_Match and Open8_Bus.Rd_En;
335
 
336
  CPU_IF_proc: process( Reset, Clock )
337
  begin
338
    if( Reset = Reset_Level )then
339
      Reg_Addr               <= (others => '0');
340
      Reg_Wr_En_q            <= '0';
341
      TX_Ctl_Clk             <= '0';
342
      TX_Ctl_Len             <= '0';
343
      DP_A_Rd_En_q           <= '0';
344
      Rd_Data                <= OPEN8_NULLBUS;
345
    elsif( rising_edge(Clock) )then
346
      Reg_Addr               <= Reg_Upper_Addr;
347
      Reg_Sel                <= Reg_Lower_Addr;
348
      Reg_Wr_En_q            <= Reg_Wr_En_d;
349
 
350
      TX_Ctl_Clk             <= '0';
351
      TX_Ctl_Len             <= '0';
352
      if( Reg_Addr = Reg_Sub_Addr )then
353
        TX_Ctl_Clk           <= Reg_Wr_En_q and not Reg_Sel;
354
        TX_Ctl_Len           <= Reg_Wr_En_q and Reg_Sel;
355
      end if;
356
 
357
      DP_A_Rd_En_q           <= DP_A_Rd_En_d;
358
      Rd_Data                <= OPEN8_NULLBUS;
359
      if( DP_A_Rd_En_q = '1' )then
360
        Rd_Data              <= DP_A_Rd_Data;
361
      end if;
362
    end if;
363
  end process;
364
 
365
-- ***************************************************************************
366
-- *                     Shared Dual-Port Memory                             *
367
-- ***************************************************************************
368
 
369
  U_RAM : entity work.sdlc_dp512b_ram
370
  port map(
371
    clock                    => Clock,
372
    address_a                => DP_A_Addr,
373
    address_b                => DP_B_Addr,
374
    data_a                   => DP_A_Wr_Data,
375
    data_b                   => DP_B_Wr_Data,
376
    wren_a                   => DP_A_Wr_En,
377
    wren_b                   => DP_B_Wr_En,
378
    q_a                      => DP_A_Rd_Data,
379
    q_b                      => DP_B_Rd_Data
380
  );
381
 
382 202 jshamlet
-- ***************************************************************************
383 278 jshamlet
-- *                     Memory Arbitration                                  *
384 202 jshamlet
-- ***************************************************************************
385
 
386 278 jshamlet
  RAM_Arbitration_proc: process( Clock, Reset )
387
  begin
388
    if( Reset = Reset_Level )then
389
      DP_Arb_State           <= IDLE;
390
      DP_Last_Port           <= '0';
391 280 jshamlet
      DP_B_Addr              <= (others => '0');
392
      DP_B_Wr_Data           <= x"00";
393
      DP_B_Wr_En             <= '0';
394 278 jshamlet
      DP_Port0_RdData        <= x"00";
395
      DP_Port0_Ack           <= '0';
396
      DP_Port1_RdData        <= x"00";
397
      DP_Port1_Ack           <= '0';
398
    elsif( rising_edge(Clock) )then
399
      DP_Port0_Ack           <= '0';
400
      DP_Port1_Ack           <= '0';
401 280 jshamlet
      DP_B_Wr_En               <= '0';
402 192 jshamlet
 
403 278 jshamlet
      case( DP_Arb_State )is
404
        when IDLE =>
405
          if( DP_Port0_Req = '1' and (DP_Port1_Req = '0' or DP_Last_Port = '1') )then
406
            DP_Arb_State     <= PORT0_AD;
407
          elsif( DP_Port1_Req = '1' and (DP_Port0_Req = '0' or DP_Last_Port = '0') )then
408
            DP_Arb_State     <= PORT1_AD;
409
          end if;
410 244 jshamlet
 
411 278 jshamlet
        when PORT0_AD =>
412
          DP_Last_Port       <= '0';
413 280 jshamlet
          DP_B_Addr          <= '0' & DP_Port0_Addr;
414
          DP_B_Wr_Data       <= DP_Port0_WrData;
415
          DP_B_Wr_En         <= not DP_Port0_RWn;
416 278 jshamlet
          if( DP_Port0_RWn = '1' )then
417
            DP_Arb_State     <= PORT0_RD0;
418
          else
419
            DP_Port0_Ack     <= '1';
420
            DP_Arb_State     <= PORT0_WR;
421
          end if;
422 244 jshamlet
 
423 278 jshamlet
        when PORT0_WR =>
424
          DP_Arb_State       <= IDLE;
425
 
426
        when PORT0_RD0 =>
427
          DP_Arb_State       <= PORT0_RD1;
428
 
429
        when PORT0_RD1 =>
430
          DP_Port0_Ack       <= '1';
431 280 jshamlet
          DP_Port0_RdData    <= DP_B_Rd_Data;
432 278 jshamlet
          DP_Arb_State       <= PAUSE;
433
 
434
        when PORT1_AD =>
435
          DP_Last_Port       <= '1';
436 280 jshamlet
          DP_B_Addr          <= '1' & DP_Port1_Addr;
437
          DP_B_Wr_Data       <= DP_Port1_WrData;
438
          DP_B_Wr_En         <= not DP_Port1_RWn;
439 278 jshamlet
          if( DP_Port0_RWn = '1' )then
440
            DP_Arb_State     <= PORT1_RD0;
441
          else
442
            DP_Port1_Ack     <= '1';
443
            DP_Arb_State     <= PORT1_WR;
444
          end if;
445
 
446
        when PORT1_WR =>
447
          DP_Arb_State       <= IDLE;
448
 
449
        when PORT1_RD0 =>
450
          DP_Arb_State       <= PORT1_RD1;
451
 
452
        when PORT1_RD1 =>
453
          DP_Port1_Ack       <= '1';
454 280 jshamlet
          DP_Port1_RdData    <= DP_B_Rd_Data;
455 278 jshamlet
          DP_Arb_State       <= PAUSE;
456
 
457
        when PAUSE =>
458
          DP_Arb_State       <= IDLE;
459
 
460
        when others => null;
461
 
462
      end case;
463
    end if;
464
  end process;
465
 
466
-- ****************************************************************************
467
-- * Bit clock generation                                                     *
468
-- ****************************************************************************
469
 
470
Clock_Master: if( Set_As_Master )generate
471
 
472
  Clock_Gen_proc: process( Clock, Reset )
473 192 jshamlet
  begin
474
    if( Reset = Reset_Level )then
475 278 jshamlet
      BClk_Cntr              <= DLY_VEC;
476
      BClk_Adv               <= '0';
477
      BClk_Accum             <= (others => '0');
478
      BClk_Div               <= '0';
479
      BClk_Okay_SR           <= (others => '0');
480
      BClk_RE                <= '0';
481
      BClk_FE                <= '0';
482
      SDLC_MClk              <= '0';
483
    elsif( rising_edge( Clock ) )then
484
      BClk_Cntr              <= BClk_Cntr - 1;
485
      BClk_Adv               <= '0';
486
      if( or_reduce(BClk_Cntr) = '0' )then
487
        BClk_Cntr            <= DLY_VEC;
488
        BClk_Adv             <= '1';
489
        BClk_Okay_SR         <= BClk_Okay_SR(2 downto 0) & '1';
490
      end if;
491
      BClk_Accum             <= BClk_Accum + BClk_Adv;
492
      BClk_Div               <= BClk_Div xor BClk_Adv;
493
      BClk_RE                <= (not BClk_Div) and BClk_Adv;
494
      BClk_FE                <= BClk_Div and BClk_Adv;
495
      SDLC_MClk              <= BClk_Div;
496
    end if;
497
  end process;
498
 
499
  BClk_Okay                  <= BClk_Okay_SR(3);
500
 
501
end generate;
502
 
503
Clock_Slave: if( not Set_As_Master )generate
504
 
505
  Clock_Edge_proc: process( Clock, Reset )
506
  begin
507
    if( Reset = Reset_Level )then
508
      BClk_SR                <= (others => '0');
509
      BClk_FE                <= '0';
510
      BClk_RE                <= '0';
511 192 jshamlet
    elsif( rising_edge(Clock) )then
512 278 jshamlet
      BClk_SR                <= BClk_SR(1 downto 0) & SDLC_SClk;
513
      BClk_FE                <= BClk_SR(2) and (not BClk_SR(1));
514
      BClk_RE                <= (not BClk_SR(2)) and BClk_SR(1);
515
    end if;
516
  end process;
517 192 jshamlet
 
518 278 jshamlet
  SDLC_MClk                  <= '0';
519
 
520
  Clock_Detect_proc: process( Clock, Reset )
521
  begin
522
    if( Reset = Reset_Level )then
523
      Ref_In_SR              <= (others => '0');
524
      Ref_In_RE              <= '0';
525
      Ref_In_FE              <= '0';
526
      RE_Threshold_Ctr       <= (others => '0');
527
      FE_Threshold_Ctr       <= (others => '0');
528
      BClk_Okay              <= '0';
529
 
530
    elsif( rising_edge(Clock) )then
531
      Ref_In_SR              <= Ref_In_SR(1 downto 0) & SDLC_SClk;
532
      Ref_In_RE              <= Ref_In_q1 and (not Ref_In_q2);
533
      Ref_In_FE              <= (not Ref_In_q1) and Ref_In_q2;
534
 
535
      RE_Threshold_Ctr       <= RE_Threshold_Ctr - 1;
536
      if( Ref_In_RE = '1' )then
537
        RE_Threshold_Ctr     <= THRESHOLD;
538
      elsif( or_reduce(RE_Threshold_Ctr) = '0' )then
539
        RE_Threshold_Ctr     <= (others => '0');
540 192 jshamlet
      end if;
541
 
542 278 jshamlet
      FE_Threshold_Ctr       <= FE_Threshold_Ctr - 1;
543
      if( Ref_In_FE = '1' )then
544
        FE_Threshold_Ctr     <= THRESHOLD;
545
      elsif( or_reduce(FE_Threshold_Ctr) = '0' )then
546
        FE_Threshold_Ctr     <= (others => '0');
547 192 jshamlet
      end if;
548 278 jshamlet
 
549
 
550
      BClk_Okay              <= or_reduce(RE_Threshold_Ctr) and
551
                                or_reduce(FE_Threshold_Ctr);
552
 
553 192 jshamlet
    end if;
554
  end process;
555
 
556 278 jshamlet
end generate;
557
 
558 202 jshamlet
-- ***************************************************************************
559 278 jshamlet
-- *                     Serial Transmit Path                                *
560 202 jshamlet
-- ***************************************************************************
561
 
562 278 jshamlet
  TX_Packet_RAM_proc: process( Reset, Clock )
563
  begin
564
    if( Reset = Reset_Level )then
565
      TX_FSM_State           <= INIT_FLAG;
566 192 jshamlet
 
567 278 jshamlet
      DP_Port0_Addr          <= x"00";
568
      DP_Port0_RWn           <= '1';
569
      DP_Port0_WrData        <= x"00";
570
      DP_Port0_Req           <= '0';
571 202 jshamlet
 
572 278 jshamlet
      TX_Length              <= x"00";
573 202 jshamlet
 
574 278 jshamlet
      TX_Wr_En               <= '0';
575
      TX_Wr_Flag             <= '0';
576
      TX_Wr_Data             <= x"00";
577 202 jshamlet
 
578 278 jshamlet
      TX_CRC_Clr             <= '0';
579
      TX_CRC_En              <= '0';
580 192 jshamlet
 
581 278 jshamlet
      BClk_q1                <= '0';
582
      BClk_CoS               <= '0';
583 202 jshamlet
 
584 278 jshamlet
      TX_Int_pend            <= '0';
585
      TX_Interrupt           <= '0';
586 202 jshamlet
 
587 278 jshamlet
    elsif( rising_edge(Clock) )then
588
 
589
      DP_Port0_RWn           <= '1';
590
      DP_Port0_WrData        <= x"00";
591
      DP_Port0_Req           <= '0';
592
 
593
      TX_Wr_En               <= '0';
594
      TX_Wr_Flag             <= '0';
595
      TX_Wr_Data             <= x"00";
596
 
597
      TX_CRC_Clr             <= '0';
598
      TX_CRC_En              <= '0';
599
 
600
      BClk_q1                <= BClk_Okay;
601
      BClk_CoS               <= BClk_q1 xor BClk_Okay;
602
 
603
      TX_Interrupt           <= '0';
604
 
605
      case( TX_FSM_State )is
606
 
607
        when INIT_FLAG =>
608
          DP_Port0_Addr      <= TX_REGISTER;
609
          DP_Port0_Req       <= '1';
610
          DP_Port0_WrData    <= FLAG_DONE;
611
          DP_Port0_RWn       <= '0';
612
          if( DP_Port0_Ack = '1' )then
613
            DP_Port0_Req     <= '0';
614
            TX_FSM_State     <= WR_CLOCK_STATE;
615
          end if;
616
 
617
        when WR_CLOCK_STATE =>
618
          DP_Port0_Addr      <= CK_REGISTER;
619
          DP_Port0_Req       <= '1';
620
          DP_Port0_WrData    <= (others => BClk_Okay);
621
          DP_Port0_RWn       <= '0';
622
          if( DP_Port0_Ack = '1' )then
623
            TX_Interrupt     <= TX_Int_pend;
624
            TX_Int_pend      <= '0';
625
            DP_Port0_Req     <= '0';
626 283 jshamlet
            TX_FSM_State     <= WAIT_FOR_UPDATE;
627 278 jshamlet
          end if;
628
 
629 283 jshamlet
        when WAIT_FOR_UPDATE =>
630
          if( TX_Ctl_Clk = '1' )then
631
            TX_FSM_State     <= WR_CLOCK_STATE;
632 278 jshamlet
          end if;
633 283 jshamlet
          if( TX_Ctl_Len = '1' and BClk_Okay = '1' )then
634
            TX_FSM_State     <= RD_TX_REGISTER;
635
          end if;
636 278 jshamlet
 
637
        when RD_TX_REGISTER =>
638
          DP_Port0_Addr      <= TX_REGISTER;
639
          DP_Port0_Req       <= '1';
640
          if( DP_Port0_Ack = '1' )then
641
            DP_Port0_Req     <= '0';
642
            TX_Length        <= DP_Port0_RdData;
643
            TX_FSM_State     <= TX_INIT;
644
          end if;
645
 
646
        when TX_INIT =>
647
          TX_FSM_State       <= WAIT_FOR_UPDATE;
648
          if( TX_Length > TX_RESERVED_LOW and
649
              TX_Length < TX_RESERVED_HIGH )then
650
            TX_CRC_Clr       <= '1';
651
            TX_FSM_State     <= TX_START_FLAG;
652
          end if;
653
 
654
        when TX_START_FLAG =>
655
          TX_Wr_En           <= '1';
656
          TX_Wr_Flag         <= '1';
657
          TX_Wr_Data         <= SDLC_FLAG;
658
          TX_FSM_State       <= TX_WAIT_START_FLAG;
659
 
660
        when TX_WAIT_START_FLAG =>
661
          if( TX_Req_Next = '1' )then
662
            DP_Port0_Addr    <= x"00";
663
            TX_FSM_State     <= TX_ADV_ADDR;
664
          end if;
665
 
666
        when TX_ADV_ADDR =>
667
          DP_Port0_Req       <= '1';
668
          if( DP_Port0_Ack = '1' )then
669
            DP_Port0_Req     <= '0';
670
            DP_Port0_Addr    <= DP_Port0_Addr + 1;
671
            TX_Length        <= TX_Length - 1;
672
            TX_FSM_State     <= TX_MESG_DATA;
673
          end if;
674
 
675
        when TX_MESG_DATA =>
676
          TX_Wr_En           <= '1';
677
          TX_Wr_Data         <= DP_Port0_RdData;
678
          TX_CRC_En          <= '1';
679
          TX_FSM_State       <= TX_WAIT_MESG_DATA;
680
 
681
        when TX_WAIT_MESG_DATA =>
682
          if( TX_Req_Next = '1' )then
683
            TX_FSM_State     <= TX_ADV_ADDR;
684
            if( TX_Length = 0 )then
685
              TX_FSM_State   <= TX_CRC_LB_WR;
686
            end if;
687
          end if;
688
 
689
        when TX_CRC_LB_WR =>
690
          TX_Wr_En           <= '1';
691
          TX_Wr_Data         <= TX_CRC_Data_LB;
692 282 jshamlet
          TX_FSM_State       <= TX_WAIT_CRC_LB;
693 278 jshamlet
 
694 282 jshamlet
        when TX_WAIT_CRC_LB =>
695 278 jshamlet
          if( TX_Req_Next = '1' )then
696
              TX_FSM_State   <= TX_CRC_UB_WR;
697
          end if;
698
 
699
        when TX_CRC_UB_WR =>
700
          TX_Wr_En           <= '1';
701
          TX_Wr_Data         <= TX_CRC_Data_UB;
702 282 jshamlet
          TX_FSM_State       <= TX_WAIT_CRC_UB;
703 278 jshamlet
 
704 282 jshamlet
        when TX_WAIT_CRC_UB =>
705 278 jshamlet
          if( TX_Req_Next = '1' )then
706
              TX_FSM_State   <= TX_STOP_FLAG;
707
          end if;
708
 
709
        when TX_STOP_FLAG =>
710
          TX_Wr_En           <= '1';
711
          TX_Wr_Flag         <= '1';
712
          TX_Wr_Data         <= SDLC_FLAG;
713
          TX_FSM_State       <= TX_WAIT_STOP_FLAG;
714
 
715
        when TX_WAIT_STOP_FLAG =>
716
          if( TX_Req_Next = '1' )then
717
            TX_FSM_State     <= TX_SET_FLAG;
718
          end if;
719
 
720
        when TX_SET_FLAG =>
721
          DP_Port0_Addr      <= TX_REGISTER;
722
          DP_Port0_Req       <= '1';
723
          DP_Port0_WrData    <= FLAG_DONE;
724
          DP_Port0_RWn       <= '0';
725
          if( DP_Port0_Ack = '1' )then
726
            DP_Port0_Req     <= '0';
727
            TX_FSM_State     <= WAIT_FOR_UPDATE;
728
          end if;
729
 
730
        when others => null;
731
      end case;
732
 
733
      if( BClk_CoS = '1' )then
734
        TX_Int_pend          <= '1';
735
        TX_FSM_State         <= WR_CLOCK_STATE;
736
      end if;
737
 
738
    end if;
739
  end process;
740
 
741 202 jshamlet
  U_TX_CRC : entity work.sdlc_crc16_ccitt
742
  generic map(
743
    Poly_Init                => Poly_Init,
744
    Reset_Level              => Reset_Level
745
  )
746
  port map(
747
    Clock                    => Clock,
748
    Reset                    => Reset,
749 192 jshamlet
    --
750 202 jshamlet
    Clear                    => TX_CRC_Clr,
751
    Wr_En                    => TX_CRC_En,
752
    Wr_Data                  => TX_Wr_Data,
753 192 jshamlet
    --
754 202 jshamlet
    CRC16_Valid              => TX_CRC_Valid,
755
    CRC16_Out                => TX_CRC_Data
756 192 jshamlet
  );
757
 
758 278 jshamlet
  TX_Serial_proc: process( Clock, Reset )
759
  begin
760
    if( Reset = Reset_Level )then
761
      TX_State               <= IDLE;
762
      SDLC_Out               <= '1';
763
      TX_Arm                 <= '0';
764
      TX_Buffer              <= (others => '0');
765
      TX_Flag                <= '0';
766
      TX_ShftReg             <= (others => '0');
767
      TX_BitStuff            <= (others => '0');
768
      TX_BitCntr             <= (others => '1');
769
      TX_Req_Next               <= '0';
770
    elsif( rising_edge(Clock) )then
771 192 jshamlet
 
772 278 jshamlet
      if( TX_Wr_En = '1' and TX_Arm = '0')then
773
        TX_Arm               <= '1';
774
        TX_Buffer_Flag       <= TX_Wr_Flag;
775
        TX_Buffer_Data       <= TX_Wr_Data;
776
      end if;
777
 
778
      TX_Req_Next               <= '0';
779
 
780
      case( TX_State )is
781
        when INIT =>
782
          SDLC_Out           <= '1';
783
          TX_State           <= IDLE;
784
 
785
        when IDLE =>
786
          SDLC_Out           <= '1';
787
          if( TX_Arm = '1' and BClk_FE = '1' )then
788
            TX_Arm           <= '0';
789
            TX_BitCntr       <= (others => '0');
790
            TX_BitStuff      <= (others => '0');
791
            TX_Flag          <= TX_Buffer_Flag;
792
            TX_ShftReg       <= TX_Buffer_Data;
793
            TX_Req_Next      <= '1';
794
            TX_State         <= XMIT;
795
          end if;
796
 
797
        when XMIT =>
798
          SDLC_Out           <= TX_ShftReg(conv_integer(TX_BitSel));
799
          TX_BitCntr         <= TX_BitCntr + BClk_FE;
800
          if( BClk_RE = '1' )then
801
            TX_BitStuff      <= TX_BitStuff(3 downto 0) &
802
                                TX_ShftReg(conv_integer(TX_BitSel));
803
          end if;
804
          if( BClk_FE = '1' )then
805
            if( TX_BitCntr >= 7 )then
806
              TX_State       <= TERM;
807
            elsif( and_reduce(TX_BitStuff) = '1' and TX_Flag = '0' )then
808
              TX_BitStuff    <= (others => '0');
809
              TX_State       <= SPACE;
810
            else
811
              TX_BitCntr     <= TX_BitCntr + 1;
812
            end if;
813
          end if;
814
 
815
        when SPACE =>
816
          SDLC_Out           <= '0';
817
          if( BClk_FE = '1' )then
818
            TX_State         <= XMIT;
819
          end if;
820
 
821
        when TERM =>
822
          if( TX_Arm = '1' )then
823
            TX_State         <= LD_NEXT;
824
          else
825
            TX_State         <= IDLE;
826
          end if;
827
 
828
        when LD_NEXT =>
829
          TX_Arm             <= '0';
830
          TX_BitCntr         <= (others => '0');
831
          TX_Flag            <= TX_Buffer_Flag;
832
          TX_ShftReg         <= TX_Buffer_Data;
833
          TX_Req_Next        <= '1';
834
          TX_State           <= XMIT;
835
          if( and_reduce(TX_BitStuff) = '1' and TX_Flag = '0' )then
836
            TX_BitStuff      <= (others => '0');
837
            TX_State         <= SPACE;
838
          end if;
839
 
840
        when others => null;
841
      end case;
842
 
843
      if( BClk_Okay = '0' )then
844
        TX_State                <= INIT;
845
      end if;
846
 
847
    end if;
848
  end process;
849
 
850 202 jshamlet
-- ***************************************************************************
851
-- *                     Serial Receive Path                                 *
852
-- ***************************************************************************
853 192 jshamlet
 
854 278 jshamlet
IF_Is_Master: if( Set_As_Master )generate
855 192 jshamlet
 
856 278 jshamlet
  Input_proc: process( Clock, Reset )
857
  begin
858
    if( Reset = Reset_Level )then
859
      RX_LatchEn_SR          <= (others => '0');
860
      RX_Serial_SR           <= (others => '0');
861
    elsif( rising_edge(Clock) )then
862
      RX_LatchEn_SR          <= RX_LatchEn_SR(Clock_Offset - 1 downto 0) & BClk_RE;
863
      RX_Serial_SR           <= RX_Serial_SR(0) & SDLC_In;
864
    end if;
865
  end process;
866 202 jshamlet
 
867 278 jshamlet
  RX_LatchEn                 <= RX_LatchEn_M;
868
 
869
end generate;
870
 
871
IF_Is_Slave: if( not Set_As_Master )generate
872
 
873
  Input_proc: process( Clock, Reset )
874
  begin
875
    if( Reset = Reset_Level )then
876
      RX_Serial_SR           <= (others => '0');
877
    elsif( rising_edge(Clock) )then
878
      RX_Serial_SR           <= RX_Serial_SR(0) & SDLC_In;
879
    end if;
880
  end process;
881
 
882
  RX_LatchEn                 <= RX_LatchEn_S;
883
 
884
end generate;
885
 
886
  RX_Serial_proc: process( Clock, Reset )
887
  begin
888
    if( Reset = Reset_Level )then
889
 
890
      RX_BitStuff_SR         <= (others => '0');
891
      RX_Flag_SR             <= (others => '0');
892
      RX_Idle_Cntr           <= (others => '0');
893
 
894
      RX_State               <= IDLE;
895
      RX_Idle                <= '0';
896
 
897
      RX_Buffer              <= (others => '0');
898
      RX_BitCntr             <= (others => '0');
899
 
900
      RX_Valid               <= '0';
901
      RX_Flag                <= '0';
902
      RX_Data                <= (others => '0');
903
 
904
    elsif( rising_edge(Clock) )then
905
 
906
      if( RX_LatchEn = '1' )then
907
        RX_Flag_SR           <= RX_Flag_SR(6 downto 0) & RX_Serial;
908
        if( RX_State = IDLE )then
909
          RX_Flag_SR         <= (others => '0');
910
        end if;
911
 
912
        RX_Idle_Cntr         <= RX_Idle_Cntr + RX_Serial;
913
        if( and_reduce(RX_Idle_Cntr) = '1' )then
914
          RX_Idle_Cntr       <= "111";
915
        end if;
916
      end if;
917
 
918
      if( RX_Serial = '0' )then
919
        RX_Idle_Cntr         <= (others => '0');
920
      end if;
921
 
922
      RX_Valid               <= '0';
923
      RX_Flag                <= '0';
924
      RX_Idle                <= '0';
925
 
926
      case( RX_State )is
927
 
928
        when INIT =>
929
          RX_Idle            <= '1';
930
          RX_State           <= IDLE;
931
 
932
        when IDLE =>
933
          RX_Idle            <= '1';
934
          RX_BitCntr         <= (others => '0');
935
          RX_BitStuff_SR     <= (others => '0');
936
          if( RX_Serial = '0' )then
937
            RX_State         <= RCV_DATA;
938
          end if;
939
 
940
        when RCV_DATA =>
941
          if( RX_Term = '1' )then
942
            RX_State         <= WRITE_DATA;
943
          end if;
944
          if( RX_LatchEn = '1' )then
945
            RX_Buffer(conv_integer(RX_BitSel)) <= RX_Serial;
946
            RX_BitStuff_SR   <= RX_BitStuff_SR(3 downto 0) & RX_Serial;
947
            RX_BitCntr       <= RX_BitCntr + 1;
948
 
949
            if( and_reduce(RX_BitStuff_SR) = '1' )then
950
              RX_BitStuff_SR <= (others => '0');
951
              if( RX_Serial = '0' )then
952
                RX_BitCntr   <= RX_BitCntr;
953
                RX_State     <= SKIP_ZERO;
954
              end if;
955
            end if;
956
          end if;
957
 
958
        when SKIP_ZERO =>
959
          RX_State           <= RCV_DATA;
960
 
961
        when WRITE_DATA =>
962
          RX_BitCntr         <= (others => '0');
963
          RX_Valid           <= '1';
964
          RX_Data            <= RX_Buffer;
965
          if( RX_Flag_SR = SDLC_Flag )then
966
            RX_Flag          <= '1';
967
          end if;
968
          RX_State           <= RCV_DATA;
969
 
970
        when others => null;
971
      end case;
972
 
973
      -- If we just shifted in the flag character, and the bit counter isn't
974
      --  0x0, then our bit counter is out of alignment. Reset it to zero so
975
      --  that the next word is clocked in correctly.
976
      if( RX_Flag_SR = SDLC_Flag and RX_BitCntr > 0 )then
977
         RX_BitCntr          <= (others => '0');
978
      end if;
979
 
980
      -- If the serial line goes idle (In the marking state for more than 7
981
      --  bit times), and the FSM isn't already in IDLE, force it to IDLE.
982
      if( and_reduce(RX_Idle_Cntr) = '1' and RX_State /= IDLE )then
983
        RX_State             <= IDLE;
984
      end if;
985
 
986
      -- If the bit clock is no longer valid, soft-reset to the INIT state.
987
      if( BClk_Okay = '0' )then
988
        RX_State             <= INIT;
989
      end if;
990
 
991
    end if;
992
  end process;
993
 
994
  Packet_Marker_proc: process( Clock, Reset )
995
  begin
996
    if( Reset = Reset_Level )then
997
      Pkt_State              <= IDLE;
998
      First_Byte             <= '0';
999
      RX_Frame_Start         <= '0';
1000
      RX_Frame_Stop          <= '0';
1001
      RX_Frame_Valid         <= '0';
1002
      RX_Frame_Data          <= x"00";
1003
    elsif( rising_edge(Clock) )then
1004
      RX_Frame_Start         <= '0';
1005
      RX_Frame_Stop          <= '0';
1006
      RX_Frame_Valid         <= '0';
1007
 
1008
      case( Pkt_State )is
1009
        when IDLE =>
1010
          if( RX_Valid = '1' and RX_Flag = '1' )then
1011
            Pkt_State        <= FRAME_START;
1012
          end if;
1013
 
1014
        when FRAME_START =>
1015
            if( RX_Valid = '1' and RX_Flag = '0' )then
1016
              RX_Frame_Start <= '1';
1017
              First_Byte     <= '1';
1018
              Pkt_State      <= FRAME_DATA;
1019
            end if;
1020
 
1021
        when FRAME_DATA =>
1022
          First_Byte         <= '0';
1023
          if( (RX_Valid = '1' and RX_Flag = '0') or
1024
            First_Byte = '1' )then
1025
            RX_Frame_Valid   <= '1';
1026
            RX_Frame_Data    <= RX_Data;
1027
          elsif( RX_Valid = '1' and RX_Flag = '1' )then
1028
            Pkt_State        <= FRAME_STOP;
1029
          end if;
1030
 
1031
        when FRAME_STOP =>
1032
          RX_Frame_Stop      <= not RX_Idle;
1033
          Pkt_State          <= IDLE;
1034
 
1035
        when others => null;
1036
      end case;
1037
 
1038
      if( RX_Idle = '1' and Pkt_State /= IDLE )then
1039
        Pkt_State            <= FRAME_STOP;
1040
      end if;
1041
 
1042
    end if;
1043
  end process;
1044
 
1045 192 jshamlet
  U_RX_CRC : entity work.sdlc_crc16_ccitt
1046
  generic map(
1047
    Poly_Init                => Poly_Init,
1048
    Reset_Level              => Reset_Level
1049
  )
1050
  port map(
1051
    Clock                    => Clock,
1052
    Reset                    => Reset,
1053
    --
1054 202 jshamlet
    Clear                    => RX_Frame_Start,
1055
    Wr_En                    => RX_Frame_Valid,
1056
    Wr_Data                  => RX_Frame_Data,
1057 192 jshamlet
    --
1058 202 jshamlet
    CRC16_Valid              => RX_CRC_Valid,
1059
    CRC16_Out                => RX_CRC_Data
1060 192 jshamlet
  );
1061
 
1062 278 jshamlet
  CRC_History_proc: process( Clock, Reset )
1063
  begin
1064
    if( Reset = Reset_Level )then
1065
      RX_CRC_Hist(0)         <= x"0000";
1066
      RX_CRC_Hist(1)         <= x"0000";
1067
      RX_CRC_Hist(2)         <= x"0000";
1068
    elsif( rising_edge(Clock) )then
1069
      if( RX_CRC_Valid = '1' )then
1070
        RX_CRC_Hist(2)       <= RX_CRC_Hist(1);
1071
        RX_CRC_Hist(1)       <= RX_CRC_Hist(0);
1072
        RX_CRC_Hist(0)       <= RX_CRC_Data;
1073
      end if;
1074
    end if;
1075
  end process;
1076 202 jshamlet
 
1077 278 jshamlet
  RX_Packet_RAM_proc: process( Reset, Clock )
1078
  begin
1079
    if( Reset = Reset_Level )then
1080
      RX_FSM_State           <= WAIT_FOR_CLOCK;
1081
 
1082
      DP_Port1_Addr          <= x"00";
1083
      DP_Port1_RWn           <= '1';
1084
      DP_Port1_WrData        <= x"00";
1085
      DP_Port1_Req           <= '0';
1086
 
1087
      RX_Length              <= x"00";
1088
 
1089
      RX_CRC_Rcvd            <= x"0000";
1090
 
1091
      RX_Interrupt           <= '0';
1092
 
1093
    elsif( rising_edge(Clock) )then
1094
 
1095
      DP_Port1_Addr          <= x"00";
1096
      DP_Port1_RWn           <= '1';
1097
      DP_Port1_WrData        <= x"00";
1098
      DP_Port1_Req           <= '0';
1099
 
1100
      RX_Interrupt           <= '0';
1101
 
1102
      case( RX_FSM_State )is
1103
 
1104
        when WAIT_FOR_CLOCK =>
1105
          RX_FSM_State       <= WAIT_FOR_FLAG;
1106
 
1107
        when WAIT_FOR_FLAG =>
1108
          if( RX_Frame_Start = '1' )then
1109
            RX_Length        <= x"00";
1110
            RX_FSM_State     <= RX_MESG_DATA;
1111
          end if;
1112
 
1113
        when RX_MESG_DATA =>
1114
          if( RX_Frame_Stop = '1' )then
1115
            RX_Length        <= RX_Length - 1;
1116
            RX_FSM_State         <= RX_CRC_UB_RD;
1117
          elsif( RX_Frame_Valid = '1' )then
1118
            RX_FSM_State     <= RX_WR_DATA;
1119
            if( RX_Length > 254 )then
1120
              RX_Length      <= ERR_LENGTH;
1121
              RX_FSM_State   <= RX_WR_COUNT;
1122
            end if;
1123
          end if;
1124
 
1125
        when RX_WR_DATA  =>
1126
          RX_Length          <= RX_Length + DP_Port1_Ack;
1127
          DP_Port1_Addr      <= RX_Length;
1128
          DP_Port1_WrData    <= RX_Frame_Data;
1129
          DP_Port1_RWn       <= '0';
1130
          DP_Port1_Req       <= '1';
1131
          if( DP_Port1_Ack = '1' )then
1132
            DP_Port1_Req     <= '0';
1133
            RX_FSM_State     <= RX_MESG_DATA;
1134
          end if;
1135
 
1136
        when RX_CRC_UB_RD =>
1137
          RX_Length          <= RX_Length - DP_Port1_Ack;
1138
          DP_Port1_Addr      <= RX_Length;
1139
          DP_Port1_Req       <= '1';
1140
          if( DP_Port1_Ack = '1' )then
1141
            DP_Port1_Req     <= '0';
1142
            RX_CRC_Rcvd_UB   <= DP_Port1_RdData;
1143
            RX_FSM_State     <= RX_CRC_LB_RD;
1144
          end if;
1145
 
1146
        when RX_CRC_LB_RD =>
1147
          DP_Port1_Addr      <= RX_Length;
1148
          DP_Port1_Req       <= '1';
1149
          if( DP_Port1_Ack = '1' )then
1150
            DP_Port1_Req     <= '0';
1151
            RX_CRC_Rcvd_LB   <= DP_Port1_RdData;
1152
            RX_FSM_State     <= RX_WR_CRC;
1153
          end if;
1154
 
1155
        when RX_WR_CRC =>
1156
          DP_Port1_Addr      <= CS_REGISTER;
1157
          DP_Port1_WrData    <= x"FF";
1158
          if( RX_CRC_Rcvd /= RX_CRC_Calc )then
1159
            DP_Port1_WrData  <= x"00";
1160
          end if;
1161
          DP_Port1_RWn       <= '0';
1162
          DP_Port1_Req       <= '1';
1163
          if( DP_Port1_Ack = '1' )then
1164
            DP_Port1_Req     <= '0';
1165
            RX_FSM_State     <= RX_WR_COUNT;
1166
          end if;
1167
 
1168
        when RX_WR_COUNT =>
1169
          DP_Port1_Addr      <= RX_REGISTER;
1170
          DP_Port1_WrData    <= RX_Length;
1171
          DP_Port1_RWn       <= '0';
1172
          DP_Port1_Req       <= '1';
1173
          if( DP_Port1_Ack = '1' )then
1174
            DP_Port1_Req     <= '0';
1175
            RX_Interrupt     <= '1';
1176
            RX_FSM_State     <= WAIT_FOR_FLAG;
1177
          end if;
1178
 
1179
        when others => null;
1180
      end case;
1181
 
1182
      if( BClk_Okay = '0' )then
1183
        RX_FSM_State         <= WAIT_FOR_FLAG;
1184
      end if;
1185
 
1186
    end if;
1187
  end process;
1188
 
1189 192 jshamlet
end architecture;

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