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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_spi_16b_tx.vhd] - Blame information for rev 279

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Line No. Rev Author Line
1 268 jshamlet
-- Copyright (c) 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL units : o8_spi_16b_tx
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-- Description: Transmits (only) a 16-bit word using a synchronous interface
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--              Clock_Polarity sets the clock state at idle
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--              Clock_Phase sets the clock edge data is shifted on
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--              Half_Period_Clks sets the number of CPU clocks used to generate
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--               a half-period tick that runs the transmit state machine.
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--              (Note that 2x this value is the full SPI period in CPU clocks)
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--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x0   AAAAAAAA Pending Word (7:0)                 (R/W)
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--   0x1   AAAAAAAA Pending Word (11:8)                (R/W)
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--   0x2   A------- Busy Flag / TX on Write            (R/W)
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      09/16/20 Initial version
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_spi_16b_tx is
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generic(
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  Clock_Polarity             : std_logic;
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  Clock_Phase                : std_logic;
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  Half_Period_Clks           : integer range 1 to integer'high;
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  Write_Qual                 : in  std_logic;
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  Rd_Data                    : out DATA_TYPE;
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  -- SPI
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  DOUT                       : out std_logic;
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  SCLK                       : out std_logic;
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  SYNC                       : out std_logic
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);
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end entity;
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architecture behave of o8_spi_16b_tx is
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  alias Clock                is Open8_Bus.Clock;
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  alias Reset                is Open8_Bus.Reset;
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  alias uSec_Tick            is Open8_Bus.uSec_Tick;
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  constant Clk_Div_i         : integer := Half_Period_Clks - 1;
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  constant Clk_Div_Bits      : integer := ceil_log2(Clk_Div_i);
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  constant CLK_DIV_VAL       : std_logic_vector(Clk_Div_Bits - 1 downto 0) :=
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                                conv_std_logic_vector(Clk_Div_i,Clk_Div_Bits);
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  signal HT_Cntr             : std_logic_vector(Clk_Div_Bits - 1 downto 0);
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  signal HT_Tick             : std_logic := '0';
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  constant User_Addr         : std_logic_vector(15 downto 2) := Address(15 downto 2);
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
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  signal Addr_Match          : std_logic;
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  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
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  signal Reg_Sel_q           : std_logic_vector(1 downto 0);
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  signal Wr_En_d             : std_logic := '0';
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  signal Wr_En_q             : std_logic := '0';
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  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
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  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal Rd_En_d             : std_logic := '0';
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  signal Rd_En_q             : std_logic := '0';
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  signal spi_xmit            : std_logic := '0';
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  type SPI_STATES is ( IDLE, ALIGN, SYNC_START, CLK_SETUP, CLK_HOLD, CLK_END, SYNC_END );
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  signal spi_state           : SPI_STATES;
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  signal spi_buffer          : std_logic_vector(15 downto 0) := x"0000";
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  alias  spi_buffer_lb       is spi_buffer(7 downto 0);
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  alias  spi_buffer_ub       is spi_buffer(15 downto 8);
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  signal bit_cntr            : std_logic_vector(3 downto 0) := x"0";
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  signal spi_busy            : std_logic := '0';
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
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  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Reg_Sel_q              <= "00";
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      Wr_En_q                <= '0';
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      Wr_Data_q              <= x"00";
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      Rd_En_q                <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
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      spi_buffer             <= (others => '0');
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      spi_xmit               <= '0';
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    elsif( rising_edge( Clock ) )then
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      Reg_Sel_q              <= Reg_Sel_d;
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      Wr_En_q                <= Wr_En_d;
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      Wr_Data_q              <= Wr_Data_d;
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      spi_xmit               <= '0';
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      if( Wr_En_q = '1' and Write_Qual = '1' )then
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        case( Reg_Sel_q )is
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          when "00" =>
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            spi_buffer_lb    <= Wr_Data_q;
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          when "01" =>
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            spi_buffer_ub    <= Wr_Data_q;
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          when "10" | "11" =>
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            spi_xmit         <= '1';
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          when others =>
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            null;
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        end case;
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      end if;
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      Rd_En_q                <= Rd_En_d;
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      Rd_Data                <= OPEN8_NULLBUS;
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      if( Rd_En_q = '1' )then
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        case( Reg_Sel_q )is
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          when "00" =>
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            Rd_Data          <= spi_buffer_lb;
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          when "01" =>
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            Rd_Data          <= spi_buffer_ub;
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          when "10" | "11" =>
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            Rd_Data          <= spi_busy & "0000000";
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          when others =>
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            null;
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        end case;
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      end if;
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    end if;
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  end process;
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  ADC_IO_FSM: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      spi_state              <= IDLE;
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      bit_cntr               <= (others => '0');
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      spi_busy               <= '0';
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      HT_Cntr                <= (others => '0');
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      HT_Tick                <= '0';
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      DOUT                   <= '0';
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      SCLK                   <= '0';
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      SYNC                   <= '1';
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    elsif( rising_edge(Clock) )then
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      HT_Cntr                <= HT_Cntr - 1;
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      HT_Tick                <= '0';
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      if( HT_Cntr = 0 )then
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        HT_Cntr              <= CLK_DIV_VAL;
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        HT_Tick              <= '1';
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      end if;
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      case( spi_state )is
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        when IDLE =>
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          DOUT               <= '0';
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          SCLK               <= Clock_Polarity;
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          SYNC               <= '1';
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          bit_cntr           <= x"F";
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          spi_busy           <= '0';
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          if( spi_xmit = '1' )then
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            spi_busy         <= '1';
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            spi_state        <= ALIGN;
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          end if;
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        when ALIGN =>
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          if( HT_Tick = '1' )then
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            spi_state        <= CLK_SETUP;
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            if( Clock_Phase = '1' )then
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              spi_state      <= SYNC_START;
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            end if;
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          end if;
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        when SYNC_START =>
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          SYNC               <= '0';
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          if( HT_Tick = '1' )then
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            spi_state        <= CLK_SETUP;
207
          end if;
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        when CLK_SETUP =>
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          SCLK               <= Clock_Polarity xor Clock_Phase;
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          DOUT               <= spi_buffer(conv_integer(bit_cntr));
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          SYNC               <= '0';
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          if( HT_Tick = '1' )then
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            spi_state        <= CLK_HOLD;
215
          end if;
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        when CLK_HOLD =>
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          SCLK               <= (not Clock_Polarity) xor Clock_Phase;
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          DOUT               <= spi_buffer(conv_integer(bit_cntr));
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          if( HT_Tick = '1' )then
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            bit_cntr         <= bit_cntr - 1;
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            spi_state        <= CLK_SETUP;
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            if( bit_cntr = 0 )then
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              spi_state      <= CLK_END;
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            end if;
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          end if;
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        when CLK_END =>
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          SCLK               <= Clock_Polarity;
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          if( Clock_Phase = '1' )then
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            SYNC             <= '1';
232
          end if;
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          if( HT_Tick = '1' )then
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            spi_state        <= SYNC_END;
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            if( Clock_Phase = '1' )then
236
              spi_state      <= IDLE;
237
            end if;
238
          end if;
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240
        when SYNC_END =>
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          SYNC               <= '1';
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          if( HT_Tick = '1' )then
243
            spi_state        <= IDLE;
244
          end if;
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        when others =>
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          null;
248
      end case;
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250
    end if;
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  end process;
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end architecture;

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